漏模板印刷优化的新思维

近几年漏模板设计逐渐从经验主义向以试验设计为基础的现代科学研究方法转变实现印刷质量的提升。现代技术对漏模板设计的方方面面提出了很高的要求，要兼顾单板上细间距器件和大间距器件的要求。而且，为了控制印锡量，工程师必需选择最好的漏模板开口设计、漏模板厚度、开口锥度，要决定是否需要电抛光；选择不同的漏模板制造技术，不同的制作技术关系到不同的制造成本。业界对这些问题缺乏深入认识，促使我们进行试验深入研究各种漏模开口板设计的各种相关因素以及现代SMT工业中不同工艺流程的相关性。本次研究的研究对象包括各种不同的材料和工艺流程，同时设计了各种不同的漏模板开口和开口形状。我们进行了一系列的试验研究各种影响因素(输入变量)与响应变量(输出变量)的关系。结论建立在10，000，000个试验数据的基础上。结果有利于澄清业界广泛存在的关于漏模板设计以及漏模板设计与工艺流程关系的各种误解。研究结果建立了漏模板开口设计的全新思维及与印刷质量关系的基本架构。     

论避免开断路漏测

本文依据多年现场测试经验积累，再结合专用／通用测试机原理等因素，分析总结出PCB测试出现漏测产生的原因，并作出相应的解决方案，以避免PCB板电测试开断路漏测。     

场板SOI RESURF LDMOS表面势场分布解析模型

以往对SOI器件的建模基本上基于漂移区全耗尽的假设,且大多未考虑场板对表面势场分布的影响。通过分区求解二维泊松方程,建立了场板SOI RESURF LDMOS表面电势和表面电场分布解析模型。该模型同时考虑了栅场板和漏场板的作用,既适用于漂移区全耗尽的情况,也适用于漂移区不全耗尽的情况。利用此模型和半导体器件仿真工具Silvaco,详细探讨了器件在不同偏压下栅场板和漏场板对漂移区表面电势和电场分布的影响。解析模型结果与数值仿真结果吻合良好,验证了模型的准确性。     

50V LDMOS漏电容非线性研究

借助软件模拟从器件结构和工艺参数角度研究了LDMOS漏电容Cd的非线性和源漏电压Vds的关系,研究了漂移区注入剂量、高压场板长度、场氧化层厚度、栅氧化层厚度、沟道区注入剂量等五个结构工艺参数对漏电容非线性的影响.主要分析了漂移区耗尽层对漏电容非线性的影响机理以及不同结构工艺参数如何通过改变漂移区耗尽层电容,进而影响漏电容非线性.提出了改善LDMOS的漏电容线性度的各参数调节方法.     

微型斯特林制冷器与杜瓦瓶组件耦合漏热分析

对杜瓦瓶漏热、微型斯特林制冷器冷指与杜瓦瓶组件耦合漏热进行了分析，得出斯特林制冷器与杜瓦瓶组件耦合时漏热量与微型节流制冷器和杜瓦瓶组件耦合时漏热量的区别，提出了斯特林制冷器与杜瓦瓶组件耦合时漏热量不但包括传统的三项漏热，而且应加上残余发子热传导引起的漏热量和穿棱漏热量。并给出了耦合时应该根据不同的制冷方式采取不同结构的建议。     

MOSFET栅下碰撞电离与击穿研究

研究了场板终端技术对改善 MOSFET栅下电场分布和碰撞电离率的作用 ,结果表明 ,MOSFET在高压应用时 ,漏极靠近表面的 PN结处电场最强 ,决定器件的击穿特性。通过对实验研究与计算机模拟结果的分析 ,表明在不同的栅压下 ,此处场板长度的大小对栅下电场强度有直接的影响 ,合理地控制场板长度能有效地提高器件的击穿电压。     

ATM网络中漏桶涌量控制特性的研究

本文对ＡＴＭ（异步转移模式）网络中话音、数据和图像业务的漏桶流量控制特性进行了研究。计算机模拟结果表明，由于各种业务内在的相关性不同，相应的漏桶流量控制特性有较大的差异，漏桶参数的选择对于各种业务具有不同的公平性，因而应根据业务的特性来设计漏桶参数。     

ATM网络中漏桶流量控制特性的研究

本文对ＡＴＭ（异步转移模式）网络中话音、数据和图像业务的漏桶流量控制特性进行了研究。计算机模拟结果表明，由于各种业务内在的相关性不同，相应的漏桶流量控制特性有较大的差异。漏桶参数的选择对于各种业务具有不同的公平性，因而应根据业务的特性来设计漏桶参数。     

焊膏印刷工艺的控制

在表面安装工艺中，焊膏印刷是一道关键的工序，膏印刷工艺的控制曩着组装板的质量。漏版、焊膏与印刷机是组成焊膏印刷工艺的三项基本内容，三方面相互联系，决定着整个工艺的品质，从焊膏的理化特性、漏版的设计制造以及焊膏印刷机工艺参数的优化设定等方面对焊膏印刷工艺的控制作了初步探讨。     

周期加载微带结构的模式分析

周期性的微带结构在相控阵天线、频率选择表面等领域都有着广泛应用。与单纯的接地介质板相比，它的电磁波模式更为复杂，解析式几乎不可得到。文中利用格林函数和矩量法相结合，对无限大的微带周期结构的表面波和漏波特性进行了数值分析，计算了方形环和方形贴片阵列两种情况。电流展开采用了分域基函数，计算得到了它的表面波和漏波模式的传播常数。     

Inkjet printed copper source/drain metallization for amorphoussilicon thin-film transistors

Source/drain metallization to amorphous silicon thin-film transistors has been made by inkjet printing. Contact pads of a metal organic copper precursor were inkjet printed, and then converted to copper metal at a maximum process temperature of 200°C. The copper contacts were used as the mask for back-channel etch. Laser printed toner was used for all other mask levels in a photoresist-free fabrication process. The inkjet printing of copper contacts represents a further step toward an all-printed thin-film transistor technology     

数字喷墨打印技术在PCB抗蚀层制作中的初步研究

随着数字喷墨打印设备和纳米油墨的不断发展,喷墨打印技术在PCB制作中得到了越来越广泛的应用。目前市场上主要包括三个方面的应用：抗蚀层、字符、阻焊。文章通过市场调研,成本评估和工艺能力评估重点研究了喷墨打印技术在线路抗蚀层制作中的应用。结果发现喷墨打印技术相对于传统的线路制作工艺具有一定的成本优势和线路制作能力。     

阻焊塞孔工艺改善

通过改良阻焊塞孔工具、规范网印塞孔操作、修改后固化参数,改善公司阻焊塞孔质量不稳定的问题。     

A simple mask aligner and printing frame for conformable photomask lithography

Conformable photomask lithography allows submicrometer lines to be replicated by contact printing. Surface acoustic wave devices with 0.4-µm lines have been produced using this technique. A mask aligner and printing frame have been designed which feature micrometer controlledXandYmotion, rotation about the center of the viewing field, and both top and bottom illumination of mask and substrate. The construction and use of the apparatus, which is based on a toolmaker's microscope, is fully described.     

SMPDP中荧光粉层制备方法的对比与研究

荫罩式等离子体显示器（SMPDP）是一种由金属荫罩板代替传统障壁的新型PDP。针对SMPDP结构的特殊性，讨论了丝网印刷法和喷涂法制备荧光粉层的制作工艺，并对比其优劣。实验结果表明：采用喷涂方法可以在SMPDP的荫罩孔内壁制备致密、均匀的荧光粉层，与掩膜配合使用，可在荫罩上制备三基色荧光粉，满足SMPDP实现彩色的需要。因此，喷涂方法是制备SMPDP三基色荧光粉层行之有效的最佳途径。     

HV‐SoP Technology for Maskless Fine‐Pitch Bumping Process

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip‐chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine‐pitch solder bumping has been widely studied. In this study, high‐volume solder‐on‐pad (HV‐SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are 28.3 μm, 31.7 μm, and 26.3 μm, respectively. It is expected that the HV‐SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine‐pitch flip‐chip bonding.     

Improving resolution in photolithography with a phase-shifting mask

The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10X tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.     

Models for characterizing phase-shift defects in optical projectionprinting

An algebraic model is developed for characterizing the printability, inspection, and repair of phase-shift defects in optical projection printing. Phase-shift defects are particularly difficult to characterize because of the many parameters associated with the exposure tool and with the attenuating phase shift mask (PSM) pattern. Furthermore, the parameters change during inspection of the attenuating PSM because the mask is examined under illumination conditions which differ from the exposure illumination. An algebraic model which encompasses this large set of variables is derived by considering the electric fields under the mask to be a combination of the electric fields from the feature and defect. These fields are then combined according to the mutual coherence function for the mask illumination. A notable difficulty is the relative phase shift due to defocus between large and small features. The model is shown to be valid for defects up to 0.35 λ/NA by comparison to SPLAT. Experimental verification is made for defects impacting a 6% transmitting PSM for 0.35-μm features at i-line. The reliability of the model is illustrated by giving rules of thumb for defect printing in attenuating PSM's     

8-wavelength DBR laser array fabricated with a single-step Bragggrating printing technique

An 8-wavelength distributed Bragg reflector (DBR) array for narrow channel wavelength division multiplexing (WDM) has been fabricated with a new technique for printing first-order Bragg gratings using a phase mask and a conventional incoherent source. All the distributed gratings were printed in a single photolithographic step with a slightly modified mask aligner. The DBR's excellent wavelength control for channels separated by as little as 0.8 nm is described. Many advanced photonic devices relying on gratings like quarter-wave shifted distributed feedback (DFB) lasers and wavelength division multiplexing (WDM) components can potentially be manufactured with this technique in a simple and cost-effective way     

A review of mask errors on a variety of pattern generators

The question of how mask dimensional errors impact yield is becoming increasingly critical to VLSI manufacturing. Both the magnitude and the spatial correlation of CD and registration errors are believed important to this issue. As part of a program to characterize these errors, we have had one identical test mask made on 6 different state-of-the-art mask pattern generators with widely different architectures. The test mask provides information on both registration and feature-size errors in both x- and y-directions, and does so over distances of several centimeters with spacing between measurements as small as 1 μm. More than 100000 data points have been collected from these test plates using a LMS2000 optical metrology system, and are analyzed in the spatial frequency domain where error contributors as small as 1 nm can be identified. All systems were found to have similar characteristics in that most error contributors occur at a number of machine-specific spatial frequencies correlated to the particular architecture and printing strategy of the machine. Comparison of raster to vector machines show that vector machines tend to have more periodic error contributors, especially in the high spatial frequency range, which is consistent with the more complex writing fields used to achieve higher throughput