电极可重复使用的PCR芯片及其温度场分析

基于MEMS加工技术,提出了一种加热、传感电极和反应腔室可分离的PCR芯片结构,加热、传感电极采用Pt薄膜材料并可重复使用,反应腔室采用PDMS材料,芯片的制造成本大为降低.利用COMSOL软件对设计的PCR芯片进行了温度场仿真分析,并用红外热像测温仪(NEC R300)对微制造的芯片温度场分布进行了测量.测量结果表明芯片结构能得到较好的温度均匀性,为后续PCR芯片扩增实验提供了可靠的依据.     

基于核酸检测的微流控芯片设计与传热分析

为了解决传统数字聚合酶链式反应(PCR)扩增过程中移液操作产生的问题以及升降温速率慢的弊端,设计了一种连续流数字PCR微流控芯片,能对包含PCR反应体系的微滴进行快速扩增,可以提升核酸检测过程中的扩增效率.用COMSOL对芯片微通道内部的温度分布和两相流体的共轭传热进行了数值模拟.结果 表明,芯片内部能产生95、55和...     

非均匀芯片布局的LED模组散热性能研究

芯片阵列均匀排列的常规大功率LED模组因温度场叠加会导致中心温度过高、温度分布不均匀。在理论分析面热源温度分布函数及多热源相互影响的基础上提出了一种LED芯片外密内疏排列的模组设计方案,并与ANSYS有限元仿真的结果进行了对比验证。当芯片按照优化后的对数和幂函数分布时芯片最高温度比常规均匀排列时均低约5℃,芯片温度的方差降低约56%。外密内疏的非均匀芯片排列方案在基板较小、较薄时对散热效果的改善更好。     

微型PCR系统及其温控特性研究

介绍了一种基于芯片的微型聚合酶链式反应(polymerase chain reaction,PCR)系统,利用该系统进行了温度控制和响应特性研究.系统由PCR芯片、封装PCB板及单片机控制系统组成.PCR芯片采用MEMS技术制作.用微型PCR系统对芯片上含有微加热器的反应仓进行了升温降温、循环温度和液体负载对比加热等实验.结果显示:微加热器升温速度可以达到3 ℃/s,降温速度可以达到1℃/s,稳定后温度变化小于0.1 ℃.通过实验结果与理论计算的对比,分析了微加热器的最高温度与加热功率之间的对应关系及提高温控特性的关键因素.     

表面组装无引线陶瓷芯片载体的热分析

应用有限元热分析技术，对表面组装无引线陶瓷芯片载体组装到印制电路板的结构进行了热３分析，得到了芯片不同粘合方式与不同冷却条件下该结构的温度场分布，从中提取出无引线陶瓷芯片载体的热阻网络及热阻值，并将计算结果与国外实验结果相对比，符合良好，本文所构造的热模型可用于产体集成电路芯片封装结构的优化设计，也为电子组装热设计提供了详细的数据。     

基于COSMOSWORKS有限元分析的HDI板热应力仿真

电子产品的高电气性能发展趋势要求了PCB制造的高密度化与芯片设计的大规模集成化。当大功率芯片无法快速散热时,PCB基体将发生温度分布不均匀现象,并且温度分布不均匀产生的热应力又会影响PCB的可靠性。本文以热分布不均匀的HDI刚挠结合板为研究对象,通过有限元数值模拟方法建立了HDI板结构模型,采用热生成加载的方式给HDI板施加热量,模拟计算出在均匀温度场中HDI板因材料热膨胀系数差异产生的层间热应力。仿真结果表明了界面热应力的大小、分布和HDI板材料的热膨胀系数、温度载荷密切相关,并且能快速观察到引起HDI板失效的层间热应力趋势,为优化HDI板结构设计、提高HDI板可靠性提供了理论依据。     

微通道式PCR芯片温度的研究

微通道式PCR芯片是对DNA扩增的新方法，通过样品试剂在三个温区间的流动，实现对试剂中特定DNA片段的几何级数扩增。研究了一种新型微通道式PCR芯片，利用有限元技术，对芯片上热区的温度梯度和均匀性进行了计算，对影响PCR反应的三种温度因素作出了定量分析。另外，针对传感器和加热器的外形、放置以及加热区的不均匀化，采取了系列优化措施，计算了薄膜电阻功率和电阻参数，改善了芯片的热特性，提高了其倍增的效率。     

128×128元锑化铟红外焦平面探测器热-应力耦合分析

考虑探测器在热冲击过程中由于传导降温非均匀引起的温度梯度分布,借助ANSYS软件对温度梯度影响下的锑化铟探测器进行热-应力耦合分析。依据热分析结果得到了热冲击下探测器的降温时间曲线,以此为基础进行热-应力耦合分析得到了探测器的应力分布,并以温度、时间为参考量将热冲击过程中InSb芯片上应力最大值变化与传统均匀降温方式下的应力最大值变化进行对比,结果表明器件内部存在温度梯度时,InSb芯片上的应力增加呈现出先快后慢现象,明显不同于均匀降温的线性增加;且应力增加主要集中在热冲击初始0～0.5 s时间段,如此短时间段内应力的急剧增加将严重影响探测器的可靠性。最后对传导降温方式下应力变化可能引起InSb芯片失效的原因进行了初步探讨,这对预测裂纹的发生提供了一定的帮助。     

基于遗传算法的MCM热布局优化研究

在多芯片组件（Multi-Chip Module，MCM）的热设计中，MCM内裸芯片组装密度大，且裸芯片是主要发热源，各裸芯片之间的位置布局直接影响MCM内温度场分布，进而影响MCM的可靠性。本文基于热叠加模型，选取裸芯片的平均温度作为评价指标，确定出用于MCM热布局优化的适应度函数，基于遗传算法提出一种MCM热布局优化算法，并编制相应优化程序，实现对裸芯片的热布局优化，得出热布局规则用于指导MCM的实际热设计；采用有限元分析软件ANSYS，对MCM布局优化结果进行温度场-应力场偶合分析，以仿真的方法验证MCM热布局优化算法的有效性。     

电加热板温度控制的仿真分析

光刻胶的前烘与坚膜是微机械加工工艺中不可缺少的两道工序，用于光刻胶烘干的热板对表面温度场分布的均匀性和温度控制稳定性均有较严格的要求，本文描述了利用有限元软件对加热板的稳态温度场，瞬态响应进行了分析，获得其最佳温度场分布，从而建立数学模型；然后利用MATLAB软件对PID控制仿真，以分析电加热板对温度的稳定性与均匀性的影响。     

Heat dissipation assessment of through silicon via (TSV)-based 3D IC packaging for CMOS image sensing

The study aims at evaluation of the steady-state heat dissipation capability of a high-density through silicon via (TSV)-based three-dimensional (3D) IC packaging technology (briefly termed 3D TSV IC packaging) designed for CMOS image sensing under natural convection through finite element analysis (FEA) and thermal experiments. To enhance modeling and computational efficiency, an effective approach based on FEA incorporating a 3D unit-cell model is proposed for macroscopically and thermally simulating the heterogeneous TSV chips. The developed effective thermal conductivities are compared against those obtained from a rule-of-mixture technique. In addition, the proposed numerical models are validated by comparison with two experiments. Besides, the uncertainties in the input chip power from the specific power supply and in the measured chip junction temperature by the thermal test die are evaluated. Finally, a design guideline for improved thermal performance is provided through parametric thermal study.     

Cool Chips: Opportunities and Implications for Power and Thermal Management

Alongside innovative device, circuit, and microarchitecture level techniques to alleviate power and thermal problems in nanoscale CMOS-based integrated circuits (ICs), chip cooling could be an effective knob for power and thermal management. This paper analyzes IC cooling while focusing on the practical temperature range of operation. Comprehensive analyses of chip cooling for various nanometer scale bulk-CMOS and silicon-on-insulator (SOI) technologies are presented. Unlike all previous works, this analysis employs a holistic approach (combines device, circuit and system level considerations) and also takes various electrothermal couplings between power dissipation, operating frequency and die temperature into account. While chip cooling always gives performance gain at the device and circuit level, it is shown that system level power defines a temperature limit beyond which cooling gives diminishing returns and an associated cost that may be prohibitive. A scaling analysis of this temperature limit is also presented. Furthermore, it is shown that on-chip thermal gradients cannot be mitigated by global chip cooling and that localized cooling can be more effective in removing hot-spots.     

Peak temperature reduction by optimizing power density distribution in 3D ICs with microchannel cooling

Liquid cooling with microchannels is a very attractive idea for 3D ICs which could help solving the problem of ever-increasing power dissipation due to its good cooling efficiency and potential scalability. However, this cooling method has some very different properties compared to the well-understood forced air convection. In particular, its cooling efficiency with respect to power variations in the chip is still not completely analyzed. Therefore, in this paper a thorough study of microchannel cooling efficiency as a function of intra- and interlayer power consumption variability is presented. We use a finite element method analysis to run a coupled thermo-fluidic simulation of a dedicated 3D chip model. An analytical analysis is also provided which calculates analytically the optimal power density profile along the channel. Then, steps necessary for finding the optimal power distribution for chip units are proposed. It is also shown that by appropriately managing the power density according to the proposed methodology, it is possible to significantly reduce the peak chip temperature. In particular, for a 3D chip including Intel's i7-6950X 10-core processor, a temperature reduction of 8.9 °C was achieved by a proper orientation of microchannels and another 5.8 °C reduction was obtained by optimally distributing power consumption between processor cores.     

嵌入式系统的制冷CCD相机

根据天文摄影中CCD的工作特性,提出了基于嵌入式技术制冷CCD相机的新方法,以ARM微处理器为硬件平台设计了嵌入式制冷CCD相机,并在低照度下的天文观测中取得了良好的效果.基于天文制冷CCD的具体特性和对信号数据输出的要求,选用CXD1267和AD9826分别设计CCD的列转移驱动时序和CCD的水平读出时序.通过微处理器定时中断,实现对CCD制冷温度的实时控制.分析了科学级CCD噪声的种类及来源,通过实验得到了温度、曝光时间与暗电流噪声的关系以及CCD的读出速率与读出噪声的关系.进而在硬件和软件上采取了相应的措施有效地降低了CCD的噪声.     

芯片冷却中热电制冷器性能的实验研究

设计了电子芯片冷却实验装置,对热电制冷器在电子芯片冷却中的冷却效果和制冷性能进行了研究。实验结果表明,不仅热电制冷片热端冷却水流量是影响冷却效果的重要因素,而且热电电流和芯片功率与热电冷却性能也有着密切的关系。实验结果对热电冷却器的最佳冷却性能的确定具有一定的参考意义。     

Design and Simulation of High-power LED Array Packaging

Thermal management is one of the key technologies for high-power Light emitting diode（LED） entering into the general illuminating field. Successful thermal management depends on optimal packaging structure and selected packaging materials. In this paper, the aluminum is employed as a substrate of LED, 3×3 array chips are placed on the substrate, heat dissipation performance is simulated using finite element analysis（FEA） software, analyzed are the influences on the temperature of the chip with different convection coefficient, and optical properties are simulated using optical analysis software. The results show that the packaging structure can not only effectually improve the thermal performance of high-power LED array but also increase the light extraction efficiency.     

Power Trace: An Efficient Method for Extracting the Power Dissipation Profile in an IC Chip From Its Temperature Map

In this paper, we present a new technique to calculate the power dissipation profile from the IC temperature map using a process analogous to image processing and restoration. In this technique, finite-element analysis (FEA) is used to find the heat-point spread function (heat PSF) of the IC chip. Then, the temperature map is used as input for an efficient image restoration algorithm which locates the sources of strong power dissipation non-uniformities. Therefore, it optimally solves the inverse heat transfer problem, and estimates the IC power map without extensive lab experiments. Our computationally efficient and robust method, unlike some previous techniques, applies to many experimental scenarios. Simulation results on a typical commercial integrated circuit chip confirm the effectiveness of our proposed method.