一种用于表征亚阈值电流镜电路中CMOS工艺波动的统计学方法

提出了一种新的表征亚阈值电路镜电路中CMOS工艺波动的方法.与现有的统计学方法相比,该方法在理论上和计算复杂度上相对简洁,但对亚阈值电流镜电路中的CMOS工艺波动做出了准确的评估.此模型利用统计学的概念将依赖于IC工艺的物理参数抽象为具有确定均值和方差的随机变量,并进一步将所有随机因素累加为离散鞅.在SMIC 0.18μm CMOS 1P6M混合信号工艺下,利用工作在100pA～1μA范围内、增益为100的亚阈值电流镜电路对此方法的正确性进行了实验验证.该理论成功地预测了～10%的实测芯片间工艺波动,并且给出了～1mV的片上阈值电压标准偏差,此结果与SMIC提供的没计参数吻合.该理论给出的概率分布与实测结果的偏差小于8%.同时,还针对高工艺稳定性的亚阈值模拟电路设计方法进行了相关的讨论.     

一种工作于亚阈值区的低功耗CMOS晶体振荡器

提出了一种基于亚阈值区的低功耗CMOS晶体振荡器电路.通过环路增益和相位的分析,得出了一般晶体振荡电路的振荡性能优化条件;并通过亚阈值电流源、亚阈值MOS管反馈、电流源放大缓冲级以及电路的其他改进,进一步优化振荡电路的性能.根据这种设计,采用SMIC 0.18 μm CMOS单层多晶硅六层金属工艺,实现了一个功耗电流0.7 μA的CMOS晶体振荡器.     

一种基于亚阈值MOSFET的140mV 0.8μA电压基准

——本文提出了一种基于亚阈值MOSFET的CMOS电压基准电路,它采用了与温度相关的阈值电压、峰值电流镜和亚阈值技术。此基准结构只由MOS晶体管和电阻组成,已经在SMIC 0.13μm CMOS工艺线上通过了流片验证。实验结果表明,基准电压输出在电源电压从0.5V变化到1.2V时具有2mV的变化,温度从-20℃变化到120℃时具有0.8mV的变化。该电路在室温时输出140mV,并且消耗电源电流仅为0.8uA,芯片面积占有0.019mm²。     

超低功耗亚阈值CMOS电压基准电路

采用SMIC 0.18μm CMOS工艺,设计了一种基于亚阈值MOS管的超低功耗、低温度系数的全CMOS电压基准电路。电路可在0.6~5V的工作电压范围内工作,当工作电压为1V时,功耗为1.12nW。在-20℃~80℃温度范围内,电路的最低温度系数为2.7×10-6/℃。在无片外滤波电容的情况下,电路的电源抑制比在100Hz和10MHz时分别为-56dB和-45dB。     

1V电源的CMOS能隙电压基准源

采用SMIC 0.35μm CMOS工艺实现了一种可以工作在1V电源电压下的CMOS能隙基准源.测试表明,该电路可以工作在1～2.5V电源电压下,输出的基准电压可以稳定在约0.446V.在从室温到100℃的范围内,温度系数不超过3.6×10-5/K.     

65nm标准CMOS工艺阈值电压系统波动检测方案设计

设计了一种标准CMOS工艺下的阈值电压系统波动检测电路,其检测电路核心部分是工作在亚阈值区的环形振荡器(SRO)。该方案包括8种级数、2种尺寸共16种SRO,并以8种级数、2种尺寸共16种传统环形振荡器(RO)作对比,在SMIC 65nm标准CMOS工艺上流片验证。芯片测试结果表明:新方案相对传统检测方案具有更高的灵敏度,更直观;且阈值电压的系统波动随器件尺寸增大而略微减小。     

基于控阈技术的电流型CMOS全加器的通用设计方法

利用电流信号的阈值易于控制这一特点,对电流型CMOS电路中如何实现阈值控制进行了研究.以开关信号理论为指导,建立了实现阈值控制电路的电流传输开关运算并具体指导设计了具有阈值控制功能的二值和多值电流型CMOS全加器.提出了适用于任意逻辑值的可控阈电流型CMOS全加器的通用设计方法.通过对开关单元实施阈值控制后,所设计的电路在结构上得到了非常明显的简化,在性能上也获得了改善.最后给出了采用0.25μm CMOS工艺参数的HSPICE模拟结果及其能耗比较.     

基于CMOS亚阈值特性的低功耗温度传感器

针对片上系统测温及其过温保护问题,提出了一种基于CMOS亚阈值特性制造的低功耗温度传感器.CSMC 0.6μm数模混合工艺仿真表明,其在-50～150℃的温度范围内,都能良好工作,且因为运放负反馈结构对电源电压具有较高的抑制,在2～6V的范围内都能得到正确的输出结果.芯片实测,温度灵敏度为0.77V/℃.因为基于CMOS亚阈值特性产生了电路的偏置电流,所以工作电流仅16μA.芯片面积300μm×250μm.该传感器的特性表明它非常适用于高容量的集成微系统中,在计算机、汽车电子、生物医学等领域有着广阔的应用前景.     

基于CMOS亚阈值特性的低功耗温度传感器

针对片上系统测温及其过温保护问题,提出了一种基于CMOS亚阈值特性制造的低功耗温度传感器.CSMC 0.6μm数模混合工艺仿真表明,其在-50～150℃的温度范围内,都能良好工作,且因为运放负反馈结构对电源电压具有较高的抑制,在2～6V的范围内都能得到正确的输出结果.芯片实测,温度灵敏度为0.77V/℃.因为基于CMOS亚阈值特性产生了电路的偏置电流,所以工作电流仅16μA.芯片面积300μm×250μm.该传感器的特性表明它非常适用于高容量的集成微系统中,在计算机、汽车电子、生物医学等领域有着广阔的应用前景.     

1V电源的CMOS能隙电压基准源

采用SMIC 0.35μｍ CMOS工艺实现了一种可以工作在1V电源电压下的CMOS能隙基准源．测试表明,该电路可以工作在1～2.5V电源电压下,输出的基准电压可以稳定在约0.446V．在从室温到100℃的范围内,温度系数不超过3.6e－５/K．     

A 0.5-V MTCMOS/SIMOX logic gate

This paper proposes a multithreshold CMOS (MTCMOS) circuit that uses SIMOX process technology. This MTCMOS/SIMOX circuit combines fully depleted low-threshold CMOS logic gates and partially depleted high-threshold power-switch transistors. The low-threshold CMOS gates have a large noise margin for fluctuations in operating temperature in addition to high-speed operation at the low supply voltage of 0.5 V. The high-threshold power-switch transistor in which the body is connected to the gate through the reverse-diode makes it possible to obtain large channel conductance in the active mode without any increase of the leakage current in the sleep mode. The effectiveness of the MTCMOS/SIMOX circuit is confirmed by an evaluation of a gate-chain test element group (TEG) and an experimental 0.5-V, 40-MHz, 16-b ALU, which were designed and fabricated with 0.25-μm MTCMOS/SIMOX technology     

Modeling statistical dopant fluctuations in MOS transistors

The impact of statistical dopant fluctuations on the threshold voltage V_T and device performance of silicon MOSFET's is investigated by means of analytical and numerical modeling. A new analytical model describing dopant fluctuations in the active device area enables the derivation of the standard deviation, σV_T , of the threshold voltage distribution for arbitrary channel doping profiles. Using the MINIMOS device simulator to extend the analytical approach, it is found that σV_T, can be properly derived from two-dimensional (2-D) or three-dimensional (3-D) simulations using a relatively coarse simulation grid. Evaluating the threshold voltage shift arising from dopant fluctuations, on the other hand, calls for full 3-D simulations with a numerical grid that is sufficiently refined to represent the discrete nature of the dopant distribution. The average V_T-shift is found to be positive for long, narrow devices, and negative for short, wide devices. The fast 2-D MINIMOS modeling of dopant fluctuations enables an extensive statistical analysis of the intrinsic spreading in a large set of compact model parameters for state-of-the-art CMOS technology. It is predicted that V_T-variations due to dopant fluctuations become unacceptably large in CMOS generations of 0.18 μm and beyond when the present scaling scenarios are pursued. Parameter variations can be drastically reduced by using alternative device designs with ground-plane channel profiles     

Leakage current,active power,and delay analysis of dynamic dual Vt CMOS circuits under P–V–T fluctuations

The leakage current, active power and delay characterizations of the dynamic dual V_t CMOS circuits in the presence of process, voltage, and temperature (P–V–T) fluctuations are analyzed based on multiple-parameter Monte Carlo method. It is demonstrated that failing to account for P–V–T fluctuations can result in significant reliability problems and inaccuracy in transistor-level performance estimation. It also indicates that under significant P–V–T fluctuations, dual V_t technique (DVT) is still highly effective to reduce the leakage current and active power for dynamic CMOS circuits, but it induces speed penalty. At last, the robustness of different dynamic CMOS circuits with DVT against the P–V–T fluctuations is discussed in detail.     

Cross-section analysis of electric devices by scanning capacitance microscope

Carrier influence of semiconductor devices is important as it affects the function of the device. In this experiment, the carrier density distribution in the cross-section of semiconductor device was analyzed by SCM: Scanning Capacitance Microscope which is one of the measuring mode of SPM: Scanning Probe Microscope.This paper describe measurement result of change in carrier density by the gate voltage at p channel area of CMOS device and its efficiency to investigating dopant profile on 16MDRAM cross-section.     

Electrical noise and RTS fluctuations in advanced CMOS devices

A brief overview of recent issues concerning the low frequency (LF) noise in modern CMOS devices is given. The approaches such as the carrier number and the Hooge mobility fluctuations used for the analysis of the noise sources are presented and illustrated through experimental results obtained on advanced CMOS generations. The use of the LF noise measurements as a characterization tool of large area MOS devices is also discussed. The main physical features of random telegraph signals (RTSs) observed in small area MOS transistors are reviewed. The impact of scaling on the LF noise and RTS fluctuations in CMOS silicon devices is also addressed. Experimental results obtained on 0.18 μm CMOS technologies are used to predicting the trends for the noise figure of foregoing CMOS technologies e.g. 0.1 μm and beyond. The formulation of the thermal noise underlying the LF fluctuations in MOSFETs is recalled for completeness.     

Analog inner product operations for image compression in 0.35-μm CMOS

We propose a new model for analyzing the sensitivity of inner products to CMOS analog hardware implementation. It is derived from Spice simulations of the circuits to be implemented, and it is required for the design of analog image compression systems based on vector quantization at the focal plane of CMOS imaging sensors. The model is shown to be equivalent to a simpler and previously introduced theoretical model, if the errors caused by the fabrication process are around 6%. For 1.5% errors, the results differ from the theoretical predictions made by the previous model. Image compression results obtained with a prototype circuit fabricated in a 0.35-μm CMOS process are presented, and show close agreement with both theoretical and simulation predictions.     

Circuit Design of a High Speed and Low Power CMOS Continuous-time Current Comparator

Current comparator is a fundamental component of current-mode analog integrated circuits. A novel high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier's negative feedback. Because the voltage swings of the CMOS complementary amplifier are reduced by low input and output resistances, the delay time of the current comparator is shortened. Its power consumption can be reduced rapidly with the increase of input current. Simulation results based on 1.2 m CMOS process model show the speed of the novel current comparator is comparable with those of the existing fastest CMOS current comparators, and its power consumption is the lowest, so it has the smallest power-delay product. Furthermore, the new current comparator occupies small area and is process-robust, so it is very suitable to high-speed and low-power applications.     

基于CMOS技术的I2C总线接口实现方法

研究了I2C总线协议内容,设计了基于CMOS技术的I2C总线接口的系统结构及实现方法。目前对于I2C总线的设计一般基于FPGA和单片机编程,文中采用CMOS技术设计和实现,具有结构简单、使用灵活、成本低、速度快的特点,在实际应用中可以满足3 MHz/s以下的传输速率,具有一定实用价值。     

Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs

A synthesized compact modeling (SCM) approach for substrate coupling analysis is presented. The SCM is formulated using a scalable$Z$matrix approach for heavily doped substrates with a lightly doped epitaxial layer and using a nodal lumped resistance approach for lightly doped substrates. The SCM models require a set of process-dependent fitting coefficients and incorporate geometrical parameters of the substrate ports in a compact form that includes size, perimeter, and separation defined using the geometric mean distance to accommodate both far-field and near-field effects. The SCM approach is verified based on measurement data from two test chips, one in a custom lightly doped process and the other one using a 0.18-$muhbox m$BiCMOS lightly doped foundry process. The model accuracy is shown to be within 15% compared to measured data extracted from the test patterns. The SCM is exploited with application examples to show substrate model generation efficiency and accuracy at different levels of complexity, including a full chip substrate noise distribution analysis for a 2 mm by 2 mm chip with 319 substrate contacts.