An Analytical Model for Predicting the Underfill Flow Characteristics in Flip-Chip Encapsulation

This article describes an analytical model for the prediction of the underfill flow characteristics in a flip-chip package driven by capillary action. In this model, we consider non-Newtonian fluid properties of the encapsulant as opposed to most other studies where Newtonian fluid properties were assumed for the underfill flow. The power-law constitutive equation was applied in our study. The simulation based on this model agreed well with the measurement obtained from the experiments available in literature. It was further shown that this model performs better than the Washburn model traditionally used for the prediction of underfill flow characteristics in the flip-chip packaging. Based on this model, the effects of the solder bump pattern (including bump pitch, solder bump diameter, and gap height) on the process variables (i.e., flow front and filling time) were studied, which facilitated both the package design and the process optimization.     

Recent advances in modeling the underfill process in flip-chip packaging

Flip-chip underfill process is a very important step in the flip-chip packaging technology because of its great impact on the reliability of the electronic devices. In this technology, underfill is used to redistribute the thermo-mechanical stress generated from the mismatch of the coefficient of thermal expansion between silicon die and organic substrate for increasing the reliability of flip-chip packaging. In this article, the models which have been used to describe the properties of underfill flow driven by capillary action are discussed. The models included apply to Newtonian and non-Newtonian behavior with and without the solder bump resistance for the purpose of understanding the behavior of underfill flow in flip-chip packaging.     

Numerical Modeling for the Underfill Flow in Flip-Chip Packaging

In the prediction of underfill flow in a flip-chip package, numerical methods are usually used for flow analysis and simulation since analytical methods cannot meet the requirement for predicting fluid distribution in a planar analysis. At present, there appears to be no simulation software commercially available that is able to provide adequate prediction for the underfill flow process driven by capillary force in a micro-cavity situation. In the study presented in this paper, a numerical model was proposed for the prediction of flip-chip underfill flow. In this model, the power-law constitutive equation was used to describe the non-Newtonian behavior of encapsulant fluids and a time-dependent velocity boundary condition was used instead of the pressure boundary condition commonly used. The comparison between the model-predicted and experimental results indicated that this model can give a good prediction for the underfill flow in a micro-cavity. This model was implemented by a general-purpose commercially available software program ANSYS, which has a high reliability and wide accessibility.      

基于表面能理论的倒装芯片封装下填充流动研究

为了预测倒装芯片封装中的下填充过程,通常要首先通过繁复的方法来求解平均毛细压.为了避免此问题,从能量的角度分析了倒装芯片封装工艺中的下填充流动过程.认为下填充是较低表面能的界面代替较高表面能的界面的过程,所释放的表面能用于形成流体流动的动能和克服阻力的能量损耗,期间能量守恒.在此分析的基础上建立了下填充流动的新模型.建立了可视化的下填充流动实验装置,并用下填充实验验证了所建立新模型的准确性.该模型避免了计算平均毛细压的复杂过程,并可方便地扩展到焊球排布形式不同的倒装芯片.     

Flow time measurements for underfills in flip-chip packaging

Flow time is a key material property for underfill materials in flip-chip applications. In this paper, we will discuss how to use flow time testing for underfill flow evaluation and material screening. The flow time of several underfills was measured at elevated temperatures using test pieces made from glass microscope slides. The material properties impacting underfill flow, such as viscosity, contact angle, and surface tension, were also experimentally measured and used to calculate estimated flow times using the Washburn equation. Empirical and calculated flow times were compared. The effects of channel width and flow distance on flow time were also studied. Additionally, the effect of a tilted stage on flow time, epoxy tongue, and void formation was evaluated.     

Enhancement of underfill capillary flow in flip-chip packaging by means of the inertia effect

This paper describes how the use of inertia forces induced by the rotation of a working disk may be adopted to increase the fill rate of the flip-chip packaging process and thereby reduce the process cycle time. It is shown how the driving forces resulting from the inertia effect are determined by the Weber number. The constant and varying contact angle models are compared under a specified set of process conditions. The calculated flow behavior results indicate that the relationship between the contact angle, the average fluid velocity, the liquid-air interface position, and the filling time depends upon the Weber number. The constant and varying contact angle models are utilized in the analysis of a new processing method referred to as rotation-enhanced underfill packaging (REUP). The inertia effect induced by the angular motion of the working disk is shown to enhance the flow of the underfill encapsulant and to reduce the time of the underfill process. The present results confirm that the rotation of the working disk leads to an increased underfill capillary flow rate, which is beneficial in reducing the production cycle time of the flip-chip packaging process.     

Recent advances in flip-chip underfill: materials, process, and reliability

In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.     

倒装芯片下填充流动二维化数值分析方法的应用

下填充流动是确保倒装芯片可靠性的重要封装工艺,其流场和流动过程具有明显的二维特征,通过降维得到的二维化数值分析新方法能高效地模拟下填充流动过程.针对一种焊球非均匀、非满布的典型倒装芯片,用该数值分析方法模拟了单边下填充流动的过程,并用实验对模拟结果进行了检验.实验采用了可视化的下填充流动装置,倒装芯片试样采用硅-玻璃键合(SOG)方法制作.将数值模拟结果与实验结果比较发现,无论是流动速度还是流动前沿的形态,两者均呈现出较高的吻合度.这表明:针对下填充流动的二维化数值分析方法兼具高效性和准确性,具有较高的应用价值.     

Reliability issues for flip-chip packages

In this article, we review the reliability issues for plastic flip-chip packages, which have become an enabling technology for future packaging development. The evolution of area-array interconnects with high I/O counts and power dissipation has made thermal deformation an important reliability concern for flip-chip packages. Significant advances have been made in understanding the thermo-mechanical behavior of flip-chip packages based on recent studies using moiré interferometry. Results from moiré studies are reviewed by focusing on the role of the underfill to show how it reduces the shear strains of the solder balls but shifts the reliability concern to delamination of the underfill interfaces. The development of the high-resolution moiré interferometry based on the phase-shift technique provided a powerful method for quantitative analysis of thermal deformation and strain distribution for high-density flip-chip packages. This method has been applied to study plastic flip-chip packages and the results and impacts on delamination at the die/underfill interface and in the underfill region above the plated through-hole via are discussed. Here a related reliability problem of die cracking during packaging assembly and test is also discussed. Finally, we discuss briefly two emerging reliability issues for advanced flip-chip packages, one on the packaging effect on Cu/low k interconnect reliability and the other on electromigration of solder balls in flip-chip packages.     

Influence of transient flow and solder bump resistance on underfill process

The underfill flow process is one of the important steps in Microsystems technology. One of the best known examples of such a process is with the flip-chip packaging technology which has great impact on the reliability of electronic devices. For optimization of the design and process parameters or real-time feedback control, it is necessary to have a dynamic model of the process that is computationally efficient yet reasonably accurate. The development of such a model involves identifying any factors that can be neglected with negligible loss of accuracy. In this paper, we present a study of flow transient behavior and flow resistance due to the presence of an array of solder bumps in the gap. We conclude (1) that the assumption of steady flow in the modeling of the flow behavior of fluids in the flip-chip packaging technology is reasonable, and (2) the solder bump resistance to the flow can not be neglected when the clearance between any two solder bumps is less than 60-70 μm. We subsequently present a new model, which extends the one proposed by Han and Wang in 1997 by considering the solder bump resistance to the flow.     

FEM modeling of temperature distribution of a flip-chip no-flow underfill package during solder reflow process

Flip chip on organic substrate has relied on underfill to redistribute the thermomechanical stress and to enhance the solder joint reliability. However, the conventional flip-chip underfill process involves multiple process steps and has become the bottleneck of the flip-chip process. The no-flow underfill is invented to simplify the flip-chip underfill process and to reduce the packaging cost. The no-flow underfill process requires the underfill to possess high curing latency to avoid gelation before solder reflow so to ensure the solder interconnect. Therefore, the temperature distribution of a no-flow flip-chip package during the solder reflow process is important for high assembly yield. This paper uses the finite-element method (FEM) to model the temperature distribution of a flip-chip no-flow underfill package during the solder reflow process. The kinetics of underfill curing is established using an autocatalytic reaction model obtained by DSC studies. Two approaches are developed in order to incorporate the curing kinetics of the underfill into the FEM model using iteration and a loop program. The temperature distribution across the package and across the underfill layer is studied. The effect of the presence of the underfill fillet and the influence of the chip dimension on the temperature difference in the underfill layer is discussed. The influence of the underfill curing kinetics on the modeling results is also evaluated.     

Modeling of the curing kinetics of no-flow underfill in flip-chip applications

No-flow underfill has greatly improved the production efficiency of flip-chip process. Due to its unique characteristics, including reaction latency, curing under solder reflow conditions and the desire for no post-cure, there is a need for a fundamental understanding of the curing process of no-flow underfill. Starting with a promising no-flow underfill formulation, this paper seeks to develop a systematic methodology to study and model the curing behavior of this underfill. A differential scanning calorimeter (DSC) is used to characterize the heat flow during curing under isothermal and temperature ramp conditions. A modified autocatalytic model is developed with temperature-dependent parameters. The degree of cure (DOC) is calculated; compared with DSC experiments, the model gives a good prediction of DOC under different curing conditions. The temperature of the printed wiring board (PWB) during solder reflow is measured using thermocouples and the evolution of DOC of the no-flow underfill during the reflow process is calculated. A stress rheometer is used to study the gelation of the underfill at different heating rates. Results show that at high curing temperature, the underfill gels at a lower DOC. Based on the kinetic model and the gelation study, the solder wetting behavior during the eutectic SnPb and lead-free SnAgCu reflow processes is predicted and confirmed by the solder wetting tests.     

Effects of underfill materials on the reliability of low-K flip-chip packaging

The reliability of low-K flip-chip packaging has become a critical issue owing to the low strength and poor adhesion qualities of the low-K dielectric material when compared with that of SiO₂ or fluorinated silicate glass (FSG). The underfill must protect the solder bumps and the low-K chip from cracking and delamination. However, the material properties of underfill are contrary to those required for preventing solder bumps and low-K chip from cracking and delamination. This study describes the systematic methodologies for how to specify the adequate underfill materials for low-K flip-chip packaging. The structure of the test vehicle is seven copper layers with a low-K dielectric constant value of 2.7-2.9, produced by the chemical vapor deposition (CVD) process. Initially, the adhesion and the flow test of the underfill were evaluated, and then the low-K chip and the bumps stress were determined using the finite element method. The preliminary screened underfill candidates were acquired by means of the underfill adhesion and flow test, and balancing the low-K chip and the bumps stress simulation results. Next, the low-K chips were assembled with these preliminary screened underfills. All the flip-chip packaging specimens underwent the reliability test in order to evaluate the material properties of the underfill affecting the flip-chip packaging stress. In addition, the failed samples are subjected to failure analysis to verify the failure mechanism. The results of this study indicate that, of the underfill materials investigated, those with a glass transition temperature (T_g) and a Young’s modulus of approximately 70–80 °C and 8–10 GPa, respectively, are optimum for low-K flip-chip packaging with eutectic solder bumps.     

Experimental study on the thermo-mechanical effects of underfill and low-CTE substrate in a flip-chip device

Moiré interferometry was used to analyze the thermal deformation of four flip-chip devices mounted on FR-4 substrate and a new multi-layer substrate, with and without underfill. Thermal loading was applied by cooling the devices from 100 °C to room temperature (25 °C). The effects of underfill and the low-CTE (coefficient of thermal expansion) substrate on thermal deformation were investigated. The experimental results showed that the underfill curved in a manner similar to the silicon chip. For the flip-chip devices mounted on the multi-layer substrate, the CTE mismatch between the silicon chip and substrate was reduced, and bending deformation decreased. Of the four flip-chip devices studied, the underfilled flip-chip device mounted on the multi-layer substrate had the least deformed solder balls.     

Comparing the Impacts of the Capillary and the Molded Underfill Process on the Reliability of the Flip-Chip BGA

In the assembly process for the conventional capillary underfill (CUF) flip-chip ball grid array (FCBGA) packaging the underfill dispensing creates bottleneck. The material property of the underfill, the dispensing pattern and the curing profile all have a significant impact on the flip-chip packaging reliability. Due to the demand for high performance in the CPU, graphics and communication market, the large die size with more integrated functions using the low-K chip must meet the reliability criteria and the high thermal dissipation. In addition, the coplanarity of the flip-chip package has become a major challenge for large die packaging. This work investigates the impact of the CUF and the novel molded underfill (MUF) processes on solder bumps, low-K chip and solder ball stress, packaging coplanarity and reliability. Compared to the conventional CUF FCBGA, the proposed MUF FCBGA packaging provides superior solder bump protection, packaging coplanarity and reliability. This strong solder bump protection and high packaging reliability is due to the low coefficient of thermal expansion and high modulus of the molding compound. According to the simulation results, the maximum stress of the solder bumps, chip and packaging coplanarity of the MUF FCBGA shows a remarkable improvement over the CUF FCBGA, by 58.3%, 8.4%, and 41.8% (66 $mu {rm m}$), respectively. The results of the present study indicates that the MUF packaging is adequate for large die sizes and large packaging sizes, especially for the low-K chip and all kinds of solder bump compositions such as eutectic tin-lead, high lead, and lead free bumps.      

A computational study on solder bump geometry, normal, restoring, and fillet forces during solder reflow in the presence of liquefied underfill

A computational survey was performed to evaluate the effect of volume and material properties on a concurrent underfilling and solder reflow manufacturing technique applied to flip-chip technology. Fillet geometry in addition to collapsed solder ball geometry and forces during solder reflow in the presence of liquefied underfill are reported. Targeted material properties included surface tension, wetting angles, and process parameters such as underfill volume. A regression model is presented representing over 1000 case studies completed using surface evolver. Also, a multiple ball model was developed to study the solder ball array behavior. Modeling results are presented. Application of this model for wafer applied coating underfill thickness prediction was also studied including the fillet forces added to a multiple-ball-model. Behavior and force studies combining all these effects were performed and are presented. Finally, a more realistic arrangement consisting of circular and square solder pad geometries combined is modeled for a single ball. The models results are expanded to include a multiball model employing a commonly used regression method. Solder joints were cross-sectioned and measured after reflow in the presence of a fluxing underfill for comparison to model predictions. The experimental results agree within 1.5%.     

Underfill of flip chip on organic substrate: viscosity, surface tension, and contact angle

In flip-chip packaging, an underfill is dispensed on one or two adjacent sides of the die. The underfill is driven by a capillary flow to fill the gap between the die and substrate. The application of an underfill reduces the stress to solder bumps and enhances the reliability of the solder joints. Underfill materials consist of epoxy or cyanate ester resins, catalyst, crosslinker, wetting agent, pigment, and fillers. Underfill materials are highly filled with the filler loading ranging from 40% to 70%. In terms of underfill material processing, fast flow and curing are desired for high throughput. The viscosity, surface tension, and contact angle are key material properties affecting the gap filling process. In order to achieve fast filling, it is required that an underfill material has low viscosity and low contact angle at dispensing temperatures. Due to curing of an underfill material at dispensing temperature, the viscosity increases with time, which complicates the underfill flow process. The rheological behavior of several underfill materials was experimentally studied. All the underfill materials showed strong temperature dependence in viscosity before the curing. The time dependent viscosity and curing of underfill materials were examined by a dynamic time sweep test. The effects of viscosity and curing behavior of underfill materials on underfill material processing were investigated. The material with a longer gel time had more stable viscosity at room temperature, and therefore longer pot life. Experimental methods were developed to measure the surface tension and the contact angle of underfills at temperatures over 100 °C. Results showed that the contact angle for underfill on a substrate was time dependent. The interaction between underfill and substrate affects not only gap filling, but also filleting. The effect of surface energies of flip-chip substrates on wetting angles was also studied. Experiment results showed that for the same underfill, the higher the surface energy of substrate, the better the filleting.     

Development of no-flow underfill materials for lead-free solderbumped flip-chip applications

No-flow underfill process in flip-chip assembly has become a promising technology toward a smaller, faster and more cost-efficient packaging technology. The current available no-flow underfill materials are mainly designed for eutectic tin-lead solders. With the advance of lead-free interconnection due to the environmental concerns, a new no-flow underfill chemistry needs to be developed for lead-free solder bumped flip-chip applications. Many epoxy resin/hexahydro-4-methyl phthalic anhydride/metal acetylacetonate material systems have been screened in terms of their curing behavior. Some potential base formulations with curing peak temperatures higher than 200°C (based on differential scanning calorimetry at a heating rate of 5°C/min) are selected for further study. The proper fluxing agents are developed and the effects of fluxing agents on the curing behavior and cured material properties of the potential base formulations are studied using differential scanning calorimetry, thermomechanical analysis, dynamic-mechanical analysis, thermogravimetric analysis, and rheometer. Fluxing capability of the developed no-flow formulations is evaluated using the wetting test of lead-free solder balls on a copper board. The developed no-flow underfill formulations show sufficient fluxing capability and good potential for lead-free solder bumped flip-chip applications     

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated     

Visco-elastic-plastic properties and constitutive modeling ofunderfills

The thermo-mechanical testing of HYSOL PP4526 underfill is reported, including the details of sample preparation and test procedures. It is found that the Young's modulus of the underfill depends on both temperature and applied strain rate. The constitutive framework proposed for solder alloys has been applied successfully to model the thermo-mechanical properties of the underfill in this paper. Excellent agreement between model predictions and experimental data is achieved, The test data and calibrated constitutive model can be used for the analysis and design of advanced electronic packages with underfills such as flip-chip packages