Picture Coding

A survey of recent German research in the field of picture coding is presented. The described coding methods are mainly based on extended differential pulse-code modulation (DPCM) techniques. A unified model of a feedback switched quantizer for picture coding is explained. Theoretical results show a 9-dB gain in SNR over that of DPCM. A simple realization is shown. For encoding the 1-MHz videotelephone signals, a two-stage coding system consisting of a two-dimensional DPCM in the first stage and a dot interlaced frame repeating codec in the second stage is described. A DPCM combined with a relevancy detector and runlength coder is used for coding the 5-MHz video signals of a high-resolution videotelephone. A special scanning technique assures compatibility with ordinary videotelephones. Good picture quality is obtained by coding the luminance and chrominance signals of color TV separately with DPCM and switched quantization into a 34 Mbit/s signal.     

Efficient Design Centering of High-Frequency Integrated Continuous-Time Filters

We apply ldquospace-mappingrdquo optimization for design centering high-frequency integrated continuous-time filters. By appropriately choosing the coarse model, a significant simplification of the space mapping technique is possible, since the coarse model design space is almost a translated version of the fine model design space. Graphical intuition is given for the simplified technique. A design example of a fifth-order 71.4-500-MHz constant-C scaled G_m-C Chebyshev ladder filter is presented. Measurement results from fabricated ICs are given.     

250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI

A 250-MHz, 16-b, fixed-point, super-high-speed video signal processor (S-VSP) ULSI has been developed for constructing a video teleconferencing system. Two major technologies have been developed. One is a high-speed large-capacity on-chip memory architecture that achieves both 250-MHz internal signal processing and 13.5-MHz input and output buffering. The other is a circuit technology that achieves 250-MHz operations with a convolver/multiplier, an arithmetic logic unit (ALU), an accumulator, and various kinds of static RAMs (SRAMs). A phase-locked loop (PLL) is also integrated to generate a 250-MHz internal clock. The S-VSP ULSI, which was fabricated with 0.8-μm BiCMOS and triple-level-metallization technology, has a 15.5-mm×13.0-mm area and contains about 1.13 million transistors. It consumes 7 W at 250-MHz internal clock frequency with a single 5-V power supply     

800 MHz mobile radio propagation prediction using Kalman filteringtechniques

A method is presented to derive a propagation model to predict the received median signal voltage for an 800-MHz mobile radio system. Results are given of an investigation into the performance of a particular model that was derived using this method. The method uses a Kalman filter that uses propagation measurements to derive a best fit for a particular propagation model to the measured data. The model that was derived is based on propagation measurements made in the State of Florida. The new propagation model uses a plane-Earth propagation model that is corrected with an environmental propagation loss term that takes into account the various environmental effects near the mobile unit. The parameters in the environmental propagation loss model were determined using a Kalman filter that computes minimum mean square estimates of the parameters using measured propagation data. The environmental propagation loss term accounts for the effects of Earth diffraction, hills, valleys, urban and suburban areas, bare and grass-covered ground, bushes, trees, swamps, and propagation over fresh and salt water. It was found that, with the 800-MHz propagation model derived with this method, the prediction error for the received median signal voltage had a standard deviation of 5.08 dB     

Wide-band dynamic modeling of power amplifiers using radial-basis function neural networks

A radial-basis function neural network (RBFNN) has been used for modeling the dynamic nonlinear behavior of an RF power amplifier for third generation. In the model, the signal's envelope is used. The model requires less training than a model using IQ data. Sampled input and output signals were used for identification and validation. Noise-like signals with bandwidths of 4 and 20 MHz were used. The RBFNN is compared to a parallel Hammerstein (PH) model. The two model types have similar performance when no memory is used. For the 4-MHz signal, the RBFNN has better in-band performance, whereas the PH is better out-of-band, when memory is used. For the 20-MHz signal, the models have similar performance in- and out-of-band. Used as a digital-predistortion algorithm, the best RBFNN with memory suppressed the lower (upper) adjacent channel power 7 dB (4 dB) compared to a memoryless nonlinear predistorter and 11 dB (13 dB) compared to the case of no predistortion for the same output power for a 4-MHz-wide signal.     

A diffuse scattering model for urban propagation prediction

A novel, simple diffuse scattering model based on a ray approach suitable for urban radio propagation is presented. The scattering model is arranged so that the main parameters, having a precise physical meaning, can be easily tuned using measurement results. The model is tested against 900-MHz measurements and the scattering contribution is shown to be important for both received power and channel dispersion in a typical microcellular case     

All-digital PLL using bulk-controlled varactor and pulse-based digitally controlled oscillator

This work presented a 150–450-MHz, all-digital phase-locked loop (ADPLL) implemented in a 0.18 μm CMOS process. The design utilizes bulk-controlled varactor and pulse-based digitally controlled oscillator (PB-DCO) providing a high timing resolution and a good jitter performance. The worst-case total locking time of the proposed ADPLL is 32 reference clock cycles. The divider used here divides by factors from 2 to 63. A test chip is implemented and verified. The RMS and peak-to-peak jitters are 6.7 and 44 ps, respectively, at 450-MHz. The peak-to-peak jitter is 2.0% at 450-MHz. When the multiplication of divider is varying at 150-MHz, the peak-to-peak jitters are less than 3.2%. The power consumption is 16.2-mW at 450-MHz. The core area of ADPLL is only 260 × 360 mm². This clock generator can be applied as re-usable silicon IP for system-on-chip (SoC) applications.     

900-MHz mobile radio propagation in the Copenhagen area

A comparative study of 900-MHz, 450-MHz, and 150-MHz mobile radio propagation characteristics performed in Copenhagen, Denmark is described. The three systems were compared with respect to usable coverage area, flutter characteristics, and transmission quality. A statistical method was used for the determination of the coverage area, the limits of which are defined by the contour line corresponding to 20-dB noise quieting at 90 percent of the locations. Flutter patterns were photographically recorded, and simultaneous recordings of voice signals received on the three systems were made on magnetic tape. Concluded is that when corrections are made for differences in transmitter power, antenna gain, receiver sensitivity, etc., and when the propagation losses are assumed to vary with frequency like the free space losses, the coverage areas obtained will be nearly identical. The increased flutter rate at 900 MHz apparently does not affect the transmission noticeably, and it must be generally concluded that the 900-MHz band will provide as good mobile radio performance as any of the lower bands.     

New radio paging system and its propagation characteristics

A radio paging system using a 200 band NRZ-digital code for the selective calling signal on new frequency bands is discussed. This system uses the 250-MHz band, and its propagation characteristics in urban areas, necessary for the radio system design, was measured in the Tokyo area. Distance versus median field strength characteristics in this band approximate that of the 150-MHz band. Building loss is 19.7 dB and is less than that of the 150-MHz band. Therefore, the new system will provide nearly the same grade of service as the former system using the 150-MHz band.     

A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning methodfor DLL replica

A 200-MHz double-data-rate synchronous-DRAM (DDR-SDRAM) was developed. The chip contains a delay-locked loop (DLL) which performs over a wide range of operating conditions. Post-mold-tuning allows precise replica programming. A 200-MHz intra-chip data bus is suitable for DDR operation     

A 1.2-μm BiCMOS sample-and-hold circuit with aconstant-impedance, slew-enhanced sampling gate

A new sampling gate circuit, with dual outputs functioning alternately in the track and hold modes, is integrated in an open-loop sample-and-hold circuit architecture achieving greater than 450-MHz small-signal input bandwidth and 100-MHz maximum sample rate. The sampling gate also incorporates slew enhancement techniques to achieve (+430 V/μs, -510 V/μs) slew rate and features a `built-in' buffer to maintain constant input impedance for both the track and hold modes, simplifying design of the front-end input buffer. Special on-chip clock generation circuits are used to minimize sampled pedestal (+4 mV). Power dissipation is less than 300 mW, including output driver. Measured harmonics are 58 dB down for a 2 V_p-p 20-MHz sine wave sampled at 100 MHz     

A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI

A 300-MHz 16-b fixed-point digital signal processor (DSP) core LSI has been developed for video signal processing. In order to achieve high performance, the DSP core LSI employs a parallel processing architecture, 300-MHz redundant binary arithmetic units, and a sophisticated high-performance electrical design. The DSP core LSI, which was fabricated with 0.5-μm BICMOS and triple-level-metallization technology, has a 3.9 mm×4.6 mm area, and contains about 57K transistors. It consumes 2 W at a 300-MHz clock frequency with a 3.3-V power supply. Measured clock skew and critical path delay are less than 80 ps and 2.6 ns, respectively     

Magnetoelastic bandwidth compression

A bandwidth compression process is described which uses the magnetoelastic normal modes of a ferrimagnetic crystal as independent subharmonic oscillators. The critical power level and mode density for this process are discussed and dynamic range is shown to be strongly dependent upon crystal geometry. Measurements have been made on a device with a 60-MHz input frequency and a 30-MHz output frequency. Spectrograms of voice signals before and after two-to-one bandwidth compression are presented and the possibility of obtaining bandwidth expansion is discussed briefly.     

Design techniques for high-throughput BiCMOS self-timed SRAMs

Design techniques for a high-throughput BiCMOS self-timed SRAM are described. A new BiCMOS read circuit using a pipelined read architecture and a BiCMOS complementary clocked driver (BCCD) are proposed to reduce the operating cycle time. A 8192×9-b dual-port self-timed SRAM designed using the proposed techniques achieved a clock cycle time of 3.0 ns, that is, a 333-MHz operating frequency, by SPICE simulation on model parameters for 0.8-μm BiCMOS technology. A high-speed built-in self-test (BIST) circuit was studied and designed for the 3.0-ns cycle SRAM. It is confirmed that the BIST circuit allows the 3.0-ns cycle SRAM to test at its maximum operating frequency     

Analysis and Design of a Novel Dual-Band Array Antenna With a Low Profile for 2400/5800-MHz WLAN Systems

A novel dual-band array antenna and its associated feed networks for 2400/5800-MHz wireless local area networks (WLAN) is proposed. The nested dual-band array is composed of a 2400-MHz band array formed by 16 (4$,times,$4) parallel-fed rectangular patches and a 5800-MHz band array formed by 64 (8 $,times,$8) hybrid-fed double-sided printed dipoles. The measured and simulated results are presented and analyzed. The relative impedance bandwidths and the peak gains of the 2400-MHz band and 5800-MHz band arrays reach 8%, 13% $({rm VSWR}<1.5)$, 24 dBi and 18 dBi respectively. The dual-band array has regular radiation patterns, high polarization purity and antenna efficiency, and it is suitable for integration with other microwave circuits and can be applied in other dual-band system by scaling its size. The design consideration for side lobe level (SLL) suppression by amplitude weighting combining the quarter-wavelength transformer and a small adjustment in the antenna geometry is discussed as well.      

Cole-cole dispersion models for aqueous gelatin-syrup dielectric composites

A dielectric composite is developed with permittivity ranging from 8 to 75 with selectable conductive and dielectric losses. The composite comprises gelatin, high fructose corn syrup (HFCS), NaCl, and water, and can be used to model soils, loams, and sands in the 200-MHz to 20-GHz range. A single-term Cole-Cole dispersion equation is developed with frequency-independent parameters being functions of component concentrations. Fits are provided for various soil samples and surrogate concentrations.     

Comparison of measured and predicted time dispersion and directionof arrival for multipath in a small cell environment

A number of three-dimensional (3-D) direction-of-arrival measurements in a small campus environment at 1845 MHz are described. The impulse responses and the power have been measured using an 80-MHz wide-band receiver applying correlation techniques. These measurements are compared with theoretical predictions made with a site-specific ray-based propagation predictor tool to determine the coherently reflected part of the signal. Furthermore, radiosity is applied as a model to determine the power scattered by the surfaces     

Dual-wideband monopole antenna using a modified half-sierpinski fractal gasket

A dual-wideband fractal monopole antenna for handheld terminals is proposed. A modified half-Sierpinski gasket patch is used to cover GPS, DCS1800, PCS1800, UMTS, IMT-2000, WiBro (Wireless Broadband Internet Service), Bluetooth, S-DMB (Satellite Digital Multimedia Broadcast) and WLAN bands. The proposed antenna exhibits two wideband frequency resonances. The measured -10-dB reflection bandwidths for two resonant frequencies are 55- (1517-2670-MHz) and 12.6- (5135-5828-MHz). The radiation characteristics and gain of the proposed antenna are also presented and discussed.     

A video codec LSI for high-definition TV systems withone-transistor DRAM line memories

A video codec LSI for high-definition television (HDTV) systems has been developed. By using a time-compressed integration encoding technique, it converts a 20.0-MHz bandwidth luminance signal and two 5.0-MHz chrominance signals into a compressed image signal at 48.6-MHz sampling frequency. It is useful in many HDTV application systems, such as 400-Mb/s digital transmission system, a video disk player system, or an analog transmission system. Over 288000 elements, including a 52-kb one-transistor DRAM (dynamic random access memory) line memory specially developed for this LSI, were integrated on a 12.16×12.10-mm² chip. A standard cell layout method and a 1.2-μm CMOS logic LSI process were used     

Computer-aided design and optimization of a broad-band high-frequency monolithic amplifier

A monolithic wide-band amplifier for applications in counters from dc to UHF frequencies has been realized. The use of computer-aided design techniques, using a transistor model, and a broad-band feedback configuration has resulted in a monolithic amplifier that previously could only be constructed in hybrid form. This paper describes the development of a new high-frequency transistor model and a dc-coupled monolithic high-frequency amplifier that incorporates a final masking step option to obtain a maximally flat response over a 700-MHz bandwidth.