2.5-V bipolar/CMOS circuits for 0.25-μm BiCMOS technology

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25-μm BiCMOS technology. A pair of ECL/CMOS level converters with built-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance     

BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 μm CMOS

A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 μm CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited ≈45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V     

BiCMOS circuit technology for a high-speed SRAM

BiCMOS circuit technology for a high-speed and large-capacity ECL-compatible static RAM (SRAM) is described. To obtain high-speed and low-power operation, a decoder with a pre-main decode configuration having an ECL-interface circuit and a word driver with BiCMOS inverter are proposed. A BiCMOS multiplexer with a single emitter-follower driver is also proposed. An optimization method for memory cell array configuration is presented that minimizes the total delay time and the total power dissipation of SRAMs. Circuit simulation results show that a 64-kbit ECL-compatible SRAM with an access time of less than 7 ns and a power dissipation of less than 1 W is obtainable     

CMOS/BiCMOS mixed design using tabu search

The problem of optimising mixed CMOS/BiCMOS circuits is solved using a tabu search. Only gates on critical sensitisable paths are considered. This strategy leads to a circuit speed improvement of >20% with a <3% increase in the overall circuit capacitance. Comparison and experimental results are presented     

Merged BiCMOS logic to extend the CMOS/BiCMOS performance crossoverbelow 2.5-V supply

The authors discuss the merged BiCMOS (MBiCMOS) gate, a unique circuit configuration to improve BiCMOS gate performance at low supply voltages. MBiCMOS maintains a measured delay and power-delay advantage over CMOS into the 2-V supply range, in a simple four-device gate that does not require any change in the standard BiCMOS processing sequence. In a 2-μm technology, MBiCMOS outperforms CMOS down to a 2.6-V supply. Gates designed for fabrication in a 0.5-μm technology and simulated using measured device parameters indicate that MBiCMOS can be used to extend the performance crossover voltage to below 2 V in the submicrometer regime. A full-swing version of the MBiCMOS gate (FS-MBiCMOS) is introduced. Simulations of 2-μm gates show FS-MBiCMOS/CMOS performance crossover voltages of 2.2 V     

High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology

The electrical characteristics of the parasitic vertical NPN (V-NPN) BJT available in deep n-well 0.18-/spl mu/m CMOS technology are presented. It has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of Early voltage, about 2 GHz of cutoff frequency, and about 4 GHz of maximum oscillation frequency at room temperature. The corner frequency of 1/f noise is lower than 4 kHz at 0.5 mA of collector current. The double-balanced RF mixer using V-NPN shows almost free 1/f noise as well as an order of magnitude smaller dc offset compared with CMOS circuit and 12 dB flat gain almost up to the cutoff frequency. The V-NPN operational amplifier for baseband analog circuits has higher voltage gain and better input noise and input offset performance than the CMOS ones at the identical current. These circuits using V-NPN provide the possibility of high-performance direct conversion receiver implementation in CMOS technology.     

Low-power CMOS/BiCMOS drivers and receivers for on-chipinterconnects

Novel low-voltage swing CMOS and BiCMOS driver/receiver circuits for low-power VLSI applications are proposed. Interconnect wire drivers with low output signal swing are employed. Special receivers provide single and double level conversion while minimizing the total driver/receiver transmission delay. These level converters have no DC power dissipation. At 3.3 V power supply voltage, the proposed circuits consume less power without delay penalty. The power saving is observed to be as high as 30%. At lower supplies further power and delay improvements are observed     

新型的芯片间互连用CMOS/BiCMOS驱动器

从改善不同类型 IC芯片之间的电平匹配和驱动能力出发 ,设计了几例芯片间接口 (互连 )用 CMOS/Bi CMOS驱动电路 ,并提出了采用 0 .5 μm Bi CMOS工艺 ,制备所设计驱动器的技术要点和元器件参数。实验结果表明所设计驱动器既具有双极型电路快速、大电流驱动能力的特点 ,又具备 CMOS电路低压、低功耗的长处 ,因而它们特别适用于低电源电压、低功耗高速数字通信电路和信息处理系统。     

High-speed BiCMOS technology with a buried twin well structure

A buried twin well and polysilicon emitter structure is developed for high-speed BiCMOS VLSI's. A bipolar transistor of high cutoff frequency (fT= 4 GHz) and small size (500 µm²) has been fabricated on the same chip with a standard 2-µm CMOS, without degrading the device characteristics of the MOSFET. Latchup immunity is improved due to the low well resistance of the buried layer. The well triggering current is a 0.5-1.0 order of magnitude higher than that of a standard n-well CMOS. To evaluate the utility of this technology, a 15-stage ring oscillator of the 2NAND BiCMOS gate is fabricated. The gate has a 0.71-ns propagation delay time and 0.25-mW power dissipation at 0.85-pF loading capacitance and 4-MHz operation. Drive ability is 0.24 ns/pF, which is 2.5 times larger than that of the equal-area CMOS gate.     

Substrate coupling evaluation in BiCMOS technology

The magnitude of switching noise coupled through common substrate in BiCMOS technology is analyzed. Noise dependence on collector resistance and buried layer doping of the noisy bipolar junction transistor (BJT) is obtained by means of simulation. It is observed that trends are different depending on bipolar transistor biasing: in common-collector, a low collector resistance is desired, while in common-emitter biasing, large values of Rc make the transistor less noisy. A test chip is fabricated in 3-μm BiCMOS technology to measure the substrate coupling produced by different BICMOS inverter gates. These experimental measurements show that noise increases with transistor size and collector resistance. Dependence on distance and speed of signal are also obtained, together with the effect of a guard ring     

A unified theory for mixed CMOS/BiCMOS buffer optimization

A simple yet realistic gate sizing theory is presented to optimize delay of a cascaded gate buffer. The theory is based on the fact that CMOS/BiCMOS gate delay is linearly dependent on fan-out f, that is the delay can be expressed as Af+B, where A and B are coefficients. The optimum fan-out f/sub OPT/ is shown to be approximated as e+B/1.5A for a gate chain. The theory covers various BiCMOS/CMOS gate types such as NANDs and NORs in a unified framework. The existence of spurious capacitance is shown to increase the size of all transistors compared with the case without the spurious capacitance.<>     

BiCMOS circuit technology for high-speed DRAMs

A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

SiGe BiCMOS technology for RF circuit applications

SiGe BiCMOS is reviewed with focus on today's production 0.18-/spl mu/m technology at f/sub T//f/sub MAX/ of 150/200 GHz and future technology where device scaling is bringing about higher f/sub T//f/sub MAX/, as well as lower power consumption, noise figure, and improved large-signal performance at higher levels of integration. High levels of radio frequency (RF) integration are enabled by the availability of a number of active and passive modules described in this paper including high voltage and high-power devices, complementary PNPs, high quality MIM capacitors, and inductors. Key RF circuit results highlighting the advantages of SiGe BiCMOS in addressing today's RF IC market are also discussed both for applications at modest frequencies (1 to 10 GHz) as well as for emerging applications at higher frequencies (20 to >100 GHz).     

Impedance boosting techniques based on BiCMOS technology

An impedance enhancement technique, based on a combination of bipolar and MOS devices, is presented. The technique uses negative active feedback action to boost the impedance level of a cascode circuit. This technique improves the gain of the conventional folded-cascode BiCMOS amplifier by the loop gain of the feedback loop. The BiCMOS-based impedance boosting circuit, compared to the CMOS version, offers the advantage of higher bandwidth together with higher output current capability. The SPICE simulations of a folded-cascode op amp based on this technique show that a 120 dB DC gain can be achieved. Application of the technique to a transducer resulted in a total harmonic distortion as low as 0.02% with 2 V_p-p input signals and an improvement of more than 10 dB in linearity, with respect to the case where no feedback was used     

Self-heating effects in a BiCMOS on SOI technology for RFIC applications

Self-heating in a 0.25 /spl mu/m BiCMOS technology with different isolation structures, including shallow and deep trenches on bulk and silicon-on-insulator (SOI) substrates, is characterized experimentally. Thermal resistance values for single- and multifinger emitter devices are extracted and compared to results obtained from two-dimensional, fully coupled electrothermal simulations. The difference in thermal resistance between the investigated isolation structures becomes more important for transistors with a small aspect ratio, i.e., short emitter length. The influence of thermal boundary conditions, including the substrate thermal resistance, the thermal resistance of the first metallization/via layer, and the simulation structure width is investigated. In the device with full dielectric isolation-deep polysilicon-filled trenches on an SOI substrate-accurate modeling of the heat flow in the metallization is found to be crucial. Furthermore, the simulated structure must be made wide enough to account for the large heat flow in the lateral direction.     

A high performance 0.35-μm 3.3-V BiCMOS technology optimized forproduct porting from a 0.6-μm 3.3-V BiCMOS technology

A 0.35-μm logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5-V version offers lower power and higher performance. A 3.3-V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6-μm 3.3-V BiCMOS process. A two-step design process for converting an existing production worthy 0.6-μm 3.3-V BiCMOS design to a 0.35-μm design is described. The silicon results are described     

Optimizing high voltage bipolar transistors in a smart-power complementary BiCMOS technology

The implementation of high voltage vertical bipolar transistors in a BiCMOS technology requires sufficient space for the extension of the collector-base depletion region. Assuming that layout design rules for high voltage devices are used, the open base breakdown voltage BV_ceo is only defined by the one-dimensional vertical doping profile through the n⁺-emitter, the p-base, the n-intrinsic and the n⁺-extrinsic collector, i.e. lateral effects can be neglected for this type of brakdown. This paper describes the derivation of simple equations for optimizing the n⁺pn⁻n⁺-structure. Closed-form analytical equations based on the impact ionization model from Fulop ([1] Solid St. Electron. 10, 39 (1967)) yield the dependence of the open base breakdown voltage BV_ceo on the transistor gain, doping level and width of the intrinsic collector.