非掺杂对称双栅的基于完整表面电势的核心模型

通过求解Poisson方程自洽地得到了表面电势随沟道电压的变化关系,从而推出了非掺杂对称双栅MOSFET的一个基于表面势的模型.通过Pao-Sah积分得到了漏电流的表达式.该模型由一组表面势方程组成,解析形式的漏电流可以通过源端和漏端的电势得到.结果标明该模型在双栅MOSFET的所有工作区域都成立,而且不需要任何简化(如应用薄层电荷近似)和辅助拟合函数.对不同工作条件和不同尺寸器件的二维数值模拟与模型的比较进一步验证了提出模型的精度.     

对称薄膜双栅nMOSFET模型的研究

利用对称薄膜双栅MOSFET在阈值电压附近硅膜中的常电位近似,以硅膜达到体反型时的泊松方程为基础,得到一个有效的双栅nMOS器件模型.考虑到薄膜双栅SOI器件的体反型特性,阈值电压处的表面势不再受限于传统的强反型界限(指2倍费米势),并运用跨导最大变化(TC)法对此模型进行分析,得到阈值电压和阈值电压处表面势的详细表达式;另外,还演示了薄膜双栅MOSFET的近乎完美的亚阈值斜率特性,其数值模拟结果与文献实验结果吻合较好.     

非对称异质双栅应变硅MOSFETs 二维模型研究

基于对二维泊松方程的精确求解,本文对全耗尽型非对称异质双栅应变硅MOSFET的二维表面势,表面电场,阈值电压进行了研究。模型结果和二维数值模拟器的结果很吻合。此外并对该器件的物理作了深入的研究。该模型对设计全耗尽型非对称异质双栅应变硅MOSFET器件有着重要的指导作用.     

基于表面势的N沟4H-SiC MOSFET I-V特性解析模型

报道了一种适于模拟 n沟 4H-Si C MOSFET直流 I-V特性的整体模型。该模型充分考虑了常温下 Si C中杂质不完全离化以及界面态电荷在禁带中不均匀分布的影响 ,通过解析求解泊松方程以及牛顿 -拉夫森迭代计算表面势 ,得到了表面电场以及表面势的分布 ,并以此为基础采用薄层电荷近似 ,计入栅压引起的载流子迁移率退化效应 ,导出了可用于所有器件工作区的统一漏电流解析表达式。当漏偏压为 1 0 V,栅压为 1 2 V时 ,模拟得到的饱和漏电流接近 40 m A。计算结果与实验值符合较好。     

异质栅非对称Halo SOI MOSFET亚阈值电流模型

在沟道源端一侧引入高掺杂Halo结构的异质栅SOI MOSFET,可以有效降低亚阈值电流.通过求解二维泊松方程,为该器件建立了亚阈值条件下的表面势模型.利用常规漂移.扩散理论,在表面势模型的基础上,推导出新结构器件的亚阈值电流模型.为了求解简单,文中给出了一种分段近似方法,从而得到表面势的解析表达式.结果表明,所得到的表面势解析表达式和确切解的结果高度吻合.二维器件数值模拟器ISE验证了通过表面势解析表达式得到的亚阈值电流模型,在亚阈值区二者所得结果吻合得很好.     

异质栅非对称Halo SOI MOSFET亚阈值电流模型

在沟道源端一侧引入高掺杂Halo结构的异质栅SOI MOSFET,可以有效降低亚阈值电流.通过求解二维泊松方程,为该器件建立了亚阈值条件下的表面势模型.利用常规漂移.扩散理论,在表面势模型的基础上,推导出新结构器件的亚阈值电流模型.为了求解简单,文中给出了一种分段近似方法,从而得到表面势的解析表达式.结果表明,所得到的表面势解析表达式和确切解的结果高度吻合.二维器件数值模拟器ISE验证了通过表面势解析表达式得到的亚阈值电流模型,在亚阈值区二者所得结果吻合得很好.     

一种基于载流子的双栅MOSFET解析模型

提出一种全新的基于载流子求解的双栅MOSFET解析模型.针对无掺杂对称双栅MOSFET结构,该模型由求解泊松方程的载流子分布和Pao-Sah电流形式直接发展而来.发展的解析模型完全基于MOSFET的基本器件物理进行直接推导,结果覆盖了双栅MOSFET所有的工作区:从亚阈到强反型和从线性到饱和区,不需要任何额外假设和拟合参数.模型的预言结果被2D数值模拟很好地验证,表明该解析模型是一个理想的双栅MOSFET建模架构.     

亚50nm自对准双栅MOSFET的结构设计

描述了一种用综合性方法设计的亚50nm自对准双栅MOSFET,该结构能够在改进的主流CMOS技术上实现.在这种方法下,由于各种因素的影响,双栅器件的栅长、硅岛厚度呈现出不同的缩减限制.同时,侧面绝缘层在器件漏电流和电路速度上表现出特有的宽度效应.建立了关于这种效应的模型,并提供了相关的设计指导.另外,还讨论了一种新型的沟道掺杂设计,命名为SCD.利用SCD的DG器件能够在体反模式和阈值控制间取得较好的平衡.最后,总结了制作一个SADG MOSFET 的指导原则.     

亚50nm自对准双栅MOSFET的结构设计

描述了一种用综合性方法设计的亚50nm自对准双栅MOSFET,该结构能够在改进的主流CMOS技术上实现.在这种方法下,由于各种因素的影响,双栅器件的栅长、硅岛厚度呈现出不同的缩减限制.同时,侧面绝缘层在器件漏电流和电路速度上表现出特有的宽度效应.建立了关于这种效应的模型,并提供了相关的设计指导.另外,还讨论了一种新型的沟道掺杂设计,命名为SCD.利用SCD的DG器件能够在体反模式和阈值控制间取得较好的平衡.最后,总结了制作一个SADG MOSFET 的指导原则.     

一种基于载流子的双栅MOSFET解析模型

提出一种全新的基于载流子求解的双栅MOSFET解析模型. 针对无掺杂对称双栅MOSFET结构，该模型由求解泊松方程的载流子分布和Pao-Sah电流形式直接发展而来. 发展的解析模型完全基于MOSFET的基本器件物理进行直接推导,结果覆盖了双栅 MOSFET所有的工作区:从亚阈到强反型和从线性到饱和区,不需要任何额外假设和拟合参数. 模型的预言结果被2D数值模拟很好地验证，表明该解析模型是一个理想的双栅MOSFET建模架构.     

倒掺杂沟道MOSFETs的研究

本文研究了一种倒掺杂沟道MOSFET。与传统的MOSFETs不同,这种器件采用沟道表面掺杂浓度低、体内掺杂浓度高的倒掺杂设计。基于Possion方程,建立了线性变掺杂的沟道倒掺杂模型,得出了器件表面电势以及漏极电流的表达式,研究了垂直于沟道方向上倒掺杂的陡峭程度对漏极电流、饱和驱动电流以及表面电势的影响。计算结果与二维仿真软件MEDICI模拟结果相符。     

A surface potential based drain current model for asymmetric double gate MOSFETs

In this paper, we present a generic surface potential based current voltage (I-V) model for doped or undoped asymmetric double gate (DG) MOSFET. The model is derived from the 1-D Poisson’s equation with all the charge terms included and the channel potential is solved for the asymmetric operation of DG MOSFET based on the Newton-Raphson iterative method. A noncharge sheet based drain current model based on the Pao-Sah’s double integral method is formulated in terms of front and back gate surface potentials at the source and drain end. The model is able to clearly show the dependence of the front and back surface potential and the drain current on the terminal voltages, gate oxide thicknesses, channel doping concentrations and the Silicon body thickness and a good agreement is observed with the 2-D numerical simulation results.     

A charge sheet model for MOSFETs with an abrupt retrograde channel Part I. Drain current and body charge

Analytical solutions to drain current, depletion and inversion charges for MOSFETs with an ideally abrupt retrograde doping profile in the channel are derived based on the charge sheet model. The validity of the analytical solutions is confirmed by comparing the modeling results with simulation data obtained using numerical calculations; the modeling and simulation results are in excellent agreement. It is shown that the inclusion of an intrinsic surface layer in the channel causes a voltage shift in the drain current, in accordance with experimental observations. For the depletion charge, an analytical expression principally identical to that for the uniformly doped body case is found with a simple replacement of the surface potential, ψ_s, by the potential at the interface between the intrinsic surface layer and the doped substrate, ψ_ξ.     

Compact model for long-channel cylindrical surrounding-gate MOSFETs valid from low to high doping concentrations

This paper presents a compact model for the electrostatic potentials and the current characteristics of doped long-channel cylindrical surrounding-gate (SRG) MOSFETs. An analytical expression of the potentials is derived as a function of doping concentration. Then, the mobile charge density is calculated using the analytical expressions of the surface potential at the surface and the difference of potentials between the surface and the center of the silicon doped layer. Using the expression obtained for the mobile charge, a drain current expression is derived. Comparisons of the modeled expressions with the simulated characteristics obtained from the 3D ATLAS device simulator for the transfer characteristics, as well for the output characteristics, show good agreement within the practical range of gate and drain voltages and for doping concentrations ranging from 10¹⁶ cm⁻³ to 5 × 10¹⁸ cm⁻³.     

Modelling of parameters for asymmetric halo and symmetric DHDMG n-MOSFETs

This article presents an analytical surface potential, threshold voltage and drain current model for asymmetric pocket-implanted, single-halo dual material gate and double-halo dual material gate (DHDMG) n-MOSFET (MOSFET, metal–oxide–semiconductor field-effect transistor) operating up to 40?nm regime. The model is derived by applying Gauss's law to a rectangular box, covering the entire depletion region. The asymmetric pocket-implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends along with the inner fringing capacitances at both the source and the drain ends and the subthreshold drain and the substrate bias effect. Using the surface potential model, the threshold voltage and drain currents are estimated. The same model is used to find the characteristic parameters for dual-material gate (DMG) with halo implantations and double gate. The characteristic improvement is investigated. It is concluded that the DHDMG device structure exhibits better suppression of the short-channel effect (SCE) and the threshold voltage roll-off than DMG and double-gate MOSFET. The adequacy of the model is verified by comparing with two-dimensional device simulator DESSIS. A very good agreement of our model with DESSIS is obtained proving the validity of our model used in suppressing the SCEs.     

基于自动微分技术的器件模型参数提取算法

自动微分 (AD)技术以非标准分析为理论基础 ,是计算机数值计算领域中的一种很有前途的方法。文中提出了基于 AD技术的器件模型参数提取算法 ,在 Visual C+ +平台编制了模型参数提取程序 ,对所建立的基于表面势的 MOSFET模型进行了有约束条件的参数提取。结果表明 ,算法收敛快、稳定性好、提取准确     

杂质非完全离化对SiC n-MOSFET电特性的影响

文章研究了SiC中杂质非完全离化对器件性能的影响.通过考虑场致离化效应,分析了空间电荷区电荷密度与表面势的关系,得出在SiC MOSFET反型条件下,可近似认为杂质完全离化.在此基础上,模拟了4H-SiC MOSFET的漏电流-栅压曲线和迁移率-栅压曲线.模拟结果与实验数据非常吻合.     

Characterization of interface degradation in deep submicron MOSFETs by gate-controlled-diode measurement

The gate-controlled-diode (GCD) characteristic of a deep submicron MOSFET is changed dramatically following a Fowler-Nordheim (FN) injection. The changes can be explained by the trap generation on the Si surface close to the channel/drain edge and the interface trap generation in the channel region. By examining the change in the reverse drain current under accumulation and inversion in the GCD measurements, the information of trap generation in the surface region close to the channel/drain edge is obtained (note that the trap generation in this region could be different from that in other interface regions); and by measuring the reverse drain current under depletion, the interface trap generation in the channel region is obtained.