Effect of dopant redistribution, segregation, and carrier trappingin As-implanted MOS gates

Anomalous capacitance-voltage behavior of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi₂ layer is reported. The C-V characteristics and specifically the inversion and accumulation capacitances are gate-bias-dependent and are strongly affected by annealing temperature, silicidation, and polysilicon gate microstructure (i.e. polysilicon versus amorphous gate). The results can be explained by insufficient As redistribution, coupled with carrier trapping, and As segregation at polysilicon grain boundaries and in TiSi₂. All these effects lead to the formation of a depletion region in the polysilicon gate and thus to the anomalous C-V behavior     

Decrease of gate oxide dielectric constant in tungsten polycidegate processes

The gate oxide thickness for tungsten (W) polycide gate processes is studied, with tungsten silicide (WSi_x) deposited either by chemical vapor deposition (CVD) or sputtering. For WSi_x deposited by CVD, it is found that the effective thickness of gate oxide as determined by CV measurement increases in all cases if the annealing temperature is 900°C or higher. However, high-resolution transmission electron microscopy (TEM) measurement indicates that the physical thickness does not change after a 900°C anneal. In this case, the dielectric constant of the gate oxide decreases by 7%. As the annealing temperature increases to 1000°C, CV and TEM measurements give the same thickness and the decrease of the dielectric constant disappears. In contrast, for WSi_x film deposited by sputtering, annealing at 900°C has no effect on the gate oxide thickness as measured by CV and TEM     

Anomalous C-V characteristics of implanted polyMOS structure in n+/p+ dual-gate CMOS technology

The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900°C/30 min to rapid thermal annealing at 1050°C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G_m of NMOS transistors with 125-Å Gate oxide thickness     

1/f noise in MODFETs at low drain bias

The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S_I/I² versus the effective gate voltage V_G=V_GS-V_off shows three regions which are explained. The observed dependencies are S_I/I²∝V_G ^m with the exponents m=-1, -3, 0 with increasing values of V_G. The model explains m =-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m=0 at large V_G or V_GS≅0 is due to the dominant contribution of the series resistance. In the region at intermediate V_G , m=-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance     

A comprehensive study on p+ polysilicon-gate MOSFET'sinstability with fluorine incorporation

It is reported that fluorine can jeopardize p⁺-gate devices under moderate annealing temperatures. MOSFETs with BF₂ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 ¹² cm^-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p⁺-gate revealed that the long gate-length device had abnormal abrupt turn-on I_d-V_g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I_d-V_g characteristics associated with long-gate-length p⁺-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p⁺-gate devices is presented. The incorporation of fluorine in the p⁺ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states     

Monte Carlo study of GaAs/Alx Ga1-xAsMODFETs: effects of AlxGa1-xAs composition

Monte Carlo methods are used to compare electronic transport and device behavior in n⁺-Al_xGa_1-xAs/GaAs modulation-doped field-effect transistors (MODFETs) at 300 K for x =0.10, 0.15, 0.22, 0.30, 0.35, and 0.40. The differences between the x=0.22 and x=0.30 MODFETs with respect to parasitic conduction in Al_xGa_1-xAs, gate currents, and switching times, are of particular interest. The donor-related deep levels in Al_xGa_1-xAs, are disregarded by assuming all donors to be fully ionized, and the focus is only on the confinement and transport of the carriers. The following quantities are studied in detail: transfer characteristics (I_D versus V _G), transconductance (g_m), switching speeds (τ_ON), parasitic conduction in Al_xGa _1-xAs, gate current (I_G), average electron velocities and energies in GaAs and Al_xGa_1-x As, electron concentration in the device domain, k-space transfer (to low mobility L and X valleys), and details of the real-space transfer process     

Comparison of I-V, CV, and chemical datafor quality control studies of SiOxNy films on Si

Capacitance-voltage (CV) and current-voltage (I- V) measurements for SiO_xN_y films are compared with chemical data in order to provide some diagnostic capabilities in relating aberrant electrical characteristics with contaminants incorporated in the insulator film structure. In-process monitoring of film quality (utilizing electrical characteristics and chemical data) is especially critical in very large-scale integration (VLSI) processing control where the films are utilized both as an integral part of specific semiconductor device processing steps or as part of the semiconductor device structure     

Optimized trench MOSFET technologies for power devices

Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V_DB =55 V (R_sp=0.2 mΩ-cm², k _D=5.7 Ω-pF) and V_DB=35 V (R_sp=0.15 mΩ-cm², k_D =4.3 Ω-PF) were developed where V_DB is the drain-source avalanche breakdown voltage, R_sp is the specific on-state resistance, and k_D=R _spC_sp is the input device technology factor where C_sp is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model     

The design and characterization of nonoverlapping superself-aligned BiCMOS technology

An optimal device structure for integrating bipolar and CMOS is described. Process design and device performance are discussed. Both the vertical n-p-n and MOS devices have non-overlapping super self-aligned (NOVA) structures. The base-collector and source/drain junction capacitances are significantly reduced. This structure allows complete silicidation of active polysilicon electrodes, cutting down the parasitic resistances of source, drain, and extrinsic base. The critical gate and emitter regions are protected from direct reactive ion etching exposure and damage. All shallow junctions are contacted by polysilicon electrodes which suppress silicide-induced leakage. An arsenic buried layer minimizes collector resistance and collector-substrate capacitance. A novel selective epitaxy capping technique suppresses lateral autodoping from the arsenic buried layer. Fully recessed oxide with polysilicon buffer layer is used to achieve a low defect density device isolation. CMOS with L_eff=1.1 μm and W _n/W_p=10 μm/10 μm exhibits averaged ring oscillator delay of 128 ps/stage. An n-p-n transistor with f_T, of 14 GHz and low-power emitter-coupled logic ring oscillator with a delay of 97 ps/stage have been fabricated     

A proposed chemically pumped laser based on theb→X transition in O2

Simple kinetics calculations demonstrate that the well-known electronic energy pooling reaction involving O₂(a ¹Δ) is capable of producing an effective population inversion in O₂(b¹Σ). The densities of O₂(a¹Δ) which are potentially achievable suggest that the extractable energy storage density of an O ₂(b→X) chemical laser might exceed 0.5 MJ/m³. The b→X emission lifetime measurements conducted under conditions of high relative O₂( b¹Σ) density reveal no evidence of rapid self-quenching effects which would be potentially detrimental to laser performance. The relatively long energy storage times predicted, together with freedom from reagent mixing requirements, make such a laser an attractive alternative to other existing and proposed short wavelength chemical lasers     

Electron transport in 0.15-μm gate In0.52Al0.48As/In0.53Ga0.47As HEMT

Magneto-transport and cyclotron resonance measurements were made to determine directly the density, mobility, and the effective mass of the charge carriers in a high-performance 0.15-μm gate In_0.52 Al_0.48As/In_0.53Ga_0.47As high-electron-mobility transistor (HEMT) at low temperatures. At the gate voltage V_G=0 V, the carrier density n _g under the gate is 9×10¹¹ cm^-2, while outside of the gate region n_g=2.1×10¹² cm^-2. The mobility under the gate at 4.2 K is as low as 400 cm²/V-s when V_G<0.1 V and rapidly approaches 11000 cm²/V-s when V_G>0.1 V. The existence of this high mobility threshold is crucial to the operation of the device and sets its high-performance region in V_G>0.1 V     

Correlation between 1/f noise and hFElong-term instability in silicon bipolar devices

Accelerated life tests with high-temperature storage and electric aging for n⁺-p-n silicon planar transistors were carried out. Current gain h_FE increases monotonously with time during the tests, and the h_FE drift is correlated with initial measured 1/f noise in the transistors, i.e. the drift amount significantly increases with the increase of noise level. The correlation coefficient of relative drift Δh_FE /h_FE and 1/f noise spectral density S_iB(f) is far larger than that of Δ h_FE/h_FE and initial DC parameters of the transistors. A quantitative theory model for the h _FE drift has been developed and explains the h _FE drift behavior in the tests, which suggests that the h _FE drift and 1/f noise can be attributed to the same physical origin, and both are caused by the modulation of the oxide traps near the Si-SiO₂ interface to Si surface recombination. 1/f noise measurement, therefore, may be used as a fast and nondestructive means to predict the long-term instability in bipolar transistors     

High-transconductance heterostructure Ga0.47In0.53As/InP metal-insulator-semiconductor field-effect transistorsgrown by chemical beam epitaxy

SiO₂ insulator is on top of an InP layer; current transport occurs, however, an in adjacent n-type Ga_0.47In_0.53As:Sn layer. A transconductance of g_m=300 mS/mm is obtained from depletion-mode MISFETs with a gate length of 1.2 μm. This MIS (metal-insulator-semiconductor) junction has a symmetric current-voltage characteristic and a low-leakage current of ~1 nA at ±2 V. High-frequency S-parameter measurements performed b probing devices on the wafers yield a unity current gain frequency of F _t=22.2 GHz and a maximum frequency of oscillation f _max=27 GHz     

The effects of boron penetration on p+ polysilicon gatedPMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p⁺ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V_FB , increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF₂ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi₂ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO ₂/Si interface     

Modeling hot-carrier effects in polysilicon emitter bipolartransistors

In self-aligned polysilicon emitter transistors a large electric field existing at the periphery of the emitter-base junction under reverse bias can create hot-carrier-induced degradation. The degradation of polysilicon emitter transistor gain under DC stress conditions can be modelled by ΔI_B∝I_R ^m+ntⁿ where n≈0.5 and m ≈0.5. The more complex relationships of Δβ(I _C, I_R, t) and β(I _C, I_R, t) result naturally from the simple ΔI_B model. Using these relationships the device lifetime can be extrapolated over a wide range of reverse stress currents for a given technology     

Electron emission from direct bandgap heterojunction capacitors

The rate of emission of electrons from an inversion layer at the interface between p-type GaAs and undoped Al_xGa_1-xAs (x=0.38) is measured using a transient capacitance technique at temperatures from 49.8 to 84.4 K and at various gate biases. A model based on physical mechanisms is developed that accurately describes the inversion charge leakage. The model parameters are adjusted within their limits of uncertainty to obtain the optimal fit of present theory to experiment. The fit results in estimation of δE_c=0.28 eV and tunneling effective mass m*=0.08 m^O, for Al_0.38 Ga_0.62As. The model is used to predict the storage characteristics of similar devices with lower GaAs doping and with an alternate barrier material     

1/f noise in GaAs filaments

A typical 1/f noise is excited in GaAs filament with the Hooge noise parameter of about α_H=2×10^-3 . The noise level increases in proportion to the square of the terminal voltage, and decreases approximately in inverse proportion to the total number of carriers within the device. A transition from the typical 1/f noise characteristics to the diffusion noise characteristics of MESFETs was observed when the electric field was increased above 1 kV/cm. The noise parameters were also investigated as a function of the device width between 2 and 200 μm. Deep levels within the n-GaAs active layer and the high electric field are the main factors of the nonideal 1/f characteristics     

Direct evidence of gate oxide thickness increase in tungstenpolycide processes

The increase of the effective gate oxide thickness for W-polycide processes is studied. The samples with as-deposited and annealed W polycide were analyzed by secondary ion mass spectrometry, transmission electron microscopy (TEM), and high-frequency CV measurements. The TEM cross section shows that the gate oxide thicknesses are ~244 and ~285 Å for as-deposited and 1000°C annealed samples, respectively. The TEM results agree with those from CV measurements. The TEM analyses provide direct physical evidence of an additional oxide thickness (~41 Å) during the W-polycide annealing     

In0.52Al0.48As/InxGa1-xAs (0.53⩽x⩽0.70) lattice-matched and strainedheterostructure insulated-gate FETs

The DC and microwave properties of In_0.52Al_0.48 Al/In_xGa_1-xAs (0.53⩽x⩽0.70) heterostructure insulated gate field-effect transistors (HIGFETs) with a quantum well channel design are presented. DC and microwave transconductances (g_m) are enhanced as the In content is increased in the InGaAs channel. An intrinsic microwave g _m value of 428 mS/mm and a K-factor of 1140 mS/mm-V have been obtained for 1.0-μm gate length with the 65% In channel devices. The sheet charge density, drift mobility, transconductance, current-gain cutoff frequency (f_T), and maximum oscillation frequency (f _max) all show a continuous improvement up to 65% In content ( f_T=22.5 GHz with 53% and f_T=27 GHz with 65% In; the corresponding f_max change is from 6.5 to 8 GHz). The device performance degrades as the In content is increased to 70%. DC and microwave characteristics show the presence of negative differential resistance (NDR) up to 2.7 GHz     

p-channel FET based on p/n double-quantum-well heterostructure

An experimental demonstration of a p-channel FET based on a heterostructure having vertically integrated p- and n-type quantum-well channels is discussed. The AlGaAs/GaAs heterostructure consists of a quantum well with an underlying p-region positioned above a second quantum well with an underlying n-region. The p-FET is fabricated with self-aligned p⁺ regions formed by zinc diffusion. Electrical characteristics for 1.5-μm gate lengths are nearly ideal in appearance with a maximum I_d of 90 mA/mm, a g _m of 80 mS/mm, and a g_m/g _d ratio of 140 at 77 K. The results demonstrate the viability of such stratified structures for the development of complementary integrated circuits or other circuits requiring integration of multiple device types