基于USRP的Link11A数据链仿真研究

阐述数据链系统的仿真，发射端可以根据Link11A数据链的既有协议进行信号生成，对于接收端的定时同步和频偏估计等关键技术存在着多种方案。探讨Schmidl&Cox定时同步算法，提出了一种适用于Link11A的定时同步算法，给出了接收端信号处理方案。使用GNU Radio和USRP结合的软件无线电技术对数据链系统进行方案验证。实验结果证明信号处理方案和验证方法的可行性。     

实现Matlab定时处理功能

为实施诸如定时数据采集、数据处理、文件存盘等定时处理任务，以实现实时仿真和控制，程序必须能够完成定时和计时功能。介绍了优秀科学计算软件Matlab实现定时处理功能的几种方式，并着重给出了用C语言按照MEX格式编写动态链接库，在Matlab环境中使用系统定时器资源的方法。最后给出了定时采集某工业实际对象的温度，利用Matlab强大的数值计算与处理功能建立系统温度模型的应用实例。文中给出的方法可作为Matlab环境中编制数据采集与处理程序，以及开发Matlab与外部程序接口时参考。     

SDPSK的调制与解调

详细分析SDPSK（Symmetrical DPSK）的调制特性，提出一种基带编解码方法及定时同步方法。基带编解码器由开关、延时单元和逻辑运算单元构成，不涉及复杂运算；而定时同步方法，直接通过基带信号运算得到同步时钟，不需要锁相环，运算量小。因此，所提出的基带编解码方法和定时同步方法非常适合硬件实现。仿真结果验证了算法的正确性。另外，通过对解调器性能的测试，分析了算法的局限性及应用范围。     

一种MC-CDMA系统的时间捕获算法

提出了一种估计低信噪比频偏多载波码分多址接入（MC-CDMA）系统定时偏差的新方法,通过采用一个特殊的PN序列,利用得到的时域序列具有的模最大值性和共轭对称性,同时采取峰值自叠加处理方法来确定定时同步起始位置。在高斯和多径衰落信道下进行了仿真,采用定时偏移的均值（mean）和均方误差（MSE）来衡量新算法的性能,验证了...     

全数字接收机中定时恢复的研究

定时恢复是全数字接收机中的核心技术之一,文章在传统的Gardner定时恢复理论基础上研究了一种改进的定时恢复方法.提出了一种改进的插值结构,并对控制器进行了改进.以四相移相键控(QPSK)信号为例进行了仿真验证,仿真结果表明上述方法可以很好地解决定时恢复问题.并可降低系统的实现成本.     

基于数据辅助的低滚降定时同步算法

突发信号的定时同步通常采用非数据辅助的定时误差估计算法进行定时误差估计。非数据辅助的定时误差算法实现简单,然而在低滚降条件下,估计性能会产生严重恶化,对系统同步性能影响较大。文章针对突发信号在低信噪比、低滚降系数的条件下,对定时同步困难的问题进行了研究,提出了基于一种数据辅助的定时误差估计算法,利用突发捕获处理中的相关值,实现了定时误差的准确估计,并给出了定时同步实现结构。通过计算机仿真对算法进行了验证,仿真结果表明,文章算法在低滚降低信噪比条件下可实现良好的同步。     

适于机动TDMA卫通站的开环网络同步方法

针对高速运动的TDMA卫星通信站可能引起较大的定时误差进而造成干扰的问题,提出一种开环网络同步方法,其对运动情况下卫通站至卫星径向距离的变化规律以及参考突发的接收参数建模,并利用Kalman滤波平滑和预测状态参数,从而在减小处理时延及信令开销的情况下实现精确突发定时.最后,通过仿真验证了其有效性及性能.     

一种星上多载波APSK信号定时恢复方法

APSK信号应用在基于MF-TDMA星上处理的卫星通信系统中增加了系统的灵活性,多载波APSK信号定时恢复是实现星上整体解调处理的一个关键步骤。针对多载波APSK信号的特殊性和星上资源的有限性,提出了一种基于2倍采样加内插的多载波APSK信号定时恢复方法,在多载波情况下该方法与常规的定时恢复方法相比能够减小一半的数据缓存量,为星上处理节约了大量宝贵的存储空间,具有处理时延小和对信号幅度不敏感的优点。通过仿真给出了本方法性能与内插滤波器阶数和运算数据长度的关系。仿真结果表明,该方法能够较好地完成星上多载波APSK信号的定时恢复。     

连续传输前馈符号定时恢复算法研究及实现

针对连续传输场景中符号定时实现相对复杂的问题,提出了一种基于插值滤波的前馈定时恢复算法,可很好地满足符号定时同步的要求,并且易于实现。对算法进行了功能和性能仿真,仿真结果表明,实现符号定时恢复的准确度高,定时后解调性能可接近理论值。基于FPGA硬件平台完成了该算法的实现,根据定时误差生成对应相位的符号时钟,并依此实现插值滤波,解决了数据切换点处符号定时不准确的问题,通过仿真验证表明可很好地应用于工程实践。     

一种MQAM系统定时误差检测的探讨

本文提出了一种适于数字信号处理实现的、多电平正交幅度调制系统的定时误差检测方法，并进行了分析。在３３２ＱＡＭ情况下进行了计算机仿真，实验结果表明，该方法有着良好的性能、较强的灵活性。     

Physical timing modeling for bipolar VLSI

An approach for the analytical timing modeling of bipolar VLSI circuits that is based on average branch current analysis and the parametric correction scheme is presented. The combination of these techniques permits complex delay-sensitive effects of bipolar digital circuits to be incorporated in the derivation of the bipolar delay models. The delay functions of two basic bipolar subcircuit configurations (the series-gated structure and the emitter follower) are derived using the proposed techniques. It is shown that accurate timing information for the high-speed bipolar digital circuit, such as ECL, CML, and BiCMOS, can be obtained by repeated processing of these subcircuit delay functions. The delay estimates obtained with these timing models have been shown to be accurate typically within 10% of SPICE estimates. Applications include switch-level timing simulation, timing analysis and verification cell optimization, and technology mapping     

平板电视画质改善IP核的研制

为改善平板电视显示器件特性引起的不足,提出研制画质改善IP核.该IP核采用数字图像处理技术,如图像细节自适应增强、色度瞬态特性改善等,从而显著提升了电视画面的质量.详细介绍该IP核的结构、开发流程及功能仿真和FPGA平台验证过程.作为嵌入式IP核在数字视频处理芯片DTV110中进行ASIC验证,验证结果表明该IP功能正确,对改善平板电视的画质有明显效果.     

A New Symbol Timing Recovery Technique for Burst Modem Applications

A fast symbol timing recovery technique for PSK signals is presented. For the carrier recovery and for the symbol timing recovery subsystems, a parallel processing of the received modulated signal is employed. Theoretically it is shown that the optimum delay is2/f_{c}and notT/2as published in the literature, where fcandTare the carrier frequency and the symbol interval, respectively. This technique has the advantage over the currently employed serial processing technique in faster acquisition of symbol timing and with it in faster overall system synchronization. Experimental verification of theoretical results is presented and applications in satellite and terrestrial microwave communication systems are discussed.     

Continuous-discrete interactions in chemical processing plants

This paper discusses important hybrid aspects of chemical processing plants. It is outlined that discrete phenomena occur both on the physical level and in the control of these plants. As the dynamics of the transformations of energy and material are predominantly continuous, large and complex hybrid systems arise. We focus on three different aspects of dealing with such systems: (1) Modeling and simulation of hybrid systems for the design and optimization of plants, controllers and operating strategies. We present powerful simulation environments that have been developed in recent years. (2) Validation of plant instrumentation and discrete controllers. These systems are largely responsible for the safe and economic operation of chemical plants and the protection of the workforce, and the environment. Techniques for the verification of discrete controllers for continuous processes are discussed, which are based on a discrete approximation of the continuous dynamics. (3) Scheduling of batch plants. For plants that are operated in a discontinuous fashion, the timing and sequencing of the operations are very important for the efficient use of the equipment. This leads to large mixed-integer optimization problems. For a typical example, we show how the process and the constraints can be modeled and describe an efficient solution algorithm     

An Automatic Functional Coverage for Digital Systems Through a Binary Particle Swarm Optimization Algorithm with a Reinitialization Mechanism

At present, functional verification represents the most expensive part of the digital systems design. Moreover, different problems such as: clock synchronization, code compatibility, simulation automation, new design methodologies, proper use of coverage metrics, among others represent challenges in this area. The automated test vector generation is involved in these problems. In this work, an automated functional test sequences generation for digital systems based on the use of coverage models and a binary Particle Swarm Optimization algorithm with a reinitialization mechanism (BPSOr) is described. Also, a comparison with other meta-heuristic algorithms such as: Genetic algorithms (GA) and pseudo-random generation is presented using different fitness functions, coverage models and devices under verification. The main strategy is based on the combination of the simulation and meta-heuristic algorithms to test the device behavior through the generation of test vector sequences. According to the results, the proposed test generation method represents a good alternative to increase the functional coverage during the automated functional verification of block-level digital systems verification.     

Statistical Performance Analysis and Estimation for Parallel Multimedia Processing

When parallelizing complex multimedia processing on multiple processors, the stochastic timing behavior should be carefully studied. Although there are already many papers on the performance analysis of stochastic parallel system, they are not targeted on multimedia processing. In this paper, first we study H.264/AVC encoder (running on x86) and QSDPCM encoder (running on TI TMS32C62) to characterize important aspects of the stochastic timing behavior in complex multimedia processing applications. It is shown that the variation and correlation are indeed very significant. In order to make systematic analysis feasible, we apply Stochastic Timed Marked Graph (STMG) as a formal model to capture essential timing related behaviors of parallel multimedia processing systems. Then, we show how the local timing variations and correlations interact and propagate to the global timing behavior; from this we conclude general parallelization guidelines. Furthermore, we develop an analytical performance estimation technique to derive the probability distribution of timing behavior for parallel multimedia processing systems that have correlated stochastic timing behaviors inside. The estimation technique is based on principal component analysis and approximations.     

数字信号处理IP的层次化设计与验证

对数字信号处理IP设计流程各个阶段的设计和验证的任务和目标进行了一般性探讨,提出了一种层次化的数字信号处理IP的设计、验证流程,并且给出设计实例.该流程的设计阶段包括理论算法设计、需求设定、定点算法设计和验证、电路接口和时序设计以及算法/软件/硬件协同验证,采用该流程能够有效地提高数字信号处理IP的设计和验证的效率.     

基于FPGA和ADV7123的VGA显示接口的设计和应用

数字图像信息在VGA接口显示器正确、完整地显示，涉及到时序的构建和数字图像信息的模拟化两方面，提出一种能够广泛应用的VGA显示接口方案，详细阐述了数字图像数据DA转化并输出到VGA接口显示器显示的方法，其中包括接口的硬件设计、视频DA转换器的使用方法、通过FPGA构造VGA时序信号的方法等等。最后提供了两种典型应用以及设计方法，一种用于图像采集处理结果的显示，另一种用于辅助前端视频设计。方案可以广泛应用于各种仪器，数字视频系统、高分辨率的彩色图片图像处理、视频信号再现等。     

Phase jitter≡timing jitter?

In digital communication systems, the periodicity of timing signals is often disturbed. While timing jitter has been adopted by the International Telecommunication Union (ITU) as the standardized measurement for such disturbances, phase jitter is often used instead in much of the current relevant literature. The fundamental concepts of timing jitter and phase jitter are examined and definitions are presented. A nonlinear relationship between timing jitter and phase jitter is developed, and a general rendition under which one can be approximated by the other is obtained. This condition is tested against the timing jitter and wander tolerance for digital equipment operating at 2048 kb/s, as specified in ITU-T Recommendation G.823     

Verification of Digital RF Processors: RF, Analog, Baseband, and Software

Single-chip RF SoCs are seeing widespread acceptance in wireless applications. In this paper we address the issue of design verification of single-chip RF SOCs in a framework that accepts RF input and analyzes receiver BER performance and transmitter output distortion and phase noise by processing several thousand packets of baseband information while compensation algorithms are simultaneously executed. No comprehensive methodology exists to date for designing such complex systems. This paper present a novel approach that allows building complex RF SoC systems based on VHDL modeling and simulation and opens up major avenues of model development for RF and analog circuits. This approach has been successfully applied to verify two generations of digital RF processors (DRP) in deep-submicron technologies