Robust ultrathin oxynitride dielectrics by NH3nitridation and N2O RTA treatment

In this paper, a method to grow robust ultrathin (E_OT=28 Å) oxynitride film with effective dielectric constant of 5.7 is proposed. Samples, nitridized by NH₃ with additional N₂O annealing, show excellent electrical properties in terms of very low bulk trap density, low trap generation rate, and high endurance in stressing. This novel dielectric appears to be very promising for future ULSI devices     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

Electrical characteristics of low temperature polysilicon TFT with a novel TEOS/oxynitride stack gate dielectric

This investigation is the first to demonstrate a novel tetraethylorthosilicate (TEOS)/oxynitride stack gate dielectric for low-temperature poly-Si (LTPS) thin film transistors (TFTs), composed of a plasma-enhanced chemical vapor deposition (PECVD) thick TEOS oxide/ultrathin oxynitride grown by PECVD N/sub 2/O-plasma. The stack oxide shows a very high electrical breakdown field of 8.4 MV/cm, which is approximately 3 MV/cm larger than traditional PECVD TEOS oxide. The field effective mobility of stack oxide LTPS TFTs is over 4 times than that of traditional TEOS oxide LTPS TFTs. These improvements are attributed to the high quality N/sub 2/O-plasma grown ultrathin oxynitride forming strong Si/spl equiv/N bonds, as well as to reduce the trap density in the oxynitride/poly-Si interface.     

Electrical properties of N2O/NH3 plasma grownoxynitride on strained-Si

Growth of ultrathin (<100 Å) oxynitride on strained-Si using microwave N₂O and NH₃ plasma is reported. X-ray photoelectron spectroscopy (XPS) results indicate a nitrogen-rich layer at the strained-Si/SiO₂ interface. The electrical properties of oxynitrides have been characterized using a metal-insulator-semiconductor (MIS) structure. A moderately low value of insulator charge density (6.1×10¹⁰ cm^-2) has been obtained for NH₃ plasma treated N₂O oxide sample. Nitrided oxide shows a larger breakdown voltage and an improved charge trapping properties under Fowler-Nordheim (F-N) constant current stress     

Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics

Capacitors with ultra-thin (6.0-12.0 nm) CVD Ta₂O₅ film were fabricated on lightly doped Si substrates and their leakage current (I_g-V_g) and capacitance (C-V) characteristics were studied. For the first time, samples with stack equivalent oxide thickness around 2.0 nm were compared with ultra-thin silicon dioxide and silicon oxynitride. The Ta₂O₅ samples showed remarkably lower leakage current, which not only verified the advantages of ultra-thin Ta₂O₅ as dielectrics for high density DRAM's, but also suggested the possibility of its application as the gate dielectric material in MOSFET's     

Enhanced hot-carrier degradation due to water-related components inTEOS/O3 oxide and water blocking with ECR-SiO2film

The authors point out that a TEOS/O₃-oxide layer used as an interlevel dielectric enhances hot-carrier degradation of MOSFETs due to the water-related components (water and/or silanols) contained in the layer. This results mainly from enhanced hot-electron trapping in the gate oxide and also from interface-trap generation. By applying an ECR-SiO₂ layer under the TEOS/O₃-oxide layer, tolerance against hot-carrier damage is improved to the level of MOSFETs without the TEOS/O₃ oxide. From ESR measurement results, it is found that the spin density of the ECR-SiO₂ film under the TEOS/O₃ oxide is two orders lower than that of the ECR-SiO ₂ film only. It is suggested that the dangling bonds in the ECR-SiO₂ film effectively trap water diffusing from the water-containing overlayer     

Comparison of electrical and reliability characteristics ofdifferent 14 Å oxynitride gate dielectrics

A comparison of RTNO, N₂O and N₂O-ISSG ultrathin oxynitride gate dielectrics fabricated by combining a remote plasma nitridation (RPN) treatment with equal physical oxide thickness of 14 Å is explored. The N₂O-ISSG oxynitride gate dielectric film demonstrates good interface properties, higher mobility and excellent reliability. This film by RPN treatment is thus attractive as the gate dielectric for future ultra-large scale integration (ULSI) devices     

Effects of Oxynitride Buffer Layer on the Electrical Characteristics of Poly-Silicon TFTs Using $hbox{Pr}_{2}hbox{O}_{3}$ Gate Dielectric

In this paper, we have developed high-k Pr₂O₃ poly-Si thin-film transistors (TFTs) using different N₂O plasma power treatments. High-k Pr₂O₃ poly-Si TFT devices using a 200-W plasma power exhibited better electrical characteristics in terms of high effective carrier mobility, high driving current, small subthreshold slope, and high I_ON/I_OFF current ratio. This result is attributed to the smooth Pr₂O₃/poly-Si interface and low interface trap density. Pr₂O₃ poly-Si TFT with a 200-W N₂O plasma power also enhanced electrical reliabilities such as hot carrier and positive bias temperature instability. All of these results suggest that a high-k Pr₂O₃ gate dielectric with the oxynitride buffer layer is a good candidate for high-performance low-temperature poly-Si TFTs.     

Novel N2O-oxynitridation technology for forming highlyreliable EEPROM tunnel oxide films

Ultrathin (≃6 nm) oxynitrided SiO₂ (SiO_xN_y) films have been formed on Si(100) by rapid thermal processing (RTP) in an N₂O ambient. It is demonstrated that with this technology the generation of electron traps in bulk SiO₂ and the low-field leakage during Fowler-Nordheim electron injection can be greatly reduced. This behavior of SiO_x N_y film can be explained by the idea that the trap sites are reduced by forming strong Si-N bonds in bulk SiO₂. This N₂O oxynitridation is viewed as a hopeful technology for forming ultrathin EEPROM tunnel oxide films     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents     

Investigation of hole-tunneling current through ultrathinoxynitride/oxide stack gate dielectrics in p-MOSFETs

The systematic investigation of hole tunneling current through ultrathin oxide, oxynitride, oxynitride/oxide (N/O) and oxide/oxynitride/oxide (ONO) gate dielectrics in p-MOSFETs using a physical model is reported for the first time. The validity of the model is corroborated by the good agreement between the simulated and experimental results. Under typical inversion biases (|VG|<2 V), hole tunneling current is lower through oxynitride and oxynitride/oxide with about 33 at.% N than through pure oxide and nitride gate dielectrics. This is attributed to the competitive effects of the increase in the dielectric constant, and hence dielectric thickness, and decrease in the hole barrier height at the dielectric/Si interface with increasing with N concentration for a given electrical oxide thickness (EOT). For a N/O stack film with the same N concentration in the oxynitride, the hole tunneling current decreases monotonically with oxynitride thickness under the typical inversion biases. For minimum gate leakage current and maintaining an acceptable dielectric/Si interfacial quality, an N/O stack structure consisting of an oxynitride layer with 33 at.% N and a 3 Å oxide layer is proposed. For a p-MOSFET at an operating voltage of -0.9 V, which is applicable to the 0.7 μm technology node, this structure could be scaled to EOT=12 Å if the maximum allowed gate leakage current is 1 A/cm² and EOT=9 Å if the maximum allowed gate leakage current is 100 A/cm²     

Effect of fluorinated silicate glass passivation layer on electrical characteristics and dielectric reliabilities for the HfO2/SiON gate stacked nMOSFET

The superior characteristics of the fluorinated hafnium oxide/oxynitride (HfO₂/SiON) gate dielectric are investigated comprehensively. Fluorine is incorporated into the gate dielectric through fluorinated silicate glass (FSG) passivation layer to form fluorinated HfO₂/SiON dielectric. Fluorine incorporation has been proven to eliminate both bulk and interface trap densities due to Hf-F and Si-F bonds formation, which can strongly reduce trap generation as well as trap-assisted tunneling during subsequently constant voltage stress, and results in improved electrical characteristics and dielectric reliabilities. The results clearly indicate that the fluorinated HfO₂/SiON gate dielectric using FSG passivation layer becomes a feasible technology for future ultrathin gate dielectrics applications.     

Low thermal-budget ultrathin NH3-annealedatomic-layer-deposited Si-nitride/SiO2 stack gate dielectricswith excellent reliability

We present novel ultrathin (EOT = 2.1 nm) atomic-layer-deposited (ALD) Si-nitride/SiO₂ stack gate dielectrics annealed in NH ₃ at a moderate temperature of 550°C. MOS capacitors are fabricated using the proposed dielectrics. Excellent performance in electrical stressing experiments is shown by the dielectrics. They also exhibit better interface quality, low bulk-trap density, low trap generation rate, and high long-term reliability in comparison with ALD Si-nitride/SiO₂ stack dielectrics without NH₃-annealing and conventional thermal SiO₂ dielectrics. The proposed stack-gate dielectrics appear to be very promising for ULSI devices     

Electrical characteristics of high quality La2O3 gate dielectric with equivalent oxide thickness of 5 Å

Electrical and reliability properties of ultrathin La₂O ₃ gate dielectric have been investigated. The measured capacitance of 33 Å La₂O₃ gate dielectric is 7.2 μF/cm² that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 Å. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm² at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3×10¹⁰ eV^-1/cm², and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO₂      

Interface characteristics of Ge3N4-(n-type) GaAs MIS devices

Passivation of GaAs surfaces was achieved by the deposition of Ge₃N₄ dielectric films at low temperatures. Electrical characteristics of MIS devices were measured to determine the interface parameters. From C-V-f and G-V-f measurements, density of interface states has been obtained as (4–6)×10¹¹ cm⁻² eV⁻¹ at the semiconductor mid-gap. Some inversion charge buildup was seen in the C-V plot although the strong inversion regime is absent. Thermally stimulated current measurements indicate a trap density of 5×10¹⁸−10¹⁹ cm⁻³ in the dielectric film, with their energy level at 0.59 eV.     

Characterizing Fluorine-Ion Implant Effects on Poly-Si Thin-Film Transistors With ${hbox{Pr}}_{2}{hbox{O}}_{3}$ Gate Dielectric

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) with high-k Pr₂O₃ as gate dielectric is investigated for the first time. Using the Pr₂O₃ gate dielectric can obtain a high gate capacitance density and thin equivalent-oxide thickness, exhibiting a greatly enhancement in the driving capability of TFT device. Introducing fluorine ions into the poly-Si film by fluorine ion implantation technique can effectively passivate the trap states in the poly-Si film and at the Pr₂O₃/poly-Si interface to improve the device electrical properties. The Pr₂O₃ TFTs fabricated on fluorine-implanted poly-Si film exhibit significantly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower off-state leakage current, and higher on/off current ratio, as compared with the control poly-Si Pr₂O₃ TFTs. Also, the incorporation of fluorine ions also improves the reliability of poly-Si Pr₂O₃ TFTs against hot-carrier stressing, which is attributed to the formation of stronger Si-F bonds. Furthermore, superior threshold-voltage rolloff characteristic is also demonstrated in the fluorine-implanted poly-Si Pr₂O₃ TFTs. Therefore, the proposed scheme is a promising technology for high-performance and high-reliability solid-phase crystallized poly-Si TFT.     

Enhanced injection in n++-poly/SiOx/SiO2/p-sub MOS capacitors for low-voltage nonvolatile memoryapplications: experiment

In this paper, n⁺⁺-poly/SiO_x/SiO₂/p-sub capacitors with enhanced electron injection under substrate accumulation are extensively studied. First, systematic investigation of the role of technology parameters in the PECVD deposition of the SiO_x films is presented. In particular, the effect of the silane dilution parameter on the device performance is investigated and the SiO_x film optimized in terms of reliability and electron injection enhancement. Then, investigation of the electrical behavior of n⁺⁺ -poly/SiO_x/SiO₂/p-sub MOS capacitors is presented. As a result, a picture of the space defect distribution in the SiO_x films is proposed. In SiO_x films, a relevant density of trapped charge adds to ionized impurities. In particular, the net charge is negative in the bulk of the dielectric, indicating that trapped electrons exceed all the other charge contributions. The space distribution of defects is strongly nonuniform and has the maximum in the vicinity of the SiO_x/SiO₂ interface. After dc current stress, the devices undergo electrical degradation, the dominant mechanism of degradation being the creation of interface hole traps. The trap generation model is based on the release of hydrogen and pairs generation in the SiO_x films. The time-scale of trap filling during the stress is tens of seconds, which suggests that the stress-induced traps are deep in the energy gap     

Study of the Reliability Impact of Chlorine Precursor Residues in Thin Atomic-Layer-Deposited HfO2 Layers

Atomic layer deposition (ALD) with HfCl₄ as a precursor is widely used for HfO₂ fabrication. Due to the nature of the precursor under study, i.e., HfCl₄ and H₂O, the presence of chlorine residues in the film due to insufficient hydrolysis is eminent. Obviously, the chlorine residue in the HfO₂ film is suspected to affect the quality of the HfO₂ film. In this paper, The authors reduced the concentration of chlorine residues by increasing the H₂O oxidant pulse time in between the deposition cycles from 0.3 to 10 and 90 s. Time-of-flight secondary ion mass spectrometry analysis shows that this decreases the chlorine concentration in the HfO₂ film by more than one order of magnitude. However, time-dependent dielectric breakdown analysis shows that the lifetime remains quasi unaffected (within identical error bars) for the different injection cycles. Charge pumping analysis was done by varying both pulse frequency and amplitude to investigate the creation of defects, but negligible differences were observed. Therefore, the presence of chlorine residues has no significant impact on the trap generation and reliability of ALD HfO₂ layers, and this result corresponded with the mobility result. The experimental picture is confirmed with first-principle calculations that show that the presence of chlorine residues does not induce defect levels in the bandgap of HfO₂     

Nitridation and post-nitridation anneals of SiO2 forultrathin dielectrics

A technique of post-oxidation annealing to improve the properties and long-term reliability of ultrathin (<100 Å) MOS gate dielectrics is discussed. In this technique, after oxidation, nitridation is done in NH₃, followed by a light reoxidation in O₂, and then an inert anneal in Ar or N₂. Using this technique, both optimum performance and reliability can be obtained without sacrificing either. NH₃ anneal of SiO₂ improved the hot-electron immunity, but degraded the interface quality. Good properties could be obtained by a strong reoxidation of the nitrided films, at the expense, however, of a substantial increase in the film thickness. Nitrogen and argon ambients were found to be equally effective at improving film properties. By annealing the film in an inert ambient following reoxidation of the nitroxide, fixed charge can be further decreased with little oxide grown, electron mobility in NMOS FETs increases further, and the hot-electron lifetime is much longer than that of the starting oxide     

Charge trapping and degradation in high-permittivityTiO2 dielectric films

Suitable replacement materials for ultrathin SiO₂ in deeply scaled MOSFETs such as lattice polarizable films, which have much higher permittivities than SiO₂, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric breakdown (TDDB), and capacitance-voltage (C-V) measurements were done on 190 Å layers of TiO₂ which were deposited through the metal-organic chemical vapor deposition (MOCVD) of titanium tetrakis-isopropoxide. Measurements of the high- and low-frequency capacitance indicate that virtually no interface states are created during constant current injection stress. The increase in leakage current upon electrical stress may be due to the creation of uncharged, near interface states in the TiO₂ film near the SiO₂ interfacial layer that give rise to increased tunneling leakage