A 0.18-μm CMOS 1.25-Gbps Automatic-Gain-Control Amplifier

A 1.25-Gbps automatic-gain-control (AGC) amplifier is presented and it has been fabricated in 0.18-mum CMOS technology. To achieve a constant settling time, this AGC amplifier with the proposed variable gain amplifier (VGA) is presented. The measured VGA has a gain tuning range of 28.5 dB from -10 to 18.5 dB, and its measured group delay is about 12.15 ns. For the bit-error rate of 10^-12, the sensitivity and the overload for this AGC amplifier are 25 and 430 mV, respectively. It achieves input dynamic range of 24.7 dB. The power dissipation is 43.2 mW from a single 1.8-V supply voltage. The chip area is 0.82 mm times 0.56 mm includes I/O pads.     

A Dual-Antenna Phased-Array UWB Transceiver in 0.18-μm CMOS

A dual-antenna ultra-wideband (UWB) transceiver in 0.18-mum CMOS for mode-1 OFDM applications employs the techniques of antenna diversity and integrated RF selectivity to improve robustness to interferers. Optimal selectivity in receiver and band flatness in transmitter are achieved by on-chip calibration of each band. The packaged device achieves an overall noise figure of 4.7 dB, an IIP3 of -0.8 dBm, a TX P1 dB of 3.1 dBm, and an error vector magnitude (EVM) of -27.2 dB for 480 Mb/s. The transmit output spectrum is fully compliant with FCC mask for UWB without any external bandpass filter     

A Ku-Band Frequency Synthesizer in 0.18-μm CMOS Technology

This letter presents a fully integrated frequency synthesizer implemented in a 0.18-mum foundry CMOS process. By employing a modified differential Colpitts voltage controlled oscillator to improve the tuning range and the phase noise, the integer-N frequency synthesizer demonstrates an output frequency from 14.8 to 16.9GHz, allowing wideband operations at Ku-band. Operated at an output frequency of 15GHz, the proposed synthesizer exhibits a reference sideband power of -50dBc and a phase noise of -104.5dBc/Hz at 1-MHz offset. The fabricated circuit consumes a dc power of 70mW from a 2-V supply voltage     

A 0.18-μm CMOS Balanced Amplifier for 24-GHz Applications

A 24-GHz balanced amplifier (BA) with a 45-dB gain is realized in 0.18-mum CMOS technology. An effective technique, pi-type parallel resonance, is proposed to boost the high-frequency gain of a MOSFET by resonating out the inherent capacitances. The miniaturized lumped-element coupler in the circuit occupies a chip area of only ~2% compared to that of the conventional transmission-line coupler. The BA consumes 123 mW from a supply voltage of 1 V. To the best of the authors' knowledge, the proposed CMOS BA presents the highest gain of 45.0 dB with a chip area of 0.97 times 0.63 mm² (core area: 0.78 times 0.43 mm²) among the published narrowband amplifiers with similar technologies and operation frequencies.     

Millimeter-Wave Bandpass Filters by Standard 0.18-μm CMOS Technology

Millimeter-wave (mm-wave) bandpass filters are presented using the standard 0.18-mum CMOS process. Without any postprocessing steps, thin film microstrip (TFMS) structure is properly constructed on the low-resistivity silicon substrate, aiming at reducing the substrate loss and crosstalk to a large extent. Using the broadside-coupled scheme, a tight coupling is achieved so as to make up a class of low-loss and broadband TFMS bandpass filters in the mm-wave range. To achieve a small size, one-stage and two-stage filters with sinuous-shaped resonators are designed and fabricated. A good agreement between the predicted and measured results has been observed up to 110 GHz     

A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-μm CMOS

A low-voltage low-power CMOS operational transconductance amplifier (OTA) with near rail-to-rail output swing is presented in this brief. The proposed circuit is based on the current-mirror OTA topology. In addition, several circuit techniques are adopted to enhance the voltage gain. Simulated from a 0.8-V supply voltage, the proposed OTA achieves a 62-dB dc gain and a gain-bandwidth product of 160 MHz while driving a 2-pF load. The OTA is designed in a 0.18-mum CMOS process. The power consumption is 0.25 mW including the common-mode feedback circuit     

A 60-GHz Millimeter-Wave Bandpass Filter Using 0.18-μm CMOS Technology

This letter presents the design and implementation of a 60-GHz millimeter-wave RF-integrated-circuit-on-chip bandpass filter using a 0.18-mum standard CMOS process. A planar ring resonator structure with dual-transmission zeros was adopted in the design of this CMOS filter. The die size of the chip is 1.148times1.49 mm². The investigations of sensitivity to the insertion loss and the passband bandwidth for different perturbation stub sizes are also studied. The filter has a 3-dB bandwidth of about 12 GHz at the center frequency of 64 GHz. The measured insertion loss of the passband is about 4.9 dB, and the return loss is better than 10 dB within the passband.     

A 32-GHz Rotary Traveling-Wave Voltage Controlled Oscillator in 0.18-μm CMOS

A millimeter-wave multiphase voltage-controlled oscillator (VCO) is presented. In order to facilitate high-frequency oscillation and to minimize the phase error caused by the device and layout mismatch, a rotary traveling-wave topology based on transmission lines with inductive loading is employed for the circuit implementation. Using a 0.18-mum CMOS process, the fabricated VCO provides half- quadrature output phases at 32 GHz. The measured output power and phase noise at 1-MHz offset are -9 dBm and -108 dBc/Hz, respectively. Operated at a supply voltage of 1.2 V, the power consumption of the proposed circuit is 54 mW.     

Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in 0.18-μm CMOS

This paper will discuss a number of circuit approaches which lower the power consumed by a current steering digital-to-analog converter while maintaining both DC and AC performance levels. An example design provides 14-bit resolution and 200 MSPS conversion rate in a one-poly four-metal (1P4M) 0.18-mum CMOS process. The inclusion of optional 3.3-V compatible devices allows operation over a supply range from 1.7 to 3.6 V. A power dissipation/conversion rate figure of merit of as low as 0.17 mW/MSPS was achieved for 1.8-V operation and as low as 0.28 mW/MSPS at 3.3 V. A measured single-tone SFDR of 70 dB is achieved at a 50-MHz output frequency, with a two-tone IMD of -75 dBc at 71 MHz output.     

An Ultra-Wide-Band 0.4–10-GHz LNA in 0.18-μm CMOS

A two-stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. With the common-gate configuration employed as the input stage, the broad-band input matching is obtained and the noise does not rise rapidly at higher frequency. By combining the common-gate and common-source stages, the broad-band characteristic and small area are achieved by using two inductors. This LNA has been fabricated in a 0.18-mum CMOS process. The measured power gain is 11.2-12.4 dB and noise figure is 4.4-6.5 dB with -3-dB bandwidth of 0.4-10 GHz. The measured IIP3 is -6 dBm at 6 GHz. It consumes 12 mW from a 1.8-V supply voltage and occupies only 0.42 mm²     

An Ultra-Wideband Distributed Active Mixer MMIC in 0.18-μm CMOS Technology

In this paper, a distributed circuit topology for active mixers suitable for ultra-wideband operations is presented. By employing nonuniform artificial transmission lines with the complementary transconductance stages in the Gilbert-cell multiplier, the proposed mixer demonstrates broadband characteristics at microwave frequencies while maintaining a high conversion gain (CG) with improved gain flatness. Using a 0.18-mum CMOS process, the proposed circuit is implemented, exhibiting a -3-dB bandwidth of 28 GHz. With a local-oscillator power of 3 dBm and an IF frequency of 10 MHz, the fabricated circuit has a CG of 12.5plusmn1 dB and an average input third-order intercept point (IIP₃) of 0 dBm within the entire frequency range. The fully integrated wideband mixer occupies a chip area of 0.87times0.82 mm² and consumes a dc power of 20 mW from a 2-V supply voltage     

1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18-μm CMOS Technology

A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated oscillators to align the clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated oscillator reset-phase control scheme causes the starting phase of gated oscillators to alternate repeatedly between 0deg and 180deg according to the current clock phase. A prototype chip was designed with the 0.18-mum CMOS technology, and a 1.25/2.5-Gb/s dual-mode operation was verified by measurement     

40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-μm CMOS

A novel circuit topology for high-gain distributed amplifiers is presented in this study. Based on the conventional distributed architecture, the gain cells are realized by cascading cas- code stages for gain enhancement. In addition, the stagger-tuning technique is extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to significant improvement in terms of the operating bandwidth and the gain flatness. With the proposed circuit architecture, two amplifiers are implemented in a standard 0.18-mum CMOS technology. The amplifier with a 3 times 3 configuration exhibits a gain of 16.2 dB and a 3-dB bandwidth of 33.4 GHz, while the one in a form of 2 times 4 demonstrates a gain of 20 dB and a bandwidth of 39.4 GHz. Consuming a dc power of 260 mW from a 2.8-V supply voltage, both circuits provide clear eye-opening with a pseudorandom bit sequence (PRBS) at 40 Gb/s.     

A Low Power Folded Mixer for UWB System Applications in 0.18-μm CMOS Technology

This letter presents a wideband mixer using a commercial 0.18-mum CMOS technology process for ultra-wideband (UWB) system applications. To achieve wideband frequency response and low dc power consumption for UWB system applications, the folded approach is utilized to reduce supply voltage as well as dc power consumption, and wideband input matching network is used to achieve wideband frequency response. The measured results show that the proposed mixer demonstrates a wideband frequency response from 0.2 to 16GHz with a conversion gain of better than 5.3dB. The dc power consumption is 15mW under a supply voltage of 1.8V, with a compact size of 0.68mmtimes0.65mm     

A 2.45-GHz 0.13-μm CMOS PA With Parallel Amplification

In this paper, a fully integrated 0.13-mum CMOS RF power amplifier for Bluetooth is presented. Four differential amplifiers are placed on a single chip and their outputs are combined with an on-chip LC balun structure. This technique allows to have a low impedance transformation ratio for each individual amplifier, and thus a lower power loss. The amplifier achieves a measured output power of 23 dBm at a supply voltage of 1.5 V and a drain efficiency of 35% and a global efficiency of 29%. The parallel amplification topology allows to efficiently control the output power which results in an efficiency improvement when the output power is reduced     

A Power-Efficient Clock and Data Recovery Circuit in 0.18 μm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 mum CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of 0.045 mm² /channel, with the total aggregate data bit rate of 20 Gb/s. The measured FTOL is plusmn3.5% and no error was detected for a 2³¹-1 pseudo-random bit stream (PRBS) input data for 30 minutes, meaning that the bit error rate (BER) is smaller than 10^-12. Meanwhile, a shared-PLL (phase-locked loop) with a wide tuning range and compensated loop gain has been introduced to tune the center frequency of all CDR channels to the desired value.     

A 2.2-μm-Pitch Single-Transistor Charge-Modulation Pixel in a 0.13-μm CMOS Process

This paper presents the investigation of a 2.2-mum-pitch single-transistor pixel designed in a 0.13-mum CMOS process. Based on charge-induced potential variation of the floating-body of the transistor, this single pixel device can be operated to perform photodetection, charge integration, signal readout, and reset. The main electrical characteristics of the pixel are evaluated by device modeling and simulations as well as measurements of test chips. With optimization of process and electrical parameters, testing results show a conversion factor of 47 muV/hole, a charge-handling capability of 3500 holes, a temporal noise of four holes, and a dynamic range of 40 dB.     

A 16–46 GHz Mixer Using Broadband Multilayer Balun in 0.18-μm CMOS Technology

A 16-46 GHz mixer using broadband balun fabricated in standard 0.18-mum CMOS process is demonstrated. The broadside-coupled balun with wide bandwidth and low insertion loss utilizes the inherent 3D multilayer structure in CMOS process. The mixer exhibits radio frequency bandwidth from 16 to 46 GHz with a conversion loss ranging from 13 plusmn 1.5 dB, and achieves bandwidth over 103% with a compact chip size of 0.24 mm².     

A 50-GHz Phase-Locked Loop in 0.13-μ m CMOS

A 50-GHz charge pump phase-locked loop (PLL) utilizing an LC-oscillator-based injection-locked frequency divider (ILFD) was fabricated in 0.13-mum logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The operating frequency range is increased by tracking the self-oscillation frequencies of the voltage-controlled oscillator (VCO) and the frequency divider. The PLL including buffers consumes 57 mW from 1.5/0.8-V supplies. The phase noise at 50 kHz, 1 MHz, and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs second-order harmonics at frequencies between 91.8 and 101 GHz. The output frequency of 101 GHz is the highest for signals locked by a PLL fabricated using the silicon integrated circuits technology.     

A 4-GS/s 4-bit Flash ADC in 0.18- μm CMOS

A 4-bit noninterleaved flash ADC implemented in 0.18-mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The ADC achieves a bit error rate of less than 10^-11 at 4 GS/s.