Low temperature wafer bonding for thin silicon film transfer

In this work, we investigate the low temperature (<200 °C) wafer bonding using wet chemical surface activation and we demonstrate high bonding strength sufficient to achieve the transfer of a thin silicon film of thickness less than 400 nm on top of another silicon wafer using spin-on-glass (SOG) film as an intermediate layer. The process developed is the first critical step that can enable three-dimensional (3D) integration and wafer level packaging of MEMS with electronic circuits.     

A study on effect of wafer bow in wafer-level BCB cap transfer packaging

This paper investigates the effects of wafer bow of Si carrier wafer to achieve high-yield BCB cap transfer in wafer-scale packaging. BCB caps are built-up on Si carrier wafer and then they are bonded and transferred to a target wafer. The height of BCB cap is 25 μm and the thickness of Si carrier wafer is 380 μm. Through several experiments, it is found that BCB cap transfer rate is mainly dependent on wafer bow of Si carrier wafer rather than that of the target wafer due to relatively large thickness of BCB caps. Therefore, Si carrier wafer bow with the BCB layers is investigated as a function of temperature. It is to figure out the effect of the wafer bow at certain temperature and applying pressure on BCB cap transfer rate. Through the study, it is found that zero wafer bow is very important for the cap transfer. Hence, aluminum metal layer is introduced to compensate the existing wafer bow of the Si carrier wafer.     

Adhesive wafer bonding with photosensitive polymers for MEMS fabrication

Adhesive wafer bonding is a technique that uses an intermediate layer (typically a polymer) for bonding two substrates. The main advantages of using this approach are: low temperature processing (maximum temperatures lower than 400°C), surface planarization and tolerance to particles contamination (the intermediate layer can incorporate particles with the diameter in the layer thickness range). The main bonding layers properties required by a large field of applications/designs can be summarized as: isotropic dielectric constants, good thermal stability, low Young’s modulus, and good adhesion to different substrates. This paper reports on wafer-to-wafer adhesive bonding using SINR^TM polymer materials. Substrate coating process as well as wafer bonding process parameters optimization was studied. Statistical analysis methods were used to show repeatability and reliability of coating processes. Features of as low as 15 μm size were successfully resolved by photolithography and bonded. An unique megasonic-enhanced development process of the patterned film using low cost solvent was established and proven to exceed standard development method performance.     

Microrivets for MEMS packaging: concept, fabrication, and strengthtesting

Microriveting is introduced as a novel and alternative joining technique to package MEMS devices. In contrast to the existing methods, mostly surface bonding, the reported technique joins two wafer pieces together by riveting, a mechanical joining means. Advantages include wafer joining at room temperature and low voltage, and relaxed requirements for surface preparation. The microrivets, which hold a cap-base wafer pair together, are formed by filling rivet holes through electroplating. The cap wafer has a recess to house the MEMS devices and also has through-holes to serve as rivet molds. The seed layer on the base wafer becomes the base of the rivet. The process requires only simple mechanical clamping of the wafer pair during riveting, compared with the more involved procedures needed for wafer bonding. Directionality of electroplating in an electric field is what makes this process simple and robust. Strength testing is carried out to evaluate the joining with microrivets. Different modes of rivet failure under different loading conditions are identified and investigated. Effective strength between 7 and 11 MPa was measured under normal loading with nickel microrivets. Joining strengths comparable to conventional wafer bonding processes, ease of fabrication with repeatability, and compatibility with batch fabrication show that microriveting is a feasible technique to join wafers for MEMS packaging, especially when hermetic sealing is not essential     

A mold and transfer technique for lead-free fluxless soldering and application to MEMS packaging

This paper demonstrates a technique to premold and transfer lead-free solder balls for microelectrocmechanical systems (MEMS)/electronics packaging applications. A reusable bulk micromachined silicon wafer is used to mold a solder paste and remove excess flux prior to transfer to a host wafer that may contain released MEMS. This technique has been used to fabricate low temperature thin film MEMS vacuum packages. Long term (>5 months) reliability of these packages at room temperature and pressure is demonstrated through integrated Pirani gauges. These packages have survived over 600 hours in an autoclave (130/spl deg/C, 85% RH, 2 atm) and more than 1300 temperature cycles (55/spl deg/C to 125/spl deg/C).     

Si基Cu/NiFe薄膜的生长及其粘附特性研究

微机械(MEMS)工艺和集成电路(IC)工艺中,在硅(Si)片上电铸高深宽比坡莫(NiFe)合金材料常出现脱落现象.提出了一种电铸NiFe合金材料的新方法,这种方法制作的合金薄膜厚度达200 μm时不脱落.此方法即对等离子刻蚀后的硅片溅射种子层铜(Cu),然后对种子层进行电镀,当其厚度达到约15 μm时,再进行NiFe合金的电铸.本文用扫描电镜、x射线衍射仪和剥离实验研究了薄膜粘附特性.研究结果表明当对种子层电镀后,随着Cu种子层厚度的增加,Cu/NiFe薄膜与基体的粘附强度增加,而薄膜的残余应力降低;同时Cu膜表面粗糙度增加,也增加了NiFe膜与Cu膜的粘附强度.     

基于局部与非局部线性判别分析和高斯混合模型动态集成的晶圆表面缺陷探测与识别

在复杂的半导体制造过程中,晶圆生产经过薄膜沉积、蚀刻、抛光等多项复杂的工序,制造过程中的异常波动都可能导致晶圆缺陷产生.晶圆表面的缺陷模式通常反映了半导体制造过程的各种异常问题,生产线上通过探测和识别晶圆表面缺陷,可及时判断制造过程故障源并进行在线调整,降低晶圆成品率损失.本文提出了基于一种流形学习算法与高斯混合模型动态集成的晶圆表面缺陷在线探测与识别模型.首先该模型开发了一种新型流形学习算法——局部与非局部线性判别分析法(Local and nonlocal linear discriminant analysis, LNLDA),通过融合数据局部/非局部信息以及局部/非局部惩罚信息,有效地提取高维晶圆特征数据的内在流形结构信息,以最大化数据不同簇样本的低维映射距离,保持特征数据中相同簇的低维几何结构.针对线上晶圆缺陷产生的随机性和复杂性,该模型对每种晶圆缺陷模式构建相应的高斯混合模型(Gaussian mixture model, GMM),提出了基于高斯混合模型动态集成的晶圆缺陷在线探测与识别方法.本文提出的模型成功地应用到实际半导体制造过程的晶圆表面缺陷在线探测与识别,在WM-811K晶圆数据库的实验结果验证了该模型的有效性与实用性.     

Wafer-level bonding and direct electrical interconnection of stacked 3D MEMS by a hybrid low temperature process

The presented fabrication technology enables the direct integration of electrical interconnects during low temperature wafer bonding of stacked 3D MEMS and wafer-level packaging. The low temperature fabrication process is based on hydrophilic direct bonding of plasma activated Si/SiO₂ surfaces and the simultaneous interconnection of two metallization layers by eutectic bonding of ultra-thin AuSn connects. This hybrid wafer-level bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects.     

Three-dimensional thin-film shape memory alloy microactuator withtwo-way effect

A novel thin film (micrometer thickness) shape memory alloy (SMA) micro actuator is presented in this paper. The thin film SMA with composition of approximately 50:50 nickel titanium (NiTi) is sputter-deposited onto a silicon wafer in an ultra high vacuum system. Transformation temperatures of the NiTi film are determined by measuring the residual stress as a function of temperature. The transformation temperature is independent of the presence of chromium (Cr) used as an adhesion layer, or being exposed to air before annealing. A mixture of hydrofluoric acid (HF), nitric acid (HNO₃) and deionized (DI) water is used to etch the film. Different etch masks are evaluated to protect the NiTi film during the etching. Among the masks tested, a thick photoresist (AZ-4620) produces the best result. The NiTi membrane is hot-shaped into a three-dimensional (3-D) dome shape using a stainless-steel jig. Results indicate the membrane exhibits two-way effect. The performance of the SMA micro actuator is characterized with a laser measurement system for deflection versus input power and frequency response     

Low‐temperature amorphous‐silicon backplane technology development for flexible displays in a manufacturing pilot‐line environment

Abstract— A low‐temperature amorphous‐silicon (a‐Si:H) thin‐film‐transistor (TFT) backplane technology for high‐information‐content flexible displays has been developed. Backplanes were integrated with frontplane technologies to produce high‐performance active‐matrix reflective electrophoretic ink, reflective cholesteric liquid crystal and emissive OLED flexible‐display technology demonstrators (TDs). Backplanes up to 4 in. on the diagonal have been fabricated on a 6‐in. wafer‐scale pilot line. The critical steps in the evolution of backplane technology, from qualification of baseline low‐temperature (180°C) a‐Si:H process on the 6‐in. line with rigid substrates, to transferring the process to flexible plastic and flexible stainless‐steel substrates, to form factor scale‐up of the TFT arrays, and finally manufacturing scale‐up to a Gen 2 (370 × 470 mm) display‐scale pilot line, will be reviewed.     

Membrane microcantilever arrays fabrication with PZT thin films for nanorange movement

Lead zirconate titanate (PZT) piezoelectric thin films have been prepared by sol-gel method to fabricate microcantilever arrays for nano-actuation with potential applications in the hard disk drives. In order to solve the silicon over-etching problem, which leads to a low production yield in the microcantilever fabrication process, a new fabrication process using DRIE etching of silicon from the front side of the silicon wafer has been developed. Silicon free membrane microcantilevers with PZT thin films of 1 μm in thickness have been successfully fabricated with almost 100% yield by this new process. Annealing temperature and time are critical to the preparation of the sol-gel PZT thin film. The fabrication process of microcantilever arrays in planar structure will be presented. Key issues on the fabrication of the cantilever are the compatible etching process of PZT thin film and the compensation of thin film stress in all layers to obtain a flat multi-layer structure.     

高量程MEMS加速度计封装工艺研究

对一种先进的双悬臂梁高量程MEMS加速度计的单芯片封装工艺进行了失效机理分析。手工粘贴芯片盖板可靠性不高,加速度计失效是由于胶粘剂(粘贴胶或灌封胶 )从芯片盖板和芯片的间隙流淌进入悬臂梁的过载保护间隙,阻碍了悬臂梁的摆动。高量程加速度计采用单芯片封装方法时,存在芯片正面和背面保护的可靠性问题,更好的封装方法是采用圆片级封装。黑胶不适宜用作加速度计的贴片胶,至少使用聚酰亚胺膜作背面保护时如此。     

Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

In this paper a novel process to bond and, at the same time, to electrically connect a silicon wafer to a glass wafer is presented. It consists of a low temperature anodic bonding process between silicon and glass by using a glass wafer with etched channels in order to contain metal tracks. The glass-to-silicon anodic bonding process at low temperatures (not exceeding 300°C) assures a strong mechanical link (Berthold et al. in Transducers 1999, June:7–10, 1999). The electrical contacts between the metal pads on the backside of a silicon wafer and the metal pads on the glass wafer are achieved by sintering and diffusion of metals due to a kind of thermo compression bonding. This bonding method permits a high vertical control due to a well-controlled etching of the cavity depth and to the thickness precision of both metallization (pads on silicon wafers and metal tracks on glass wafer). This IC-processing compatible approach opens up the way to a new electrical connection concept keeping, at the same time, a strong mechanical bond between glass and silicon wafers for an easier fabrication of a more complex micro-system.     

基于硅晶圆键合工艺的MEMS电容式超声传感器设计

针对目前电容超声传感器多采用表面工艺制备,存在振膜应力大、厚度均匀性控制差且表面需要沉积分立电极而造成传感器灵敏度低、归一化位移小、频率易偏差的缺点,提出基于硅晶圆键合工艺的MEMS电容超声传感器。采用应力小、厚度均匀的SOI顶层硅作为敏感单元的一体化全振微传感薄膜,无需沉积分立电极,易于加工且频率偏差小。通过下电极的区域化定义及巧妙互联,避免了非活跃区的寄生电容。通过ANSYS及MATLAB对所设计的5种工作频率在124 kHz～484 kHz之间、满足水下成像需求的传感器结构进行性能分析,表明传感器的电容变化量为650.62 fF/Pa～10.827 fF/Pa,满足现有条件的信号检测,输出电压灵敏度可达1.700 mV/Pa。与同频率指标的传统基于牺牲工艺而制备的金属-氮化膜堆栈结构对比表明,本结构频率可预测性高,偏差仅为0.0535%;振膜变形更均匀,归一化位移提高0.0432%以上;灵敏度平均提高11.9249 dB。     

A low-temperature thin-film electroplated metal vacuum package

This paper presents a packaging technology that employs an electroplated nickel film to vacuum seal a MEMS structure at the wafer level. The package is fabricated in a low-temperature (<250/spl deg/C) 3-mask process by electroplating a 40-/spl mu/m-thick nickel film over an 8-/spl mu/m sacrificial photoresist that is removed prior to package sealing. A large fluidic access port enables an 800/spl times/800 /spl mu/m package to be released in less than three hours. MEMS device release is performed after the formation of the first level package. The maximum fabrication temperature of 250/spl deg/C represents the lowest temperature ever reported for thin film packages (previous low /spl sim/400/spl deg/C). Implementation of electrical feedthroughs in this process requires no planarization. Several mechanisms, based upon localized melting and Pb/Sn solder bumping, for sealing low fluidic resistance feedthroughs have been investigated. This package has been fabricated with an integrated Pirani gauge to further characterize the different sealing technologies. These gauges have been used to establish the hermeticity of the different sealing technologies and have measured a sealing pressure of /spl sim/1.5 torr. Short-term (/spl sim/several weeks) reliability data is also presented.     

Neural Network Structures for Optimal Control of LPCVD Reactors

In this paper, a new approach of LPCVD reactor modelling and control is presented, based on the use of neural networks. We first present the development of a hybrid networks model of the reactor. The objective is to provide a simulation model which can be used to compute online the film thickness on each wafer. In the second section, the thermal control of a LPCVD reactor is studied. The objective is to develop a multivariable controller to control a space- and time-varying temperature profile inside the reactor. A neural network is designed using a methodology based on process inverse dynamics modelling. Good control results have been obtained when tracking space-time temperature profiles inside the LPCVD reactor pilot plant. Finally, global software is elaborated to achieve film thickness control in an experimental LPCVD reactor pilot plant, in order to get a defined and uniform deposition thickness on the wafers all along the reactor. Experimental results are presented which confirm the efficiency of the optimal control strategy.     

Low temperature transient liquid phase bonding of Au/Sn and Cu/Sn electroplated material systems for MEMS wafer-level packaging

This paper presents the development of a low temperature transient liquid phase bonding process for 8″ wafer-level packaging of micro-electro-mechanical systems. Cu/Sn and Au/Sn material systems have been investigated under varying bonding temperatures from 240 to 280 °C and different dwell times from 8 to 30 min. The used bond frame had a width of 80 μm and lateral dimensions of 1.5 mm × 1.55 mm. The sealing frame of the cap wafer consisted of Au and Cu, respectively, and Sn. The MEMS wafer only holds the parent metal of Au or Cu. High quality bonds were confirmed by shear tests, cleavage analysis, polished cross-section analysis using optical and electron microscope, energy dispersive X-ray spectroscopy and pressure cocker test. The samples showed high shear strength (>80 MPa), nearly perfect bond regions and no main failure mode in the cleavage analyses. Non-corroded Cu test structures confirmed the hermeticity.     

Gold metallizations for eutectic bonding of silicon wafers

Gold eutectic bonding of silicon wafers is a good candidate for wafer level vacuum packaging of vibrating MEMS: in this paper we investigated several e-beam evaporated metallizations stacks including a titanium adhesion layer, an optional diffusion barrier (Ni or Pt) and a gold film for eutectic bonding on Si and SiO₂/Si wafers. Interdiffusion in the multilayers for annealing temperatures (380–430°C) larger than the Au–Si eutectic temperature (363°C) and times corresponding to a bonding process was characterized by RBS, roughness and resistivity measurements. Au/Pt/Ti and Au/Ti/SiO₂ were found to have the best characteristics for bonding. This was confirmed by bonding experiments.     

Wafer-level plasma activated bonding: new technology for MEMS fabrication

Manufacturing and integration of MEMS devices by wafer bonding often lead to problems generated by thermal properties of materials. These include alignment shifts, substrate warping and thin film stress. By limiting the thermal processing temperatures, thermal expansion differences between materials can be minimized in order to achieve stress-free, aligned substrates without warpage. Achieving wafer level bonding at low temperature employs a little magic and requires new technology development. The cornerstone of low temperature bonding is plasma activation. The plasma is chosen to compliment existing interface conditions and can result in conductive or insulating interfaces. A wide range of materials including semiconductors, glasses, quartz and even plastics respond favorably to plasma activated bonding. The annealing temperatures required to create permanent bonds are typically ranging from room temperature to 400°C for process times ranging from 15–30 min and up to 2–3 h. This new technique enables integration of various materials combinations coming from different production lines.     

Gold metallizations for eutectic bonding of silicon wafers

Gold eutectic bonding of silicon wafers is a good candidate for wafer level vacuum packaging of vibrating MEMS: in this paper we investigated several e-beam evaporated metallizations stacks including a titanium adhesion layer, an optional diffusion barrier (Ni or Pt) and a gold film for eutectic bonding on Si and SiO₂/Si wafers. Interdiffusion in the multilayers for annealing temperatures (380–430°C) larger than the Au–Si eutectic temperature (363°C) and times corresponding to a bonding process was characterized by RBS, roughness and resistivity measurements. Au/Pt/Ti and Au/Ti/SiO₂ were found to have the best characteristics for bonding. This was confirmed by bonding experiments.