Viterbi译码器的应用及其硬件设计与实现

维特比译码器是人们广泛采用的卷积码的译码器,在IS-95,GSM,3GPP中都有广泛的应用.文中首先简单说明Viterbi译码算法原理,接着分析Viterbi译码算法设计及伪代码实现,根据TD-SCDMA卷积码编码方案,设计了一种采用软判决方式的维特比译码器,并采用合理的归一化方式,保证了计算路径值的过程中不会发生溢出.仿真表明:改进的译码器具有良好的性能.     

一种基于FPGA的Viterbi译码器的研究与设计

针对通信系统中传统维特比(Viterbi)译码器结构复杂、译码延时大、资源消耗大的问题,提出了一种新的基于FPGA的Viterbi译码器设计。结合(2,1,7)卷积编码器和Viterbi译码器的工作原理,设计出译码器的核心组成模块,具体采用3比特软判决译码,用曼哈顿距离计算分支度量,32个碟型加比选子单元并行运算,完成幸存路径和幸存信息的计算。幸存路径管理模块采用Viterbi截短译码算法,回溯操作分成写数据、回溯读和译码读,以改进的流水线进行并行译码操作,译码延时和储存空间分别降低至和。     

Viterbi译码中的路径度量存储管理

大约束度卷积码的Viterbi译码器硬件复杂度大,限制了其速度。该文分析了Viterbi译码器的结构,从路径度量存储管理着手,合理地组织了存储器结构,简化了ACS和度量存储器之间的接口电路。提高了译码速率,使译码器便于FPGA实现。     

大约束度Viterbi译码器中路径存储单元的设计

维特比(Viterbi)译码器由于其优良的纠错性能,在通信领域有着十分广泛的应用。用FPGA实现Viterbi译码算法时,其硬件资源的消耗与译码速度始终是相互制约的两个方面,通过合理安排加比选单元和路径度量存储单元可有效缓解这一矛盾。基于基4算法所提出的同址路径度量存储管理方法能在提高译码速度同时有效降低译码器的硬件资源需求。     

Viterbi译码在TD-SCDMA测试平台中的应用

根据3GPP的规定提出了TD-SCDMA网络测试平台中的Viterbi译码器的DSP实现方案。该方案兼顾了资源消耗和译码效率,提高了译码器的硬件结构和整体性能.通过对TD-SCDMA终端维特比译码的理解,设计出相应网络测试平台中的译码器。并给出了其DSP实现程序,利用CCS集成环境平台和TMS320C55XDSP芯片进行仿真分析。由仿真和测试结果表明,该实现方法在实际应用中检测效果很好。     

基于IP核的Viterbi译码器实现

Viterbi译码器在通信系统中应用非常普遍,针对采用DSP只能进行相对较低速率的Viterbi译码的问题,人们开始采用FPGA实现高速率Viterbi译码。本文首先简单描述了Viterbi译码的基本过程,接着根据Viterbi译码器IP核的特点,分别详细介绍了并行结构、混合结构和基于混合结构的增信删余3种Viterbi译码器IP核的主要性能和使用方法,并通过应用实例给出了译码器IP核的性能仿真。     

基于FPGA的高速Viterbi译码器优化设计和实现

卷积码作为信道纠错编码在通信中得到了广泛的应用,而其相应的Viterbi译码器随着约束度N的增大其硬件复杂度成指数增加,硬件复杂度的大小决定译码速度。采用预计算的思想,避免了常规算法中的重复计算;对Viterbi译码器的核心模块ACS进行了优化设计,提出了一种FPGA实现方案,简化了接口电路、提高了速度。     

基于FPGA的软判决Viterbi译码实现

根据系统高速、稳定的要求,采用FPGA技术实现了针对(2,1,7)卷积编码的软判决Viterbi译码器.考虑到芯片的速度、面积和功耗,通过对Viterbi译码和前端接口部分设计的若干优化算法进行研究和讨论,选择4bit量化、差分软译码、大回朔深度和最小状态判决准则等方案以保证性能.采用全并行ACS结构和寄存器交换法以提高速度,并且采用分支度量预计算、度量存储溢出控制及对译码器其他部分的优化设计,在保证时序稳定的情况下有效减少了硬件消耗.     

一种适用于导航系统的维特比译码器电路设计与仿真

设计了一种适用于导航系统的低功耗、串行维特比译码器电路.介绍了设计的维特比译码器电路的整体结构和各部分硬件电路的设计与特点,仿真结果显示设计的维特比译码器电路能够正常译码,并能纠正传输过程中的错误比特;SMIC0.18μm工艺下的综合结果表明译码器电路的面积只有4102门,功耗为399.514μW.     

一种高速Viterbi译码器的设计与实现

Viterbi算法是卷积码的最优译码算法.设计并实现了一种高速(3,1,7)Viterbi译码器,该译码器由分支度量单元(BMU)、加比选单元(ACSU)、幸存路径存储单元(SMU)、控制单元(CU)组成.在StratixⅡ FPGA上实现、验证了该Viterbi译码器.验证结果表明,该译码器数据吞吐率达到231Mbit/s,在加性高斯白噪声(AWGN)信道下的误码率十分接近理论仿真值.与同类型Viterbi译码器比较,该译码器具有高速、硬件实现代价低的特点.     

数字流水Viterbi译码器的VLSI设计

本文介绍了高速数字流水Ｖｉｔｅｒｂｉ译码器的ＶＬＳＩ设计。在符号４值系统的基础上，给出Ｖｉｔｅｒｂｉ算法的新的功能分解公式，并介绍了用于译码器实现的两个重要的快速运算部件ＡＤＤ和ＭＡＸ的原理及其现场可编程（序）门阵列（ＦＰＧＡ）实现。文中详细讨论了译码器的ＶＬＳＩ结构、设计和性能分析。本文给出的Ｖｉｔｅｒｂｉ译码器可塑性强，并具有高度的并行性和很高的数据吞吐率。     

An artificial neural net Viterbi decoder

The Viterbi algorithm is a maximum likelihood means for decoding convolutional codes and has thus played an important role in applications ranging from satellite communications to cellular telephony. In the past, Viterbi decoders have usually been implemented using digital circuits. The speed of these digital decoders is directly related to the amount of parallelism in the design. As the constraint length of the code increases, parallelism becomes problematic due to the complexity of the decoder. In this paper an artificial neural network (ANN) Viterbi decoder is presented. The ANN decoder is significantly faster than comparable digital-only designs due to its fully parallel architecture. The fully parallel structure is obtained by implementing most of the Viterbi algorithm using analog neurons as opposed to digital circuits. Several modifications to the ANN decoder are considered, including an analog/digital hybrid design that results in an extremely fast and efficient decoder. The ANN decoder requires one-sixth the number of transistors required by the digital decoder. The connection weights of the ANN decoder are either +1 or -1, so weight considerations in the implementation are eliminated. This, together with the design's modularity and local connectivity, makes the ANN Viterbi decoder a natural fit for VLSI implementation. Simulation results are provided to show that the performance of the ANN decoder matches that of an ideal Viterbi decoder     

A robust Viterbi decoder and its application to terrestrial HDTVbroadcasting

The conventional Viterbi (1967) decoder employing the Euclidean distance has been widely used and considered as the optimum one in the sense of maximum likelihood sequence decoding under the hypothesis of additive white Gaussian noise (AWGN). However, what will happen if the noise distributions of actual channels deviate from the assumed AWGN? A robust Viterbi decoder utilizing absolute distance is carefully examined. Analytical and numerical results show that this Viterbi decoder is more advantageous than the conventional Viterbi decoder for actual channels with various kinds of interference, particularly in the presence of impulsive noise. Finally the robust Viterbi decoder is applied to TCM-8VSB terrestrial HDTV broadcasting, achieving 0.5-1.0 dB SNR gains over the conventional Viterbi decoder on contaminated AWGN channels     

An effective simplifying scheme for Viterbi decoder

A Viterbi decoding algorithm with a scarce-state transition-type circuit configuration, namely the probability selecting states (PSS) mode decoder, is presented. The algorithm has reduced complexity compared to a conventional Viterbi decoder. It is shown that this method has three advantages over the general Viterbi algorithm: it is suitable to the quick look-in code, it applies the optimum decoding in a PSS-type decoder, and it makes full use of the likelihood concentration property. The bit-error-rate (BER) performance of a r=1/2, k=7 (147,135) code and PSS-type Viterbi decoder approximates the optimum performance of the standard Viterbi decoder and reduces the hardware of the conventional Viterbi decoder to about half     

一种高速Viterbi译码器的优化设计及Verilog实现

文章设计了一种高速Viterbi译码器，该设计基于卷积码编码及其Viterbi译码原理，完成了Viterhi译码的核心单元算法的优化，并采用Verilog语言编程实现了卷积码编码器和译码器。仿真和综合的结果表明本文设计的译码器速率达50Mbit／s，同时译码器的电路规模也通过算法得到了优化。     

Viterbi译码器的硬件实现

介绍了一种Vkerbi译码器的硬件实现方法。设计的基于硬判决的Viterbi译码器具有约束长度长（9)、译码深度深（64)的特点。为了兼顾硬件资源与电路性能两个方面，在设计中使用了4个ACS单元，并根据Xilinx Virtex系列FPGA的结构特点．利用FPGA内部的BlockRAM保存汉明距离和幸存路径，提高了译码速度。