Analysis of modified lateral PNP transistors

An analysis for modified lateral PNP transistors with an applied or built-in electric field in the base region is performed for several different cases. Improvement in operation is obtained for the modified devices and this is shown by comparing the results with unmodified equivalent structures.     

Simulation of PNP InAlAs/InGaAs heterojunction bipolar transistors

The performance of single heterojunction InAlAs/InGaAs PNP heterojunction bipolar transistors is modeled numerically and good agreement is found with experimental measurements. Peak experimental values of f_T=14 GHz, f_Max=22 GHz, β=170 and U=38 dB are obtained near a collector current density of 10⁴ A/cm² for a nonoptimized device     

III-V field-effect transistors for low power digital logic applications

Sustaining Moore’s Law of doubling CMOS transistor density every twenty four months will require not only shrinking the transistor dimensions, but also introduction of new materials and new device architectures to achieve the highest performance per watt of power dissipation. Compound semiconductor-based quantum-well field effect transistors have recently emerged as a promising transistor option for future ultra low-power logic applications. This paper reviews the opportunities and challenges in this exciting field of research.     

Base diffusion isolated transistors for low power integrated circuits

Base diffusion isolated transistors (BDI) designed for low power, nonsaturating, integrated circuits have been fabricated. Buried collectors are unnecessary in these low power devices, resulting in structures equivalent to discrete transistors in complexity of fabrication. A low-current power supply is required for isolation purposes. Transistor characteristics differ negligibly from those of standard transistors at collector currents <0.05 mA, and are satisfactory for application in linear circuits at currents up to at least 0.1 mA. Transistor fTis 80 MHz at 0.1 mA emitter current, 2 V collector voltage.     

A low cost and low power silicon npn bipolar process with NMOS transistors (ADRF) for RF and microwave applications

A silicon bipolar process for RF and microwave applications, which features 25-GHz double-polysilicon self-aligned npn bipolar transistors with 5.5-V BV/sub CEO/, optional 0.7-/spl mu/m (L/sub eff/) NMOS transistors with p/sup +/ polysilicon gates for switch applications, lateral pnp transistors, high and low valued resistors, p/sup +/ polysilicon-to-n/sup +/ plug capacitors, and inductors is described. The npn transistors utilize nitride-oxide composite spacers formed using sacrificial TEOS spacers, a process which is simpler than the previously reported composite spacer processes. Use of the composite spacer structure virtually eliminates problems relating to the extrinsic-intrinsic base link-up and reduces plasma induced damage associated with the conventional spacer process. Microwave and RF capabilities of the process up to several GHz are demonstrated by fabricating and characterizing RF amplifiers, low noise amplifiers, and RF switches.<>     

The future of bipolar power transistors

Silicon based bipolar power transistor (BPT) as a switching power transistor has been replaced by other superior power devices in the past two decades. This transformation is primarily due to the poor performance of the BPT. Among many problems of the BPT, low current gain and small safe operation area (SOA) caused by the second breakdown have been most detrimental to silicon BPT's fate. However, BPT performance based on newer materials, such as wide bandgap semiconductors, has not been previously studied. This paper systematically compares the BPTs based on wide bandgap semiconductor materials. Device figures-of-merit for conduction and switching losses are proposed. Comparison of the BPT based on total power loss is then provided. Based on this work, it is concluded that BPTs based on wide bandgap materials overcome the critical disadvantages of silicon BPTs, and are capable of switching power operation at several hundred kilohertz frequencies at very high current densities and voltages. Therefore, BPTs based on wide bandgap materials are still very attractive switching power devices for the future     

A theory and some characterisitcs of power transistors at high-level conditions

The concentration of injected carriers is large compared with the impurity doping concentration in the base region of a power transistor operating at high level. Carrier concentration and characteristics of a two-dimensional transistor model are calculated for this case. Emitter and base contacts are in the form of strips. Most of the injected emitter current reaches the collector while the remainder recombines in the slightly doped base region under the emitter, resulting in a current in the highly doped base contact. In addition, a recombination current generated in the base region under the base contact is added to this base current and results in a decrease of current gain. In order to analyze the base recombination current, a special transistor with divided collector contacts was prepared. In this way, the collector current due to the region under the emitter contact can be separated from the collector current due to the region under the base contact. The presented theory could be verified. Additional corrections are necessary, however, in the direction of the current in the slightly doped base region.     

Double-interdigitated power transistors

The results of a comprehensive investigation concerning the implementation of the double-interdigitated (TIL) concept in TO-3-packaged triple-diffused power n-p-n^--n transistors are reported. The ease of manufacturing is accompanied by a relaxation of the tradeoff between the doping and width of the p-base and the main transistor parameters, which is still a crucial issue in conventionally interdigitated switches. The advantages exhibited by TIL devices when compared with identical conventional interdigitated transistors processed simultaneously are discussed     

A process for high yield and high performance carbon nanotube field effect transistors

Carbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candidates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low subthreshold swing of 139 mV/dec, high transconductance of 1.27 μS, and high I_on/I_off ratio of 10⁶ can be easily obtained with Ti source/drain contact after a post annealing process. Record high yield of 74% has been demonstrated. On the basis of the proposed process, lots of high performance CNTFETs can be obtained easily for advanced study on the electrical characteristics of CNTFETs in the future.     

兼容纵向PNP，纵向NPN双极型晶体管的2·0um集成电路制造工艺的研究

自从1960年第一块集成电路问世以来,集成电路工业飞速发展,不断遭遇新的要求和挑战。至今仍在应用的传统双极工艺,能够同时提供纵向NPN晶体管和横向PNP晶体管,在实际应用过程中,在遇到要求高输出电流,大驱动能力的电路时,横向PNP晶体管的性能成为电路设计的瓶颈。研究表明在传统的双极工艺中,由于基区浓度由外延本身决定,因此掺杂浓度相对较低。同时横向结构决定了基区的宽度相对于纵向结构而言,大大的增加。因此导致了PNP双极晶体管的输出性能差强人意。基于上述分析,在对传统的结构进行修改之后,以增加工艺复杂性为代价,在保证原有结构的情况下,能够得到性能令人满意的纵向PNP晶体管。增加一个BLN2层次,以满足纵向PNP晶体管对于隔离的要求,增加NB层次,从而得到掺杂浓度远高于外延层的纵向PNP晶体管的基区。从而避免了横向PNP晶体管的缺陷。主要结论为：通过合理地安排工艺步骤,能够在对原有结构不产生影响的情况下,得到性能令人满意的纵向PNP晶体管。相比于原有的横向PNP晶体管,输出特性得到极大改善。     

Origin of 1/f noise in lateral PNP bipolar transistors

1/f noise was measured on lateral bipolar PNP transistors over a temperature range of 220<T<450 K. Noise power spectral density measurements were performed simultaneously across two resistors connected in series with base and collector. The equivalent base current noise source S_IB has two dominant components. One is S_IBE that is between the base and the emitter, in parallel with r_π. The other is S_IBC coming from the surface recombination current at the neutral base, between the base and the collector. The extracted S_IB exhibited a near square law dependence on base current I_B. The noise remained nearly constant when the temperature was below 310 K. However, it presented strong temperature dependence when the temperature was beyond 310 K. Two different models are proposed for the noise in different temperature regions. For the high temperature region, the surface recombination velocity fluctuation model is proposed, which indicates that the noise is coming from the fluctuations in the surface recombination velocity at the neutral base surface. The tunneling assistant trapping model is responsible for the low temperature region, where the noise source is the carrier trapping–detrapping by the defects in the spacer oxide covering the surface of the depletion layer.     

The low temperature strain sensitivity of MOS transistors

A theoretical and experimental study has been made of the effect of strain on metal oxide silicon transistors (MOST's) at low temperatures. The quantization of momentum of electrons which occurs in the inversion layer of n-channel MOST's alters the piezoresistance effect, and an analysis is given for the case of a single quantized sub-band. This analysis shows that under certain rather restrictive conditions the piezoresistance of the drain to source resistance of MOST's fabricated in the (111) plane of silicon can be independent of temperature. Experimental results were obtained from both n^?and p-channel transistors; a maximum sensitivity to strain usually occurred at about 100 K. At lower temperatures the strain sensitivity could be made fairly insensitive to temperature changes under appropriate conditions. However it is unlikely that strain gauges made from MOST's could rival conventional gauges for the measurement of strain at low temperatures.     

Nonplanar power field-effect transistors

This paper reviews the criteria involved in the design of silicon power field-effect transistors. Particular emphasis is placed on recent nonplanar structures which will, in the near future, present a serious challenge to bipolar power transistors as linear amplifiers and high-speed switches.     

Epitaxial VVMOS power transistors

The design aspects of a V-groove vertical-geometry power MOST (VVMOS) using a simple epitaxial-channel technology, are discussed in this paper. The process has several features including ease of fabrication, good threshold voltage controllability, and high breakdown voltage. Expressions for the on-resistance as a function of device parameters and for the device capacitances as a function of the geometric features of the transistor are derived. Experimental results on fabricated devices are presented.     

A low power current controllable single-input three-output current-mode filter using MOS transistors only

A novel circuit configuration for the realization of low power single-input three-output (SITO) current mode (CM) filters employing only MOS transistors are presented. The proposed circuit can realize low-pass (LP), band-pass (BP) and high-pass (HP) filter functions simultaneously at three high impedance outputs without changing configuration. Despite the other previously reported works, the proposed circuit is free from resistors and passive capacitors. Instead of passive capacitors; the gate-source capacitor of MOS transistor is used making the proposed circuit ideally suitable for integration. Compared to other works, the proposed filter has also the lowest number of transistors and lowest power consumption. The proposed circuit exhibits low-input and high-output impedances, which is highly desirable for cascading in CM signal processing. Moreover, it is center frequency can be electronically adjusted using a control current without a significant effect on quality factor (Q) granting it the highly desirable capability of electronic tunability. Transfer functions of the LP, BP and HP outputs are derived and the performance of the proposed circuit is proved through pre layout and post layout simulations at supply voltage of 1.8 V and using 0.18 μm CMOS process parameters. The power consumption and the required chip area are only 0.5 mW and 77.4 μm × 70.2 μm, respectively.     

Thermal characterization of power transistors

The idealized concept of thermal resistance as applied to power transistors is discussed. This concept must be used with care because two of the basic assumptions made in applying the concept to these devices are not valid. Contrary to these assumptions, it is shown that 1) the junction temperature of a power transistor is never spatially uniform, and 2) no unique value of thermal resistance can be defined for all operating conditions. Also, various electrical methods for measuring the junction temperature (thermal resistance) of power transistors are discussed with the emphasis placed on the emitter-only switching measurement technique, which is the preferred standard method of measurement. In addition, the generation and meaning of forward-biased safe-operating-area (SOA) limits are discussed, and it is shown that because of the presence of current crowding and the associated hotspots, the specified SOA limits often permit devices to be operated at dangerously high junction temperatures. Electrical measurement methods capable of determining the peak junction temperature as well as determining the onset of current crowding are described, and it is shown how these methods might be used for the generation of improved SOA limits.     

Pattern design of power transistors

The distribution of the emitter current density along the emitter stripe in the comb structure has been analytically obtained by taking into account the junction temperature and the sheet resistance of the diffused base layer, From this result the optimum length of the emitter stripe has been obtained.     

Heat transfer in power transistors

The internal heat transfer problem for a typical power-transistor structure has been solved analytically. The relations among current distribution, heat generation and temperature distribution have been derived. Usage of the resulting equations is illustrated by application to the most elementary problem, namely, uniform heat generation under the emitter.     

Recent developments in power transistors

Power transistors capable of providing five watts output are now in production. Because these units are relatively non-linear in their characteristics, large signal graphical analysis of their behavior is necessary. To facilitate this, the static characteristics of the grounded base, grounded emitter, and grounded collector circuits are presented for several temperatures. Since power transistors are seldom driven with a high impedance source, the input voltages must be known as well as the input currents. These characteristics are drawn to indicate both simultaneously on one chart. The power that must be removed from the junction of these transistors requires that the mounting for the transistor be thermally adequate to remove the heat without allowing the temperature of the Junction to exceed its critical value. The temperature power relationship is discussed and the theoretical size requirements for a heat dissipator are shown for free air convection and forced convection.