An experimental 1-Mbit BiCMOS DRAM

Three developments are proposed for high-performance DRAMs: a bipolar complementary MOS (BiCMOS) DRAM device structure featuring high soft-error immunity due to a p/SUP +/ buried layer; a high-speed circuit configuration of eight NMOS subarrays combined with BiCMOS peripheral drivers and BiCMOS data output circuitry; and BiCMOS voltage and current limiters lowering power dissipation as well as peak current. A 1.3 /spl mu/m 1-Mb DRAM is designed and fabricated to verify the usefulness of these BiCMOS DRAM technologies. Features of this chip include a typical access time of 32 ns, a typical power dissipation of 450 mW at a 60-ns cycle time, and chip size of 5.0/spl times/14.9 mm/SUP 2/.     

A reliable 1-Mbit DRAM with a multi-bit-test mode

A single 50V supply 1-Mb DRAM using a half V/SUB cc/ biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide world-line technology.     

A 23-ns 1-Mb BiCMOS DRAM

A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines the NMOS differential circuit on each pair of data lines with a common highly sensitive bipolar circuit. The resulting chip has been verified to have high-speed characteristics while maintaining a wide operating margin and a relatively small chip size of 62.2 mm², in spite of a 1.3-μm lithography level     

A 4-Mbit DRAM with trench-transistor cell

An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.     

An experimental 1-Mbit cache DRAM with ECC

A cache DRAM which consists of a dynamic RAM (DRAM) as main memory and a static RAM (SRAM) as cache memory is proposed. An error checking and correcting (ECC) scheme utilizing the wide internal data bus is also proposed. It is constructed to be suitable for a four-way set associated cache scheme with more than a 90% hit rate estimated to be obtained. An experimental cache DRAM with 1-Mb DRAM and 8-kb SRAM has been fabricated using a 1.2-μm, triple-polysilicon, single-metal CMOS process. A SRAM access time of 12 ns and a DRAM access time of 80 ns, including an ECC time of 12 ns, have been obtained. Accordingly, an average access time of 20 ns is expected under the condition that the hit rate is 90%. The cache DRAM has a high-speed data mapping capability and high reliability suitable for low-end workstations and personal computers     

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

Describes a 1-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A double-polysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3- mu m feature size. The chip has also been fabricated in a 0.9*shrunken version with an area of 67 mm/sup 2/, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAMs to be used in a broad new range of applications.<>     

A 4-Mbit DRAM with half-internal-voltage bit-line precharge

A single 5-V supply 4-Mb dynamic random access memory (DRAM) was developed by using a buried-storage-electrode memory cell, a half-internal-voltage bit-line precharge method combined with a constant voltage converter, and a high signal-to-noise ratio sensing scheme. The chip was designed in a double-polycide, single-Al, epitaxial substrate NMOS technology with a 0.8-/spl mu/m minimum design rule. As a result, a 4M word/spl times/1-bit DRAM with 95-ns typical access time and 99.2-mm/SUP 2/ chip area was attained by 10.58-/spl mu/m/SUP 2/ storage cells.     

A 1-Mbit DRAM with 33-MHz serial I/O ports

High-speed operation, a 33-MHz serial cycle, and a 10-ns serial data access time have been realized by internal serial/parallel conversion circuits, a newly designed I/O controller circuit, new dynamic register circuits, a divided sensing method, and an optimized layout design. The chip is fabricated with a 1.2-/spl mu/m double-level polysilicon and double-level aluminium n-channel MOS process technology. An optimized interlevel insulator realizes equivalent first- and second-level aluminium pitches for a compact chip design. The chip size is 5.88/spl times/11.2 mm/SUP 2/. This memory has high-speed input and output capability as well as random accessibility. These features are suitable for TV and VCR frame-memory-system applications.     

An experimental 4-Mbit CMOS DRAM

A 4-Mb dynamic RAM has been designed and fabricated using 1.0-/spl mu/m twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high /spl alpha/-particle immunity was achieved with this structure. One cell measures 3.0/spl times/5.8 /spl mu/m/SUP 2/ yielding a chip size of 7.84/spl times/17.48 mm/SUP 2/. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static-column-mode and fast-age-mode operation. The chip is usable as /spl times/1 or /spl times/4 organizations with a bonding option. Using an external 5-V power supply, the row-address-strobe access time is 80 ns at room temperature. The typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.     

A redundancy test-time reduction technique in 1-Mbit DRAM with amultibit test mode

To realize an efficient redundancy test using the multibit test (MBT) mode, a redundancy flag on a memory LSI tester and an effective redundancy technique which cooperates with the MBT mode have been introduced. This simple redundancy architecture needs only the RFLG (512 bits for the 1 M×1-bit DRAM) as a hardware option on a memory LSI tester. The program development time for the redundancy test has been shortened. Throughput improvement of six to ten times has been achieved in the actual 1-Mb DRAM redundancy test     

A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-linearchitecture

A 16-Mb dynamic RAM has been designed and fabricated using 0.5-μm CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3-μm² in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4×17.38 (93.85) mm² to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time     

Submicrometer Electron-Beam Direct Writing Technology for 1-Mbit DRAM Fabrication

A 1-Mbit DRAM with 0.5-/spl mu/m minimum linewidth is fabricated using variable shaped e-beam direct writing technology. A simple linewidth control technique using newly developed submicrometer resists is developed to achieve high resolution and better linewidth accuracy. In addition, a highly accurate registration technique is developed to ensure required overlay. These techniques are successfully used to achieve overlay accuracy of 0.04 /spl mu/m(sigma) and linewidth deviation of 0.018 /spl mu/m(sigma) in the fabrication.     

Submicrometer electron-beam direct writing technology for 1-Mbit DRAM fabrication

A 1-Mbit DRAM with 0.5-µm minimum linewidth is fabricated using variable shaped e-beam direct writing technology. A simple linewidth control technique using newly developed submicrometer resists is developed to achieve high resolution and better linewidth accuracy. In addition, a highly accurate registration technique is developed to ensure required overlay. These techniques are successfully used to achieve overlay accuracy of 0.04 µm(σ) and linewidth deviation of 0.018 µm(σ) in the fabrication.     

A 4-Mbit DRAM with 16-bit concurrent ECC

A 256 K-word×16-bit dynamic RAM with concurrent 16-bit error correction code (ECC) has been built in 0.8-μm CMOS technology, with double-level metal and surrounding high-capacitance cell. The cell measures 10.12 μm² with a 90-fF storage capacitance. A duplex bit-line architecture used on the DRAM provides multiple-bit operations and the potential of high-speed data processing for ASIC memories. The ECC checks concurrently 16-bit data and corrects a 1-bit data error. This ECC method can be adapted to higher-bit ECC without expanding the memory array. The ratio of ECC area to the whole chip is 7.5%. The cell structure and the architecture allow for expansion to 16-Mb DRAM. The 4-Mb DRAM has a 70-ns RAS access time without ECC and a 90-ns RAS access time with ECC     

A 1-Mbit CMOS DRAM with fast page mode and static column mode

A 1-Mb words/spl times/1-bit CMOS dynamic RAM fabricated with an advanced n-well CMOS technology is described. More than 2.2 million devices are integrated on a 62.5 mm/SUP 2/ silicon chip by utilizing an n-channel memory cell of triple-level poly Si structure and a 1.2-/spl mu/m feature size VLSI process. Novel CMOS circuit design techniques such as the half V/SUB cc/ bitline precharge scheme are successfully applied to realize the excellent performance combination of high-speed operation and low-power dissipation. The CMOS peripheral circuitry is capable of the new operating functions, fast page mode, or static column mode with metal mask options. The typical RAS access time is 56 ns, the active current is 30 mA at a 190-ns cycle time, and the standby current is 0.2 mA.     

An experimental 80-ns 1-Mbit DRAM with fast page operation

An experimental general purpose 5-V 1-Mb dynamic RAM has been designed for increased performance, high density, and enhanced reliability. The array consists of a one-device overlapped I/O cell with a metal bitline architecture. The cell measures 4.1 /spl mu/m by 8.8 /spl mu/m, which yields a chip size of 5.5 mm by 10.5 mm with an array to chip area ratio of 65.5%. The chip was designed in a double-poly single-metal NMOS technology with selected 1-/spl mu/m levels and an average feature size of 1.5 /spl mu/m. Key design features include a fast page mode cycle with minimum column precharge delay and improved protection for short error rate using a boosted word-line after sense amplifier set scheme. The CAS access time is 40 ns and the cycle is 65 ns at 4.5 V and 85/spl deg/C. The RAS access time is 80 ns and the cycle is 160 ns at 4.5 V and 85/spl deg/C with a typical active power of 625 mW. The chip is usable as a X1, X2, or X4 with the use of block select inputs and the selected package option. The package options include a 500-mil/SUP 2/ pin grid array module with 23 pins, and a 22 pin or 26 pin 300-mil surface solder plastic package.     

A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register

A single 3.3-V 16-Mbit DRAM with a 135-mm/sup 2/ chip size has been fabricated using a 0.5- mu m twin-well process with double-metal wiring. The array architecture, based on the twisted-bit-line (TBL) array, includes suitable dummy and space word-line configurations which suppress the inter-bit-line noise and bring yield improvement. The multipurpose register (MPR) designed for the hierarchical data bus structure provides a line-mode test (LMT), copy write, and cache access capability. The LMT with on-chip test circuits using the MPR and a comparator creates a random test pattern and reduces the test time to 1/1000. A field shield isolation and a T-shaped stacked capacitor allow the layout of a 4.8- mu m/sup 2/ cell size with a storage capacitance of 35 fF. These techniques enable the 3.3-V 16-Mbit DRAM to achieve a 60-ns RAS access time and 300-mW power dissipation at 120-ns cycle time.<>     

A 60-ns 4-Mbit CMOS DRAM with built-in selftest function

A 4-Mb CMOS DRAM measuring 6.9/spl times/16.11 mm/SUP 2/ has been fabricated using a 0.9-/spl mu/m twin-tub CMOS, triple-poly, single-metal process technology. N-channel depletion-type trench cells, 2.5/spl times/5.5 /spl mu/m/SUP 2/ each, are incorporated in a p-well. A novel built-in selftest (BIST) function which enables a simultaneous and automatic test of all the memory devices on a board is introduced to reduce the RAM testing time in a system. This function is effective for system maintenance and a daily start-up test even in a relatively small system. A high-speed low-power 4-Mb CMOS DRAM with 60-ns access time, 50-mA active current, and 200-/spl mu/A standby current is realized by widening the DQ line bus which connects the sense amplifiers with DQ buffers, thereby reducing the parasitic capacitance of the DQ lines.     

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz.<>     

A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure

Low-noise, high-speed circuit techniques for high-density DRAMs (dynamic random-access memories), as well as their application to a single 5-V 16-Mb CMOS DRAM with a 3.3-V internal operating voltage for a memory array, are described. It was found that data-line interference noise becomes unacceptably high (more than 25% of the signal) and causes a serious problem in 16-Mb DRAM memory arrays. A transposed data-line structure is proposed to eliminate the noise. Noise suppression below 5% is confirmed using this transposed data-line structure. A current sense amplifier is also proposed to maintain the data-transmission speed in common I/O lines, in spite of a reduced operating voltage and increased parasitic capacitance loading in the memory array. A speed improvement of 10 ns is achieved. Using these circuit techniques, a 16-Mb CMOS DRAM with a typical RAS access time of 60 ns was realized