A 35-ns 64K EEPROM

An extremely high-speed 8K/spl times/8 EEPROM has been fabricated in a 2-/spl mu/m double-poly CMOS floating gate technology. A typical address and chip enable access time of 35 ns has been achieved. Through a metal option, the device is compatible with 28-pin EEPROM, SRAM, or EPROM, or is a 24 pin bipolar PROM substitute. The high-speed access has been achieved with a fast single-ended sense amplifier, high-speed static bootstrapping techniques, a novel combination of static CMOS and depletion load technology, substrate bias, and high-performance layout. A new column and byte latch circuit implements a page-mode programming feature. Column redundancy implemented with EEPROM fuses increases manufacturability.     

A 50-ns CMOS 256 K EEPROM

A 32 K×8 EEPROM (electrically erasable programmable read-only memory), which operates with a single 5-V power supply and achieves 100 K cycle endurance, 50-ns typical read access time, and 1-ms page programming time, equivalent to 16 μs/byte, was designed. A double-poly, double-metal, n-well CMOS process with 1.25-μm minimum feature size was developed to manufacture the device. The required and optional extended JEDEC standards for software data protection and chip clear are implemented along with parity check, toggle bit, page-load timer, and data-protection status bit. A modified Hamming code, which uses four parity bits per byte, was implemented to detect and correct single-bit errors     

64kB电可擦除只读存储器研究与设计

文章通过对电可擦除可编程只读存储器工作原理的研究,掌握了该存储器的设计技术和工艺加工技术,特别是关键模块（如软硬件数据保护、页写、全片擦除等）的设计技术,在此基础上研制了一种存储容量为64kB的EEPROM。64kB EEPROM的特殊结构保证了电可擦除可编程存储器的高性能和可制造性;器件利用内部错误诊断来增强数据的耐久性,同时改进了数据的保存特性;同时可选择的软件数据保护机制用于预防误写入。有关方面研究工作将对后续同类产品的研制起到积极的作用。     

A 128 K flash EEPROM using double-polysilicon technology

An easily manufacturable 128 K flash EEPROM (electrically erasable programmable read-only memory) was developed based on a novel cell. Programming is achieved through hot-electron injection and erasing through electron tunneling from the floating gate to the drain. The cell is 20% larger than an EPROM cell and contains an integral series transistor which ensures selflimited erasing, reduces leakage, and increases the cell current. The flash EEPROM device can withstand thousands of program/erase cycles. Endurance failures are due to threshold window closing caused by electron trapping in the gate oxide. Typical erasure time is 1 s to clear the entire memory.     

A 5 V only one-transistor 256 K EEPROM with page-mode erase

Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is fiver per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5 μm design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7×8 μm² and the chip size is 5.55×7.05 mm². The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC     

Hi-MNOS II Technology for a 64-kbit Byte-Erasable 5-V-Only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 /spl mu/m and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180/spl mu/m2, a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of /spl plusmn/1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10/sup 4/ write/erase cycles.     

Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 µm and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180 µm², a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of ± 1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10⁴write/erase cycles.     

A fault-tolerant 64K dynamic random-access memory

A 64K dynamic MOS RAM with features and performance fully compatible with current 16K RAM's has been designed and characterized. The memory cell is a one-transistor-one-capacitor structure, standard except for a polysilicon bit line. A dual-32K architecture, along with partial selection and stepped recovery, holds power and peak current values below those of 16K parts. Spare rows and columns, which can be substituted for defective elements by the laser opening of polysilicon links, enhance yield. Worst case column enable access time of the memory is 100 ns, row enable access time is 170 ns, and only 128 cycles within 4 ms are needed to refresh the device.     

A process-tolerant out-of-band blocker rejection technique for SAW-less receivers

In this paper, an active filtering technique is presented which is capable of filtering the out-of-band blockers in wireless receivers. The concept is based on the feedforward cancellation technique where a blocker replica is subtracted at the output of the low-noise amplifier (LNA). In contrast to the previously reported feedforward cancellation methods, exact gain and phase matching are easily obtained in the proposed architecture to produce a highly selective narrowband frequency response at the output of the LNA with wide rejection bandwidth. For the proof of concept, the system is implemented in a 65 nm CMOS technology. It occupies a total area of 0.8 mm² and the current consumption is 24 mA from a 1.2 V supply. The system post-layout simulations showed a blocker rejection of more than 33 dB for blocker signals 100 MHz away from the desired signal when the feedforward path is activated. The noise figure (NF) of the entire system is 3.8 dB that degrades to 5.8 dB when the feedforward path is activated.     

A 15-ns CMOS 64K RAM

The RAM was built using a technology with self-aligned TiSi/SUB 2/, single-level metal, an average minimum feature size of 1.35 /spl mu/m, and a minimum effective channel length of 1.1 /spl mu/m. An access of 10 ns is possible with the word line stitched on a second level of metal and some minor redesign. High speed is achieved through innovative circuits and design concepts. Novel CMOS circuits include a sense-amp set signal generator, a row decoder, and an input circuit. A layout-rule-independent graphics tool, which was used for the artwork design, is discussed.     

A 25 ns 64K static RAM

A high-performance 64K/spl times/1-bit CMOS SRAM is described. The RAM has an access time of 25 ns with active power of 350 mW and standby power of 15 mW. The access time has been obtained by using a 1.5 /spl mu/m rule CMOS process, advanced double-level A1 interconnection technology, an equalizer circuit, and a digit line sense amplifier that is the first sense amplifier directly connected to digit lines. The WRITE recovery circuit is effective in improving WRITE characteristics, and a block selecting circuit was used for low power dissipation.     

An 8K EEPROM using the SIMOS storage cell

An 8192 bit MOS floating-gate EEPROM has been developed and transferred to volume production. The memory uses a two-transistor SIMOS cell for nonvolatile storage of alterable data. The cell is programmed by channel injection of hot electrons while electrical erasure is achieved by tunneling of cold electrons through a thin oxide. Standard production parts show a minimum endurance of 10/SUP 3/ program-erase cycles. The extrapolated data retention is at least 10 years of operation in a 70/spl deg/C ambient, while the number of read cycles is unlimited. Cell design features provide reliable programming combined with minimum sensitivity to fabrication tolerances. Special circuit design, however, ensures programmability of deeply erased cells and avoids electrical stress to the cell unintentionally affecting the programmed information. A novel read amplifier design allowed the realization of an access time of less than 350 ns.     

A process-tolerant cache architecture for improved yield in nanoscale technologies

Process parameter variations are expected to be significantly high in a sub-50-nm technology regime, which can severely affect the yield, unless very conservative design techniques are employed. The parameter variations are random in nature and are expected to be more pronounced in minimum geometry transistors commonly used in memories such as SRAM. Consequently, a large number of cells in a memory are expected to be faulty due to variations in different process parameters. We analyze the impact of process variation on the different failure mechanisms in SRAM cells. We also propose a process-tolerant cache architecture suitable for high-performance memory. This technique dynamically detects and replaces faulty cells by dynamically resizing the cache. It surpasses all the contemporary fault tolerant schemes such as row/column redundancy and error-correcting code (ECC) in handling failures due to process variation. Experimental results on a 64-K direct map L1 cache show that the proposed technique can achieve 94% yield compared to its original 33% yield (standard cache) in a 45-nm predictive technology under /spl sigma//sub Vt-inter/=/spl sigma//sub Vt-intra/=30 mV.     

64K DSA ROM

A 64K (8K/spl times/8) fully-static ROM has been developed using DSA E/D MOS technology. The ROM bit pattern is programmed on the diffusion mask. A new address decoder circuit has been designed and implemented in the device. ROM cell size is 11.5/spl times/15 /spl mu/m, and chip size is 5.05/spl times/5.05 mm.     

EEPROM28C64和28C256的14MeV中子辐照特性

给出了ＥＥＰＲＯＭ器件的中子辐照实验结果，发现２８Ｃ６４和２８Ｃ２５６的１４ＭｅＶ中子辐效应不是以往所认为的单粒子效应，而是总剂量效应器件出现的错误不是随机的，而是存在中子注量阈值；不同的错误有不同的阈值。在相同的中子注量下，加电的器件出现错误，而不加电的器件无错误；对于２８Ｃ２５６，“０”→“１”错误比“１”→“０”错误容易发生；存贮单元由一种状态彻底变为相反状态之前的一段时间内，其状态是不确定     

An 80 ns 32K EEPROM using the FETMOS cell

A 32K bit EEPROM using the FETMOS (floating-gate electron tunneling MOS) cell has achieved a typical access time of 80 ns and a die size of 20.6 mm/SUP 2/ using approximately 3 /spl mu/m feature sizes. The device has many built-in ease of use and ease of test features, including multimode erase (word, page, and bulk), bulk `O' program, latched inputs for program and erase operation, nonlocked high voltage supply, and margin test capability for both programmed and erased states. A unique TPP (transparent-partial programming) yield enhancement technique, using polysilicon fuse programming, can convert partially good 32K dice into totally good 16K and 8K devices.     

EEPROM可靠性初探

本文从EEPROM的简单的理论入手，引入了EEPROM器件的可靠性的概念。从“点”：隧道氧化层的评估（QBD实验）──“线”（擦／写实验）──“面”（加速保持特性实验）全面综合评估了EEPROM的可靠性。从中得到要保证EEPROM的可靠性的关键是要尽量减少隧道氧化层中的可动电荷和缺陷密度，如此才能保证它的“擦／写”质量，改善它的保持和耐久特性。     

A true single-transistor oxide-nitride-oxide EEPROM device

A novel single-transistor EEPROM device using single-polysilicon technology is described. This memory is programmed by channel hot-electron injection and the charges are stored in the oxide-nitride-oxide (ONO) gate dielectric. Erasing is accomplished in milliseconds by applying a positive voltage to the drain plus an optional negative voltage to the gate causing electron tunneling and/or hot-hole injection due to the deep-depletion-mode drain breakdown. Since the injection and storage of electrons and holes are confined to a short region near the drain, the part of the channel near the source maintains the original positive threshold voltage even after repeated erase operation. Therefore a select transistor, separate or integral, is not needed. Because oxide layers with a thickness larger than 60 Å are used, this device has much better data retention characteristics than conventional MNOS memory cells. This device has been successfully tested for WRITE/ERASE endurance to 10000 cycles.     

A 64K DRAM with 35 ns static column operation

A 64K dynamic RAM with a function mode similar to static memory operation is described. The device has multiplexed address inputs and a one-address strobe clock (RAS). After a row address is applied to the device, column selection is performed as in static memory, resulting in fast cycle time and simplicity of use. Column address access time and cycle times of 35 ns are achieved. The device has some other functions to reduce critical timings. Address transition detector circuits are used for column selection. An improved column decoder is provided to allow column address input skew. The device uses NMOS single transistor memory cells and is packaged in a standard 300-mil 16-pin DIP.