MPEG-4 Video and Image Coding on Digital Signal Processors

The emerging MPEG-4 standard encompasses a wide variety of applications, many of which are suitable for implementation on a Digital Signal Processor (DSP). In particular, consumer products with embedded multimedia capability, such as set-top boxes and wireless communicators, are suitable for DSP-based implementation. With a programmable approach, various algorithmic tradeoffs can be made, based on processing capability. For best performance, careful attention must be paid to memory allocation, data transfer, and ordering of instructions to best match the DSP architecture. We discuss implementing simple profile MPEG-4 video on the low-power TMS320C54x, core profile on the TMS320C6x, and scalable texture profile, which could be implemented on either processor family.     

Hardware/Software Co-reconfigurable Instruction Decoder for Adaptive Multi-core DSP Architectures

A programmable instruction decoder (PID) is introduced for designing adaptive multi-core DSP architectures by using a hardware/software co-reconfigurable approach without employing programmable devices. This PID permits DSP software developers for post-manufacturing modification of their DSP instruction sets to add their application-specific instructions whenever necessary. In addition, PID offers software developers an enhanced means to utilize the underlying DSP architectures by rescheduling implemented micro-operations for their tailored instructions in the DSP processors. Thus, emerging DSP applications can be swiftly and efficiently re-imported to PID-based DSP processors without re-fabrication of new DSP chips. In addition to instruction-level modification, an innovative instruction-packing procedure for PID is presented for further enhancement of the PID-based DSP systems. PID architecture was developed and implemented in VHDL. The PID-based DSP systems were also developed and evaluated to demonstrate various post-manufacturing adaptabilities in DSP processor systems. Various multi-core DSP architectures based on Texas Instruments’ TMS320C55 DSP processor were used for evaluating performance and adaptability of this new programmable instruction decoder.     

High VelociTI processing [Texas Instruments VLIW DSP architecture]

The Texas Instruments VelociTI architecture is a very long instruction word (VLIW) architecture. The TMS320C6x family of digital signal processors (DSPs) is the first to employ the VelociTI architecture, with the TMS3206201 (C6201) being the first device in this family. The C6201 is based on the fixed-point TMS320C62x (C62x) CPU. This article describes the VelociTI VLIW architecture and discusses the C62x, C67x, C6201, and the VelociTI development tools. An overview of the VelociTI including architectural principles, data path, instruction set, and pipeline operation is presented, and both the C62x fixed-point CPU and the C67x floating-point CPU are described. A summary of the C62x benchmark performance is also presented. The chip-level support outside the CPU that allows the C6201 to operate in a variety of high-performance DSP environments is also described. An overview of the C6x development environment is also given, demonstrating the breadth of the development environment and illustrating the programming methodology. The article concludes with a performance analysis of the C compiler     

基于TMS320VC55x DSP在线升级的设计与实现

提出了一种用串口实现DSP在线升级的方案,介绍了在线升级系统的结构组成和原理,并给出了一种基于TI公司TMS320VC55x处理器的DSP终端具体实现方法。根据TMS320VC55x处理器的特点,提出了二次引导机制实现灵活引导。在终端软件设计上,提出了层次化的结构使开发与维护更加清晰,描述了在线升级的软件实现流程。该系统已成功运用于DSP的数据采集系统,并且此方法可推广到其他嵌入式处理器系统。     

新一代节能高效数字信号处理器 TMS320C55x 及其应用

美国德州仪器公司的TMS320C55x是新一代数字信号处理器，具有低功耗、高性能和向下一代码兼容等特点，因此介绍了它的主要特性和主要应用。     

μCLinux操作系统的移植及Bootloader程序设计

ARM7TDMI是一种高效,低功耗的RISC处理器。以该内核及一个可编程数字信号处理器（DSP）为核心的TMS320VC5471是一款支持许多外围设备的双核设备。嵌入式μCLinux由于代码开放性以及强大的网络功能,在中低端的嵌入式网络设备中有广泛应用。和其他的嵌入式操作系统相比,具有更多的优势。就此以DSP＋ARM结构的嵌入式处理器TMS320VC5471评估板（EVM）作为目标板,搭建了基于GDB的嵌入式操作系统集成开发调试环境并实现了μCLinux操作系统的移植。     

基于波束形成算法的声源定位与DSP实现

声源定位在军事、工业噪声定位等领域具有广泛应用,基于麦克风阵列信号的波束形成是声源定位的主要方法。与传统波束形成算法相比,最小方差无失真响应(MVDR)算法具有较大优势,但MVDR算法运算量大,一般处理器无法满足实时性要求。针对波束形成算法的数据量大,运算复杂的特点,选取TI公司推出的TMS320DM642定点DSP芯片,采用C和汇编语言混合编程,实现了8个麦克风组成的均匀圆阵基于MVDR算法在TMS320DM642 DSP 的应用,其处理速度比在ARM上快,具有速度快,精度高,实用性强的特点。     

Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores

The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open research compiler infrastructure to a novel VLIW DSP (known as the PAC DSP core) and the specific design of code generation for its register file architecture. The PAC DSP utilizes port-restricted, distributed, and partitioned register file structures in addition to a heterogeneous clustered data-path architecture to attain low power consumption and a smaller die. As part of an effort to overcome the new challenges of code generation for the PAC DSP, we have developed a new register allocation scheme and other retargeting optimization phases that allow the effective generation of high quality code. Our preliminary experimental results indicate that our developed compiler can efficiently utilize the features of the specific register file architectures in the PAC DSP. Our experiences in designing compiler support for the PAC VLIW DSP with irregular resource constraints may also be of interest to those involved in developing compilers for similar architectures.

DSP环境下C代码的手工汇编优化

由于DSP器件的特殊结构,使得该平台上C编译器的效率较低,编译生成的汇编代码含有大量冗余,无法充分发挥DSP强大的运算能力,因而对C语言程序进行手工汇编优化就成为DSP软件开发和移植中常用的方法。TMS320C5410是TI推出的一款16位定点DSP芯片,结合在该芯片上优化实现G.729语音编码压缩算法的经验,详细探讨了手工汇编优化过程中使用的优化策略以及其他注意事项。     

Paged Absolute Addressing Mode Optimizations for Embedded Digital Signal Processors Using Post-pass Data-flow Analysis

We address the problem of code generation for embedded DSP systems. In such systems, it is typical for one or more digital signal processors (DSPs), program memory, and custom circuitry to be integrated onto a single IC. Consequently, the amount of silicon area that is dedicated to program memory is limited, so the embedded software must be sufficiently dense. Additionally, this software must be written so as to meet various high-performance constraints, which may include hard real-time constraints. Unfortunately, existing compiler technology is unable to generate dense, high-performance code for DSPs since it does not provide adequate support for the specialized architectural features of DSPs. These specialized features not only allow for the fast execution of common DSP operations, but they also allow for the generation of dense assembly code that specifies these operations. Thus, system designers often hand-program the embedded software in assembly, which is a very time-consuming task. In this paper, we focus on providing compiler support for one particular specialized architectural feature, namely the paged absolute addressing mode – this feature is found in two commercial DSPs, the Texas Instruments' TMS320C25 and TMS320C50 fixed-point DSPs; however, it may also be featured in application-specific processors (ASIPs). We present some machine-dependent code optimizations that improve code density by exploiting this architectural feature. Experimental results demonstrate that for a set of typical DSP benchmarks, some of our optimizations reduce overall code size and data memory consumption by an average of 5.0% and 16.0%, respectively. Our experimental vehicle throughout this research is the TMS320C25.     

TMS320C55x性能及DMA的使用

TMS320C55x是德州仪器公司的新一代高性能低功耗定点数字信号处理器。以TMS320C5509为例介绍了TMS320C55x系列的特点和性能指标,并重点介绍了DMA技术在C5509中的使用,最后给出DMA的编程实例。该实例中控制寄存器的定义和引用可用于对其他片内外设的编程。     

TMS320VC55x系列DSP在线烧写方法研究

TMS320VC55x系列DSP是TI公司在TMS320C54x基础上推出的新一代低功耗DSP。由于该系列DSP没有片内Flash,所以程序的加载方法是必须解决的问题。阐述了TMS320VC55x系列DSP的片外Flash在线编程方法,给出了系统的硬件连接方法和烧写程序,并研究了自举引导的实现方法。     

PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing

PLX is a concise instruction set architecture (ISA) that combines the most useful features from previous generations of multimedia instruction sets with newer ISA features for high-performance, low-cost multimedia information processing. Unlike previous multimedia instruction sets, PLX is not added onto a base processor ISA, but designed from the beginning as a standalone processor architecture optimized for media processing. Its design goals are high performance multimedia processing, general-purpose programmability to support an ever-growing range of applications, simplicity for constrained environments where low power and low cost are paramount, and scalability for higher performance in less constrained multimedia systems. Another design goal of PLX is to facilitate exploration and evaluation of novel techniques in instruction set architecture, microarchitecture, arithmetic, VLSI implementations, compiler optimizations, and parallel algorithm design for new computing paradigms.Key characteristics of PLX are a fully subword-parallel architecture with novel features like wordsize scalability from 32-bit to 128-bit words, a new definition of predication, and an innovative set of subword permutation instructions. We demonstrate the use and high performance of PLX on some frequently-used code kernels selected from image, video, and graphics processing applications: discrete cosine transform, pixel padding, clip test, and median filter. Our results show that a 64-bit PLX processor achieves significant speedups over a basic 64-bit RISC processor and over IA-32 processors with MMX and SSE multimedia extensions. Using PLXs wordsize scalability feature, PLX-128 often provides an additional 2× speedup over PLX-64 in a cost-effective way. Superscalar or VLIW (Very Long Instruction Word) PLX implementations can also add additional performance through inter-instruction, rather than intra-instruction parallelism. We also describe the PLX testbed and its software tools for architecture and related research.Ruby B. Lee is the Forrest G. Hamrick Professor of Engineering and Professor of Electrical Engineering at Princeton University, with an affiliated appointment in the Computer Science department. She is the founder and director of the Princeton Architecture Laboratory for Multimedia and Security (PALMS). Her current research is in rethinking computer architecture for high-performance but low-cost security and multimedia processing. Prior to joining the Princeton faculty in 1998, Dr. Lee served as chief architect at Hewlett-Packard, responsible at different times for processor architecture, multimedia architecture, and security architecture for e-commerce and extended enterprises. She was a key architect in the initial definition and the evolution of the PA-RISC processor architecture used in HP servers and workstations. As chief architect for HPs multimedia architecture team, Dr. Lee led an inter-disciplinary team focused on architecture to facilitate pervasive multimedia information processing using general-purpose computers. She introduced innovative multimedia instruction set architecture (MAX and MAX-2) in microprocessors, resulting in the industrys first real-time, high-fidelity MPEG video and audio player implemented in software on low-end desktop computers. Dr. Lee also co-led an HP-Intel multimedia architecture team for IA-64, released in Intels Itanium microprocessors. Concurrent with full-time employment at HP, Dr. Lee also served as Consulting Professor of Electrical Engineering at Stanford University. Dr. Lee has a Ph.D. in Electrical Engineering and a M.S. in Computer Science, both from Stanford University, and an A.B. from Cornell University, where she was a College Scholar. She is a Fellow of ACM, a Fellow of IEEE, and a member of IS&T, Phi Beta Kappa, and Alpha Lambda Delta. She has been granted 115 U.S. and international patents, with several patent applications pending.A. Murat Fiskiran is a Ph. D. student at the Department of Electrical Engineering at Princeton University. He is a member of the Princeton Architecture Laboratory for Multimedia and Security (PALMS) and a Kodak Fellow. His research interests include computer architecture and computer security.     

定点DSP在数字语音通信中的应用

本文介绍了新一代定点DSP芯片——TMS320C54x的体系结构和特点,及应用单片C548实现高质量、低延时的G.729协议的语音编码算法,并分析了定点DSP在实时实现数字语音通信中的一些关键技术。     

具有超级计算机功能的CMOS DSP芯片

本文介绍了美国德克萨斯州仪器公司的TMS320C30数字信号处理器组织结构,指令系统和典型应用.TMS320C30数字信号处理器能实现快速浮点数学运算,并提供了大的在片RAM和ROM空间、高速指令缓冲器、DMA控制器、多地址发生器和支持高级语言编程.高度的并行操作和能达到33MFLOPS的处理速度,为DSP展示了广泛的应用前景.     

基于数字信号处理器DSP的SPM研究

本文以TI公司的TMS320C54xDSP为核心，介绍了DSP-SPM全数字化系统。文章首先指出目前国产扫描探针显微镜存在智能化及集成度不高、PID参数调节不方便、成本高等不足。进而引入数字信号处理器(Digital Signal Processor DSP)，介绍了TMS320C54x DSP的特点及其开发工具；然后给出了DSP-SPM系统的框图及DSP算法；文章最后还简单介绍了利用’54X的HPI(Host Port Interface)与PC机并口通讯的情况。     

基于TMS320F2808DSP最小系统设计及应用

通过介绍了新一代美国德州仪器（TI）公司C2000平台上的定点DSP芯片TMS320F2808的性能特点和硬件结构、外设模块,给出了由TMS320F2808组成的DSP最小应用系统,并介绍了各部分电路的设计方案。     

实时图像跟踪系统中TMS320C6x DSP的软件优化

TMS320C6x系列DSP器件采用了VelociTI TM体系结构的内核,集成了DMA控制器等多种功能强大的外设,并具有以blocks和banks划分的内部数据存储器.要充分发挥硬件潜力,提高系统性能,就必须采取一系列措施来优化DSP软件,实现指令的高度并行和流畅的流水线操作.文章介绍了TMS320C6x C语言优化方面的一些有效的方法,包括硬件特点考虑,指令存储器相关性消除,以及代码结构改善等.并给出了实时图像跟踪系统中的应用和结果.     

H.263视频编码算法原理及DSP实现

介绍ITU-T H.263视频编码器在德州仪器（Texas Instruments)公司新一代数字信号处理芯片IMS320C6000上的实时实现技术。编程实现了H.263标准的主要内容及H.263 中提出的新的编码技术，重点讨论了H.263编码在TMS320C6711 DSP上的优化和实现。