Power Trench MOSFETs with very low specific on-resistance for 25V applications

In this paper, an investigation of the benefits of deep ultra violet lithography for the manufacturing of Trench MOSFETs and its impact on device performance is presented. We discuss experimental results for devices with a pitch size down to 0.6 μm fabricated with an unconventional implant topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are benchmarked against previously published TrenchMOS technologies by de-embedding the parasitic substrate resistance, revealing a record-low specific on-resistance of 5.3 mΩ mm² at a breakdown voltage of 30 V (V_gs = 10 V).     

Progressive breakdown in ultrathin SiON dielectrics and its effect on transistor performance

The post-breakdown conduction properties of ultrathin SiON layers were investigated, to determine the impact of various parameters on the growth of a breakdown path after its formation. Post-breakdown conduction is seen to be dependent on stress voltage used to break the oxide, the stress temperature, and the time-to-breakdown. With this knowledge, the performance of transistors of various channel lengths and widths was studied both before and after breakdown occurred to determine whether the devices still function as a digital switches after breakdown. That is, the drain to source current (I_ds) in the on–state (V_g V_th) is much larger than I_ds in the off–state (V_g < V_th), allowing the device to continue to function as a switch, after breakdown occurs.     

Temperature dependence of snap-back breakdown up to 300°C analyzed using circuit level model and simulation

The MOS snap-back breakdown and its temperature dependence were investigated up to 300°C using silicided LDD-NMOS transistors. The snap-back sustaining voltage increases from 8.25V at room temperature to 8.9V at 300°C (for L_eff=0.56μm). By using extracted parameters for a simple lumped element model we explain this behaviour originating from an increasing avalanche breakdown voltage and slope of avalanche multiplication factor compensating the increase in bipolar gain with temperature.     

Evaluation of SiGe:C HBT intrinsic reliability using conventional and step stress methodologies

The reliability of SiGe:C HBT devices fabricated using the Freescale’s 0.35-μm RF-BICMOS process was evaluated using both conventional and step stress methodologies. This device technology was assessed to determine its capability for various power amplifier applications (e.g., WLAN, Bluetooth, and cellular phone), which are more demanding than conventional circuit designs. The step stress method was developed to allow a rapid evaluation of product reliability, as well as, a quick method to monitor product reliability. For all tests the collector current I_C and collector voltage V_C were kept constant throughout the test, and the current gain β (I_C/I_B) was continuously monitored. The nominal bias condition was V_C = 3.5-V and J_C = 50-kA/cm² (or 0.5-mA/μm²). The “failure criterion” for all reliability evaluations was −10% degradation in β from the initial value at the start of each stress test or interval. The median time to failure (MTTF) at a junction temperature (T_JCN) of 150 °C for the conventional stress test was 1.86E6-h, and the thermal activation energy was 1.33-eV. In contrast for the temperature step stress tests the combined results gave an MTTF at T_JCN = 150 °C of 5.2E6-h and a thermal activation energy of 1.44-eV. Considering the differences in the two test methods, these results are quite close to one another. The intrinsic reliability of this device at the nominal bias condition and T_JCN = 150 °C is more than adequate for a 5-year system life.     

Degradation of n-channel a-Si:H/nc-Si:H bilayer thin-film transistors under DC electrical stress

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated, using as channel material hydrogenated amorphous silicon (a-Si:H)/nanocrystalline silicon (nc-Si:H) bilayers, deposited at 230 °C by plasma-enhanced chemical vapor deposition, and SiN_x as gate dielectric. The stability of these devices is investigated under three bias stress conditions: (i) gate bias stress (V_G = 25 V, V_D = 0), (ii) on-state bias stress (V_G = 25 V, V_D = 20 V) and (iii) off-state bias stress (V_G = −25 V, V_D = 20 V). It is found that the TFT degradation mechanisms are strongly dependent on the bias stress conditions, involving generation of deep and tail states in the active area of the channel material, carrier injection (electrons or holes) within the gate insulator and generation of donor trap states at the gate insulator/channel interface. The common features and the differences observed in the degradation behaviour under the different bias stress conditions are discussed.     

High breakdown voltage Schottky rectifier fabricated on bulk n-GaN substrate

Vertical Schottky rectifiers have been fabricated on a free-standing n-GaN substrate. Circular Pt Schottky contacts with different diameters (50 μm, 150 μm and 300 μm) were prepared on the Ga-face and full backside ohmic contact was prepared on the N-face by using Ti/Al. The electron concentration of the substrate was as low as 7 × 10¹⁵ cm⁻³. Without epitaxial layer and edge termination scheme, the reverse breakdown voltages (V_B) as high as 630 V and 600 V were achieved for 50 μm and 150 μm diameter rectifiers, respectively. For larger diameter (300 μm) rectifiers, V_B dropped to 260 V. The forward turn-on voltage (V_F) for the 50 μm diameter rectifiers was 1.2 V at the current density of 100 A/cm², and the on-state resistance (R_on) was 2.2 mΩ cm², producing a figure-of-merit (V_B)²/R_on of 180 MW cm⁻². At 10 V bias, forward currents of 0.5 A and 0.8 A were obtained for 150 μm and 300 μm diameter rectifiers, respectively. The devices exhibited an ultrafast reverse recovery characteristics, with the reverse recovery time shorter than 20 ns.     

A novel low temperature integration of hybrid CMOS devices on flexible substrates

In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180 °C and 120 °C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm²/V s, respectively. Threshold voltages (V_t) are 1.14 V for nMOS and −1.89 V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress.     

Flexible complementary inverter with low-temperature processable polymeric gate dielectric on a plastic substrate

We report low-temperature processability of poly(4-vinylphenol) based gate dielectric by investigating the effect of composition and processing temperature on the thermal, mechanical and electrical characteristics of the gate dielectric. We found that the processing temperature of the gate dielectric could be reduced up to 70 °C by optimizing the composition of the gate dielectric solution. Based on this finding, we have fabricated a flexible organic complementary inverter by integrating n- and p-type organic thin-film transistors (OTFTs) with the low-temperature processable gate dielectric on a plastic substrate. Pentacene and F16CuPc were used as p-type and n-type semiconductor, respectively. The inverter shows that the swing range of V_out is same as V_DD, which ensures “zero” static power consumption in digital circuits. The logic threshold of the inverter with G5 gate dielectric cured at 70 °C is 21.0 V and the maximum voltage gain (∂V_out/∂V_in) of 8.1 is obtained at V_in = 21.0 V. In addition, we have discussed in more detail the characteristics of the OTFTs and the complementary inverter with respect to the process condition of the gate dielectric.     

High threshold voltage matching performance on gate-all-around MOSFET

For the first time, threshold voltage matching was measured on multiple gate transistors, and particularly on Gate-All-Around transistors (GAA) with both doped and undoped channels. Good matching performance is demonstrated on doped channel transistors, thanks to the absence of pocket nor halo implants. But most of all, it is shown that suppressing the channel doping allows to drastically reduce the dopant induced fluctuations contribution and provides an A_Vt parameter as low as 1.4 mV μm, which is one of the best reported result on MOS transistors.     

Ka-band InP high electron mobility transistor monolithic microwave integrated circuit reliability

The reliability of AlInAs/GaInAs high electron mobility transistor (HEMT) monolithic microwave integrated circuits on InP substrates from HRL Labs has been studied with elevated-temperature lifetests on Ka-band LNAs, as well as ramped-voltage tests on individual capacitors. In the lifetests the LNAs were put under normal DC bias, and aging was accelerated by heating to channel temperatures of 190°C and 210°C. Room-temperature characterizations involved DC tests of HEMT parameters as well as 30 GHz measurements of gain, noise figure and phase. Aging caused the noise figure to drop by a few tenths of a dB, and the phase changed by ±10°. The gain dropped gradually by several dB. Taking 1 dB drop in gain as the failure criterion, we find an activation energy of 1.1 eV, and a mean time to failure (MTTF) at an operating channel temperature of 70°C of 7×10⁶ h. In the ramped-voltage tests, 10×10 μm² capacitors were taken to breakdown at two different temperatures, and several ramp rates. This yielded a voltage acceleration factor of γ=36–39 nm/V, and thermal activation energy of 0.11–0.13 eV. Next, ramped voltage tests were conducted on 200×200 μm² capacitors, typical of those in circuits. These were done at 25°C and 3.0 V/s only, and at least 1000 specimens were tested per wafer. The known acceleration factors were used to find the MTTFs at 70°C, with operating biases of 5 or 10 V. For the majority of the population the MTTFs are about 10⁹ h, while only 0.07% of the population has MTTF less than 1×10⁶ h. The combination of results from elevated-temperature lifetests and ramped-voltage capacitor tests indicates excellent reliability for this MMIC technology in terms of known “wearout” failure mechanisms.     

Reliability of 100 nm silicon nitride capacitors in an InP HEMT MMIC process

A reliability study has been conducted on capacitors made with 100 nm of silicon nitride, in an InP HEMT MMIC fabrication process. Special wafers were fabricated, containing 1482 200 × 200 μm² capacitors each, and these were probed automatically. They were subject to ramped-voltage stress and the breakdown voltages recorded. On a typical wafer the vast majority of the breakdown voltages are between 50 and 90 V. In addition, IV curves were measured on a small number of specimens from 0 V up to breakdown. This was done in two regimes: above 25 V with a conventional setup, and below 25 V with an ultra-low-current measurement system. These were done at 25 and 175 °C above 25 V, and at 25 °C only below 25 V. The data were fitted well with a model for the conductivity, consisting of ohmic conduction at low voltages and Frenkel–Poole conduction at high voltages. Parameters of the fits included thermal activation energies, the voltage acceleration factor in the Frenkel–Poole model, and d_eff, the effective thickness of the dielectric at the thinnest point. Analysis invoked the time-dependent dielectric breakdown model, which provides the time to failure as a function of the d_eff, while d_eff can be found from the ramped-voltage measurements. From the 10 wafers that have been probed so far, the mean of the distribution of failure times (at 1.5 V, 40 °C) is above 5 × 10⁷ h, and the distribution becomes insignificant below 2 × 10⁶ h. Further, the probability of failure in 10 years at 1.5 V, 40 °C is much less than 1 in 14,600. This indicates that 100 nm silicon nitride capacitors in this technology have good reliability.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

Organic thin film transistors with HfO2 high-k gate dielectric grown by anodic oxidation or deposited by sol–gel

We report here on pentacene based organic field effect transistors (OFETs) with a high-k HfO₂ gate oxide. HfO₂ layers were prepared by two different methods: anodic oxidation and sol–gel. A comparison of the two processes on the electrical properties of OFETs is given. Ultra thin nanoporous (20 nm) sol–gel deposited oxide films were obtained following an annealing at 450 °C. They lead to high mobility and stable devices (μ = 0.12 cm²/V s). On the other hand, devices with anodic HfO₂ revealed a little bit more leaky and show some hysteresis. Anodization, however, presents the advantage of being a fully room temperature process, compatible with plastic substrates. Stability and response to a bias stress are also reported.     

A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe-source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved compared with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe-S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451 μA/μm at V_dd of 0.9 V and I_off of 100 nA/μm (552 μA/μm at V_dd of 1.0 V). Furthermore, by combining with V_dd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation.     

A high-linear wide-tunable CMOS transconductor for video frequency applications

In this paper a new CMOS transconductor structure based on a g_m-boosted degenerated differential pair is presented for applications in the video frequency range. The proposed circuit combines two techniques, a switchable array of source degenerating MOS resistors and a programmable output current mirror, in order to widen the G_m tuning range while maintaining linearity. Degeneration MOS resistors are made common-mode voltage independent thanks to a simple control circuit. Post-layout simulation results from a 0.35 μm design supplied at 3.3 V show a wide tuning range (10–100 MHz), good linearity (−58.4 dB for an output signal voltage of 1.1 V_p–p) and low excess phase (<0.5° over the whole tuning range).     

Low power, GHz class ADC for broadband applications

The design of ultra-low power (<100 mW), high-speed analogue to digital converter (ADC) is an essential element for the next generation radio telescope, the square kilometre array (SKA). CMOS technology is limited in high precision applications, such as ADCs due to the stringent requirement of device matching. Also to achieve high-speed (f_t>100 GHz) CMOS requires deep sub-micron gates (90 nm or less) where expensive phase shift masks are required. This paper describes the design and simulation of a low-power high-speed (4 GS/s) analogue to digital converter based on an InP/InGaAs heterojunction bipolar transistor (HBT). The technology used was developed at the University of Manchester using MBE growth which relied upon two novel developments. Firstly stoichiometric conditions permitted growth at a fairly low temperature of 420 °C while conserving extremely high-quality materials. Secondly dimeric phosphorus was generated from a gallium phosphide (GaP) decomposition source leading to excellent RF device properties. The DC and RF performance of the fabricated HBTs showed characteristics ideally suited to low-power IC designs, with current gain 70, low offset voltages and achieving an f_t=91 GHz and f_max=83 GHz on a 1.5×5 μm² emitter area device using fairly relaxed optical lithography.     

Electrical reliability of highly reliable 256M-bit mobile DRAM with top-edge round STI and dual gate oxide

A novel CMOS fabrication process with a dual gate oxide (NDGO, thin oxide 5.0 nm, thick oxide 7.8 nm) and a shallow trench isolation (STI) top-edge rounded by a pad oxide undercut was developed for a 256M-bit mobile dynamic random access memory (DRAM) with V_D=1.8 V. We present a comprehensive study on the I–V characteristics and the long-term reliability of CMOSFET fabricated by NDGO process, and compared these characteristics with those of conventional single gate oxide transistors with a gate oxide thickness 5.0–7.5 nm. While thin oxide nMOSFET have a threshold voltage of nMOSFET (V_thn) of between 0.70 and 0.72 V and a saturation current (I_DSAT) of between 280 and 300 μA/μm, thick oxide nMOSFET have a V_thn of between 0.85 and 0.90 V and an I_DSAT of between 160 and 200 μA/μm in NDGO process due to a difference in the gate oxide thickness at similar boron doses. A 10 year lifetime of thick oxide cell transistors is projected for a V_g=8.9 V due to an electrical stress release at the STI top-edge round improved by the pad oxide undercut. The hot carrier lifetime and hot electron induced punchthrough also showed good characteristics. Consequently, this NDGO process is able to provide a reliable transistor performance for a 256M-bit mobile DRAM operating at low power.     

Comparative studies of Pt and Ir schottky contacts on undoped Al0.36Ga0.64N

Schottky contacts of Pt and Ir on undoped Al_0.36Ga_0.64N have been fabricated and the ideality factor, the built-in voltage and the reverse bias current were determined using current–voltage measurements to make a comparison.The smallest ideality factors, the lowest reverse bias current and the highest built-in voltages have been obtained for Ir Schottky contacts.We have studied the effect of an annealing for Pt and Ir Schottky contacts, on the ideality factor, the built-in voltage and the reverse bias current. A decrease of the ideality factor and the reverse bias current associated to an increase of the built-in voltage have been obtained except for high annealing temperature (T > 400 °C).Reductions of 37% and 43% of the ideality factor and improvements of 24% and 41% of the built-in voltage have been obtained for Pt and Ir Schottky contacts, respectively, after an annealing performed at 350 °C during 30 min.Two different electrical stresses have also been applied on the ohmic and Schottky contacts during 164 h to study the reliability of the employed technology. In a first time, the devices have been stressed with a drain-to-source voltage V_DS of 20 V and a gate-to-source voltage V_GS of −5 V to submit the devices to an electrical field only and not to a thermal effect induced by the electrical current. In a second time, the aging stress has been applied for a V_DS of 20 V and for a V_GS of 0 V in order to study the impact of the electrical field and the thermal effect induced by the drain current on the electrical behaviours of Al_0.36Ga_0.64N/GaN transistors. This study has also shown the existence of electrical traps in the device structure and proved the good reliability of the involved technology.These comparative studies demonstrate that Ir is a better candidate than Pt for the realisation of Schottky contacts on undoped Al_0.36Ga_0.64N.     

Impact of anomalous short-channel MOS transistors on VLSI circuit reliability

In VLSI and ULSI circuits, a major reliability concern is that completed, fully functional, in-specification integrated circuits may contain one or more anomalous transistors with substantially closer source-to-drain spacing than the minimum-design-rule devices, and that such transistors will be more susceptible to degradation or failure due to hot-carrier effects, total-dose-radiation effects or other instabilities. A further concern is that such vulnerable transistors will not be detected during conventional electrical testing or during typical high-reliability integrated circuit burn-in procedures such as static or dynamic burn-in at 125°C, since hot carrier effects tend to anneal out at elevated temperatures, as well as having a negative temperature acceleration factor.Experimental studies have shown that fully functional nMOS transistors with shorter-than-normal channel lengths can have many orders of magnitude greater susceptibility to hot-electron-induced threshold voltage shifts, compared to transistors with minimum-design-rule dimensions of 1.2μm. Total-dose radiation tests showed that anomalous n-channel MOS transistors can have orders-of magnitude higher post-total-dose radiation leakage than nominal devices made by the same process.Several possible types of screening techniques that can be considered for detecting integrated circuits containing anomalous transistors are discussed, including a low-dissipation dynamic stress test at room temperature or at −55°C, with parts electrically characterized before and after the stress test. A large change (delta) of certain critical parameters would be used to predict future failure. Quiescent CMOS supply-current testing could also be used to detect the presence of anomalous transistors in some types of integrated circuits.     

Numerical analysis of SOI LDMOS using a recessed source and a trench drain

A new SOI LDMOS using a recessed source and a trench drain was proposed to improve the on-characteristics at a given breakdown voltage. On-resistance and breakdown voltages of the proposed LDMOS are investigated by the two-dimensional simulator, MEDICI. The simulation results show that the on-resistance of the proposed and the conventional LDMOS are 76.3 and 129.5 mΩ mm², respectively. The on-resistance of the proposed LDMOS decreases by 41% compared to that of the conventional LDMOS at the same breakdown voltage of 36.5 V.