The Elmwood multiprocessor operating system

Elmwood is an object-oriented, multiprocessor operating system designed and implemented during a graduate seminar. It consists of a minimal kernel and a collection of user-implemented services. The kernel provides two major abstractions: objects, which consist of code and data, and processes, which represent asynchronous activity. Objects, like programs, are passive. To operate on an abstraction or to request a service, processes invoke an entry procedure defined by the corresponding object. Objects implement their own protection and synchronization policies using minimal kernel mechanisms. We describe the Elmwood kernel interface, an implementation on the BBN Butterfly parallel processor, and our experiences in developing a multiprocessor operating system under rigid time constraints. These experiences illustrate several general lessons regarding kernel design and trade-offs for implementation expedience.     

The EMMA2 multiprocessor operating system

The EMMA2

1 EMMA is a registered trademark of Elsag—Elettronica San Giorgio.

parallel architecture is a network of nodes, named 'Regions': each region is based on two shared-memory hierarchical bus levels, on which a large series of monocpu, multicpu and specialized I/O boards can be inserted, grouped in 'Families'. Its typical applications are Image processing, pattern recognition and artificial intelligence, characterized by intensive computation requirements, real-time constraints and good price-performance ratio for building large industrial systems. This paper presents the main characteristics of the EMMA2 parallel operating system, highlighting the internal organization and mechanisms offering the parallel co-operation model for user programs. Section 1 briefly introduces the overall hardware architecture. It allows application partitioning into parallel independent subsystems, on two levels of computation: the lower level (family) is dedicated to massive number crunching, while the upper (region) permits the interaction of these lower machines. Section 2 deals with the system software environment, based on a host-target configuration: the host is mainly devoted to machine control, system monitoring, program development and debugging in a multi-user environment. Sections 3, 4 and 5 describe respectively the fundamental concepts of the operating system internal organization and the basic mechanisms with respect to the machine architecture; the basic functions that constitute the internal layers and services; the resulting parallel programming and co-operation model and the typical mapping rules of algorithms to this architecture, completed with some examples of their functionalities. The most important aspect of the EMMA2 operating system is the fact that it offers a uniform interface to user tasks, independently of their allocation on the target machine. Objects managed by system services can be referred to via logical names. Code for system services is distributed among processors and resides on a private read-only memory. The operating system's data reside in shared memory only for system functions that need to be distributed, while private functions are based on different copies of data in private memories. Section 6 gives more details on the most relevant EMMA2 industrial applications, also showing their mapping to the parallel architecture and some performance-related information. Section 7 contains a brief outline of the novel architecture currently in development and of the subsequent OS Improvements. In conclusion, we report some considerations about the present status of the EMMA2 system, compared with some other well-known architectures, and about research efforts for its future evolution.     

多处理机并行计算自动测控系统

介绍了多处理机系统的并行计算,在此基础上,给出了采用十刻度策略解决任务排序,采用满射策略解决任务映射的算法。最后,给出了一个自动测控系统示例,该系统不仅可以使多台处理机同时进行多种不同仪器仪表、设备的测控工作,而且处理机间的通信成本较低,加快了被测对象的测试速度,节省了测试时间。     

Fault—Tolerance Analysis of Multibus Multiprocessor System

This paper proposes a new graph model for multibus multiprocessor system.Based on the link representation of cut set of the hypergraph,ring sum and its algebraic properties,we can directly calculate the degrees of bus-fault-tolerance and processor-fault-tolerance for any multibus multiprocessor system.Algorithms are listed and all the theorems and proofs are stated.     

Hardware monitoring of a multiprocessor system

The Testbed for Distributed Processing, or Ted, consists of Intel Corp.'s iSBC 8086 single board computers (SBCs) organized into groups or clusters. Each cluster consists of several SBCs that communicate via a shared memory. Intercluster communication occurs through an Ethernet interface. A hardware monitor designed and implemented to handle the monitoring activities within a cluster in the Ted system is described. By using specified patterns and don't-care masks, the system can detect accesses to selected data, addresses, or blocks of addresses. This function helps monitor events such as the access or usage of a memory location or a group of mailbox addresses. It also determines the amount of time consumed by the performance of specific operations     

The Stanford Dash multiprocessor

The overall goals and major features of the directory architecture for shared memory (Dash) are presented. The fundamental premise behind the architecture is that it is possible to build a scalable high-performance machine with a single address space and coherent caches. The Dash architecture is scalable in that it achieves linear or near-linear performance growth as the number of processors increases from a few to a few thousand. This performance results from distributing the memory among processing nodes and using a network with scalable bandwidth to connect the nodes. The architecture allows shared data to be cached, significantly reducing the latency of memory accesses and yielding higher processor utilization and higher overall performance. A distributed directory-based protocol that provides cache coherence without compromising scalability is discussed in detail. The Dash prototype machine and the corresponding software support are described     

Error Recovery in a Real-Time Multiprocessor System

In this paper,a new scheme for recovering errors due to transient faults in a real-time multiprocessor system is presented.The scheme,called dynamic redundancy at the task level,is implemented in a real-time multitasking environment,Utilizing the facilities in the operating system,the scheme makes backup tasks for the primary tasks as redundancy.The paper introdues an algorithm to generate a fault tolerant schedule for the tasks so that they recover errors as retry of checkpointing does.A reliability model is proposed to evahuste the effectiveness of the scheme.     

Token bus communications within a multiprocessor system

In multiprocessor systems, interprocessor communication is fundamental to overall performance in terms of throughput, modularity and fault tolerance. Generally, emphasis is placed on achieving high processing speeds (as measured in Whetstone and Dhrystone benchmarks) at the expense of other factors. Communication methods used to support high throughputs are often unacceptable when factors such as reliability and redundancy are paramount. This paper presents a multiprocessor communications architecture designed to achieve high performance, good modularity and expandability, good fault tolerance and the ability to support processor reconfiguration. The protocol is based on that of the token passing bus method, electrical signalling being carried out using a simple parallel bus structure. The design is processor independent.     

Performance evaluation of the IMPS multiprocessor system

The performance of the IMPS multiprocessor computer system is studied and investigated. An analytic queueing model is derived for one cluster of the architecture. These results were validated by developing a discrete-event simulation model written in SIMSCRIPT II.5 simulation language. The simulator uses real values for its input parameters, collected by using one processor module and a logic analyzer. The analytical performance results closely match the simulation model performance results. The primary performance index used in the modeling is the speedup. Other performance measures can easily be derived from the speedup.     

IP-PCA的多处理机系统设计

IC－PCA（protocol converter A)是一个协议转换器，主要实现中国七号信令和IP协议的转换。设计目标是把16条PCM（2M／S）的中国七号信令转换为1条（10／100 M／S）自适应IP信令协议的以支网接口，把电话交换设备通过IP－PCA连到IP网上去，使电用户能够通过IP网进行长途电话业务。     

多处理器系统的在线节能调度算法

随着多处理器系统计算性能的提高,能耗管理已变得越来越重要,如何满足实时约束并有效降低能耗成为实时调度中的一个重要问题。基于多处理器计算系统,针对随机到达的任务,提出一种在线节能调度算法(OLEAS)。该算法在满足任务截止期限的前提下,尽量将任务调度到产生能耗最少的处理器,当某个任务在所有处理器上都不能满足截止期限要求时,则调整处理器之间的部分任务,使之尽量满足截止期限要求。同时,OLEAS尽量使单个处理器上的任务按平均电压/频率执行,以降低能耗,只有当新到任务不满足截止期限要求时,才逐个调高前面任务的电压/频率。模拟实验比较了OLEAS、最早完成时间优先(EFF)、最高电压节能(HVEA)、最低电压节能(LVEA)、贪心最小能耗(MEG)和最小能耗最小完成时间(ME-MC)的性能,结果表明OLEAS在满足任务截止期限和节省能耗方面具有明显的综合优势     

A large-area integrated multiprocessor system for videoapplications

This 16.89 cm² multiprocessor system performs coding of high-resolution video streams in real time. Redundancy and self-reconfiguration techniques ensure high reliability with a suitable yield. We used our own built-in self-test approach, which allows parallel testing of the processor cores     

A Bitonic Selection Algorithm on Multiprocessor System

The so-called (m, n) selection problem is defined as the selection of them smallest (or largest) numbers fromn given numbers (n>m). Solving this problem in parallel mode has been successful on the networks, but it is seldom studied on the multiprocessor systems. This paper first, based on Batcher’s principle of bitonic merging, proposes the bitonic selection network. Then it repeals the varying rule of the pivots in all successive ranks of the network through our observation to the data transfer property in the network. Finally, according to this rule, the parallel selection algorithm with running timeO (lognlogm)¹⁾ onn processors is presented. This work was supported by the National Science Foundation of China under Grant Tech.-85217.     

An operating system for a fault-tolerant multiprocessor controller

The development of an operating system that is a central component of a fault-tolerant multiprocessor is described. The operating system, while relatively simple and small, supports multitasking and multiprocessing, as well as both self-diagnostics and cross-diagnostics for fault detection. In the event of a fault, the system permits rapid reconfiguration in a manner that retains processing for the highest-priority tasks. Since the hardware needed to provide fault tolerance is available when there are no faults, the operating system can utilize this excess capacity to accomplish lower-priority tasks during normal operation. This approach yields graceful degradation in response to faults in the system components     

基于软实时多处理器系统的动态低功耗算法

结合DVS技术和(m,k)-firm模型，提出一个保证完成率、适用于软实时多电压多处理器系统中有依赖关系任务集的动态低功耗算法VAP_DY。该算法权衡应用的性能需求、执行时间的不确定性和系统对合理执行失败的容忍来动态调整每个处理器运行时的供电电压,以降低多处理器系统的总功耗。分析和实验结果表明，VAP_DY能够在保证时间和完成率约束的条件下有效降低系统功耗。     

A parallel Ada system on an experimental multiprocessor

This paper describes the development of a parallel Ada system on an experimental MIMD multiprocessor. The system enables a single unmodified Ada program, with a number of tasks, to execute in parallel on different processors. Allocation and migration strategies are controlled by mechanisms in the run-time system, and are thus transparent to the Ada programmer. The parallel Ada system is based on a validated portable front-end compiler. Implementation issues related to the multiprocessor environment are pointed out, and solutions to these issues are suggested. The experimental multiprocessor environment, consisting of both hardware and software, is described. Applicable resource allocation strategies in, and feasible experiments with, the Ada system are discussed. The complete experimental system provides unique possibilities to experiment with, and monitor the effects of, design decisions at different levels in a multiprocessor environment.     

Construction of an inexpensive and flexible multiprocessor system

A multiprocessor system, based on the 6800 family of microprocessors, is described. It is designed for experimentation in hardware and software aspects of distributed processing. System organization, hardware and software are all given. Listings of test programs are provided.