Efficient switched-capacitor common-mode feedback circuit for high-speed low-power amplifiers

A new switched-capacitor (SC) common-mode feedback (CMFB) circuit for fully-differential operational amplifiers (op-amps) is presented. By reducing the amplifier capacitive load with respect to conventional SC-CMFB schemes, the proposed solution guarantees a significant improvement of the op-amp speed performance. A typical SC integrator employing the new CMFB has also been designed in 0.35 μm CMOS technology. Simulation results show that, for a given power consumption, the op-amp settling time can be about halved by using the proposed CMFB instead of the conventional one.     

GaAs switched-capacitor circuits for high-speed signal processing

Switched-capacitor building blocks are presented which are suitable for implementation in GaAs MESFET technology. They include gain stages, operational amplifiers, and transmission gates. Switched-capacitor design techniques are discussed that minimize filter sensitivity to GaAs op-amp limitations. Experimental results are presented on a variety of GaAs switched-capacitor circuits, including a gain stage, a second-order bandpass filter, and a third-order low-pass filter. The circuits demonstrate sampling rates exceeding 100 MHz without significant loss of accuracy.     

Dynamic biasing scheme for high-speed= low-power switched-capacitor stages

A scheme is proposed for adjusting the bias current of the op-amp in a switched-capacitor stage so that it follows the swing of the input signal, minimising the power consumption of the stage. Simulations indicate that a 60% power saving is possible using the method     

Multipath common-mode feedback scheme suitable for high-frequency two-stage amplifiers

A method for stabilising the common-mode feedback (CMFB) loop in high-speed fully differential two-stage amplifiers is presented. Existing approaches may prove to be inadequate for high-speed designs. The problem becomes acute because of positive DC feedback by external network, which leads to 'latching states'. The proposed multipath approach avoids the latching states while maintaining the stability of the CMFB loop.     

An improved common-mode feedback loop for the differential-difference amplifier

Unconditional stability of the high-gain amplifiers is a mandatory requirement for a reliable steady-state condition of time-discrete systems, especially for all blocks designed to sample-and-hold (S/H) circuits. Compared to differential path, the common-mode feedback loop is often affected by poles and zeros shifting that degrades the large signal response of the amplifiers. This drawback is made worse in some well-known topologies as the difference-differential amplifier (DDA) that shows non-constant transconductance and poor linearity. This work proposes a body-driven positive-feedback frequency compensation technique (BD-PFFC) to improve the linearity for precision DDA-based S/H applications. Theoretical calculations and circuit simulations carried out in a 0.13 μm process are also given to demonstrate its validity.     

Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper

Low-voltage high-speed switched-capacitor (SC) circuit design without using voltage bootstrapper is presented. The basic building block used for low-voltage SC circuit design is the auto-zeroed integrator (AZI), which can work at both low voltage and high sampling frequency. With this method, two low-voltage SC systems were successfully designed and implemented in 1.2-/spl mu/m CMOS technology. The first one is a fully differential SC bandpass biquad working at 1.5 V and 5.0-MHz clock frequency. The measured Q value is 8.0 at the center frequency of 833 kHz. The second one is a fully differential fourth-order bandpass /spl Delta//spl Sigma/ modulator that also works at 1.5 V and 5.0 MHz. Its measured third-order intermodulation is less than -78 dBc due to the low distortion characteristic of AZI. The measured signal-to-noise ratio of the modulator is 61 dB within the narrow band of 25 kHz centered at 1.25 MHz.     

A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector

A pseudo-differential fully balanced fully symmetric CMOS operational transconductance amplifier (OTA) architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. The OTA achieves a third harmonic distortion of -43 dB for 900 mV/sub pp/ at 30 MHz. The OTA, fabricated in 0.5-/spl mu/m CMOS process, is used to design a 100-MHz fourth-order linear phase filter. The measured filter's group delay ripple is 3% for frequencies up to 100 MHz, and the measured dynamic range is 45 dB for a total harmonic distortion of -46 dB. The filter consumes 42.9 mW per complex pole pair while operating from a /spl plusmn/1.65-V power supply.     

Differential log-domain filters with high-gain common-mode feedback

A new class of differential log-domain filters based on common-mode feedback (CMFB) is demonstrated. Conditions for adding CMFB to differential log-domain integrators while preserving external linearity are derived. Because signals within differential log-domain circuits are nonlinear, the definition of "common-mode" in these circuits is not unique. Three possible definitions are explored, and each is illustrated with a simple but practical circuit. The circuits provide large CMFB loop gain, which forces common-mode signals to follow a desired nonlinear function. This allows closed-form expressions for the nonlinear internal signals to be derived, which is highly advantageous for design. Second-order filters using CMFB were compared to filters without CMFB through simulation and through measurements of fabricated filters. Adding CMFB is shown to allow greatly increased undistorted signal swings.     

Synthesis of single-amplifier switched-capacitor networks

A new approach to synthesis of switched-capacitor networks containing operational amplifiers is given. The method starts with a signal flowgraph and, by the use of several transformations, a suitable structure is obtained which realises the given biquadratic transfer function. The procedure is straight-forward and flexible and is illustrated by an example.     

Topological analysis of switched-capacitor networks

A topological approach to the analysis of s.c. networks is presented. A graph model is chosen and explicit formulae are subsequently derived for all transfer functions in the z-domain. A corresponding topological analysis program has been constructed, giving transfer functions which are analytically dependent on z and capacitance elements.     

Voltage amplification in switched-capacitor networks

The letter deals with the voltage amplification property of networks containing only capacitors and switches. It is shown that with any given n capacitors a circuit comprising a finite number of switches may be realised for which a voltage amplification close to 2n is achievable. If there is freedom in choosing the capacitors, then a switching circuit may be designed for which voltage amplification close to 22n?2+2n?1 is achievable. It is conjectured that this number presents the upper bound of voltage amplification achievable by means of an SC circuit with n capacitors.     

Improved common-mode feedback circuit suitable for operational transconductance amplifiers with tuning

A simple modification is proposed for a popular common-mode feedback circuit used in operational amplifiers, such that it can be used in an operational transconductance amplifier (OTA) without leading to significant DC offset caused by the unavoidable tuning of the OTA. Simulation results show that the improved circuit has nearly zero DC offset for the whole tuning range.<>     

THE DESIGN OF BALANCED AMPLIFIER BASED ON COMMON-MODE FEEDBACK

The balanced operational amplifier including its merits and designing methods is discussed by comparing its performance to a conventional differential output amplifier when used in a single balanced stage. A balanced OTA circuit design is also presented.     

Current-mode common-mode feedback for constant signal behaviour control in rail-to-rail input realisation

A new circuitry is introduced to maintain the constant signal behaviour for rail-to-rail input stages, and is suitable for general mixed-signal ultra-large-scale-integration and system-on-chip applications in contemporary nanoscale CMOS technologies. The constant signal performance is verified by experimental results in a 65 nm standard digital CMOS technology.     

Method of simplified analysis of switched-capacitor networks

A simple by-inspection method is described for the z-domain analysis of switched-capacitor networks. The approach is based on the nodal admittance matrix and a concept of basic elements for the switched capacitor.     

Feedforward associative memory switched-capacitor artificial neural networks

Observed spatiotemporal firings of biological neurons have lead many researchers to believe that the rate of firings of these biological neurons is what conveys neuronal information in the brain. In this paper we seek to highlight parallels between biological neurons and observed effects in real neurons, with artificial neurons implemented as switched-capacitor structures. One such effect is the heavy use of lateral inhibition observed in the brain that is often modeled by winner-take-all analog circuits. This paper introduces a novel winner-take-all circuit using switched capacitors that truly mimics this effect seen in biological systems. In addition, we show how switched-capacitor structures can also cater to both binary and bipolar coding of input data vectors, as required by many artificial neural network paradigms today. Applications of switched-capacitors artificial neural networks to pattern recognition and character recognition problems using feedforward associative neural networks are also discussed, and two examples are provided. Simulations using both HSPICE and SWITCAP2 confirm all our expectations.     

Compact matrix scheme for use in computer analysis of switched-capacitor networks

The matrices that normally occur in the analysis of multiphase switched-capacitor networks are quite large and very sparse. A technique is presented which reduces the matrix order and increases the fill. Storage requirements are minimised and the arithmetic handling of large arrays is reduced without recourse to sparse matrix procedures.     

Realization of second-order transfer functions with switched-capacitor networks

A flexible switched-capacitor synthesis procedure realizing second-order z-domain voltage-transfer functions is given. The active networks generated by this technique consist of capacitors, switches and operational amplifiers.