共查询到20条相似文献,搜索用时 921 毫秒
1.
《Electron Devices, IEEE Transactions on》2009,56(6):1228-1234
2.
A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller 总被引:3,自引:0,他引:3
《Solid-State Circuits, IEEE Journal of》2006,41(9):2115-2124
A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-$muhbox m$ standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2$muhbox m^2$ three-transistor (3T) OTP cells where each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking transistor, and an access transistor, which are all compatible with standard CMOS process. In order for high density implementation, the size of the 3T cell has been reduced by 80% in comparison to previous work. The fabricated total chip size, including 32-KB OTP ROM, which can be programmed via external$hboxI^2hboxC$ master device such as universal$hboxI^2hboxC$ serial EEPROM programmer, 16-bit microcontroller with 16-KB program SRAM and 8-KB data SRAM, peripheral circuits to interface other system building blocks, and bonding pads, is 9.9$hbox mm^2$ . This paper describes the cell, design, and implementation of high-density CMOS OTP ROM, and shows its promising possibilities in embedded applications. 相似文献
3.
Hsiao S.-F. Tsai M.-Y. Wen C.-S. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2010,57(1):21-25
4.
Three-transistor one-time programmable (OTP) ROM cell array using standard CMOS gate oxide antifuse 总被引:1,自引:0,他引:1
Jinbong Kim Kwyro Lee 《Electron Device Letters, IEEE》2003,24(9):589-591
A three-transistor (3-T) cell CMOS one-time programmable (OTP) ROM array using CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high-voltage blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option of high-density CMOS OTP ROM array for modern digital as well as analog circuits. 相似文献
5.
Kung-Hong Lee Shih-Chen Wang Ya-Chin King 《Electron Devices, IEEE Transactions on》2005,52(12):2676-2681
A multilevel/analog electrically erasable programmable read only memory cell fabricated by standard CMOS logic process is presented. The cell is operated by select-gate-controlled channel current induced drain avalanche hot hole for programming and hot electron for erasing. The self-convergent programming scheme proposed allows this cell to be easily adopted for the multilevel or analog storage. In addition, a compact SPICE subcircuit model of the cell has been established to facilitate cell behavior simulation with its interfacing circuits, especially for multilevel/analog nonvolatile memory applications. 相似文献
6.
《Solid-State Circuits, IEEE Journal of》1987,22(5):669-675
A high-density (512K-word/spl times/8-b) erasable programmable read-only memory (EPROM) has been designed and fabricated by using 0.8-/spl mu/m n-well CMOS technology. A novel chip layout and a sense-amplifier circuit produce a 120-ns access time and a 4-mA operational supply current. The interpoly dielectric, composed of a triple-layer structure, realizes a 10-/spl mu/s/byte fast programming time, in spite of scaling the programming voltage V/SUB PP/ from 12.5 V for a 1-Mb EPROM to 10.5 V for this 4-Mb EPROM. To meet the increasing demand for a one-time programmable (OTP) ROM, a circuit is implemented to monitor the access time after the assembly. A novel redundancy scheme is incorporated to reduce additional tests after the laser fuse programming. Cell size and chip size are 3.1/spl times/2.9 /spl mu/m/SUP 2/ and 5.86/spl times/14.92 mm/SUP 2/, respectively. 相似文献
7.
Zhang K. Bhattacharya U. Zhanping Chen Hamzaoglu F. Murray D. Vallepalli N. Yih Wang Zheng B. Bohr M. 《Solid-State Circuits, IEEE Journal of》2005,40(4):895-901
A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data. 相似文献
8.
This paper describes a novel low-power wideband low-phase noise divide-by-two frequency divider.Hereby,a new D-latch topology is introduced.By means of conventional dynamic source-coupled logic techniques,the divider demonstrates a wideband with low phase noise by adding a switch transistor between the clock port and the couple node of the input NMOS pair in the D latch.The chip was fabricated in the 90-nm CMOS process of IBM.The measurement results show that the frequency divider has an input frequency range from 0.05 to 10 GHz and the phase noise is-159.8 dBc/Hz at 1 MHz offset from the carrier.Working at 10 GHz,the frequency divider dissipates a total power of 9.12 mW from a 1.2 V supply while occupying only 0.008 mm2 of the core die area. 相似文献
9.
《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(7):883-892
10.
Asymmetric halo CMOSFET to reduce static power dissipation with improved performance 总被引:2,自引:0,他引:2
In this paper, we show the benefits of using asymmetric halo (AH, different source, and drainside halo doping concentrations) MOSFETs over conventional symmetric halo (SH) MOSFETs to reduce static leakage in sub-50-nm CMOS circuits. Device doping profiles have been optimized to achieve minimum leakage at iso on-current. Results show a 61% reduction in static leakage in AH nMOS transistor and a 90% reduction in static leakage in AH pMOS transistor because of reduced band-to-band tunneling current in the reverse biased drain-substrate junctions. In an AH CMOS inverter, static power dissipation is 19% less than in an SH CMOS inverter. Propagation delay in a three-stage ring oscillator reduces by 11% because of reduced drainside halo doping and hence reduced drain junction capacitance. Further comparisons have been made on two-input NAND and NOR CMOS logic gates. 相似文献
11.
McAdams H.P. Acklin R. Blake T. Xiao-Hong Du Eliason J. Fong J. Kraus W.F. Liu D. Madan S. Moise T. Natarajan S. Ning Qian Yunchen Qiu Remack K.A. Rodriguez J. Roscher J. Seshadri A. Summerfelt S.R. 《Solid-State Circuits, IEEE Journal of》2004,39(4):667-677
A low-voltage (1.3 V) 64-Mb ferroelectric random access memory (FRAM) using a one-transistor one-capacitor (1T1C) cell has been fabricated using a state-of-the-art 130-nm transistor and a five-level Cu/flouro-silicate glass (FSG) interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate-oxide low-voltage logic process. Novel overwrite sense amplifier and programmable ferroelectric reference generation schemes are employed for fast reliable read-write cycle operation. Address access time for the memory is less than 30 ns while consuming less than 0.8 mW/MHz at 1.37 V. An embedded FRAM (eFRAM) density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/. 相似文献
12.
Akil N. van Duuren M. Slotboom M. Baks W. Goarin P. van Schaijk R. Tello P.G. Cuppens R. 《Electron Devices, IEEE Transactions on》2005,52(4):492-499
The performance of compact nonvolatile memory cells, meant for embedded applications in advanced CMOS processes, is studied and analyzed in detail by means of technology computer-aided design (TCAD), and new experimental results are presented. Improvement of the memory performance is achieved. The key element of this improvement is access gate oxide thickness reduction combined with suitable design of the channel/source/drain doping profiles. An increase of the memory readout current by a factor of two was achieved with an excellent low-leakage current level of the access gate transistor. The increase of the read current allows faster read access, while the excellent subthreshold behavior of the access gate transistor allows aggressive scaling of the access gate length down to 160 nm. A gate voltage as low as 1 V can be used for reading the cell, so there is no need for voltage boosting. The source-side injection programming speed is increased by one order of magnitude for devices with thin access gate oxide. The compact cell is suited for embedded applications in sub-100-nm CMOS generations. 相似文献
13.
Furumiya M. Ohkubo H. Muramatsu Y. Kurosawa S. Okamoto F. Fujimoto Y. Nakashiba Y. 《Electron Devices, IEEE Transactions on》2001,48(10):2221-2227
A high-photosensitivity and no-crosstalk pixel technology has been developed for an embedded active-pixel CMOS image sensor, by using a 0.35-μm CMOS logic process. To increase the photosensitivity, we developed a deep p-well photodiode and an antireflective film, consisting of Si3N4 film, for the photodiode surface. To eliminate the high voltage required for the reset transistor in the pixel, we used a depletion-type transistor as the reset transistor. The reset transistor also operates as an overflow control gate, which enables antiblooming overflow when excess charge is generated in the photodiode by high-illumination conditions. To suppress pixel crosstalk caused by obliquely incident light, a double-metal photoshield was used, while crosstalk caused by electron diffusion in the substrate was suppressed by using the deep p-well photodiode. A 1/3-in 330-k-pixel active-pixel CMOS image sensor was fabricated using this technology. A sensitivity improvement of 110% for 550-nm incident light was obtained by using the deep p-well photodiode, while an improvement of 24% was obtained by using the antireflective film. The pixel crosstalk was suppressed to less than 1% throughout the range of visible light 相似文献
14.
设计研制了一款适用于数据通路的10万门容量的FPGA器件FDP100K(FDP:FPGA for Data-Path),其主要特点为:可编程逻辑单元结构不同于国际上已有的可编程逻辑单元结构,是一种新颖的基于查询表LUT和多路选择器MUX的混合结构;连线资源结构采用新颖的层次式布线结构,提供高度灵活的布线能力.芯片采用SMIC 0.35 μm CMOS工艺,包含1024个可编程逻辑单元和128个可编程IO单元.芯片配合自主开发的软件系统FDE(FPGA Development Environment)进行测试,结果表明:FDP100K芯片的可编程逻辑单元功能正常;芯片的各种连线资源功能正常;可以准确地实现数据通路型电路和其他类型的电路的功能. 相似文献
15.
《Electron Device Letters, IEEE》2009,30(3):246-249
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17.
《Semiconductor Manufacturing, IEEE Transactions on》2009,22(1):31-39
18.
研究了新型的FDP FPGA电路结构及其设计实现.新颖的基于3输入查找表的可编程单元结构,与传统的基于4输入查找表相比,可以提高约11%的逻辑利用率;独特的层次化的分段可编程互联结构以及高效的开关盒设计,使得不同的互联资源可以快速直接相连,大大提高了可编程布线资源效率.FDP芯片包括1600个可编程逻辑单元、160个可用IO、内嵌16k双开块RAM,采用SMIC 0.18μm CMOS工艺全定制方法设计并流片,其裸芯片面积为6.104mm×6.620mm.最终芯片软硬件测试结果表明:芯片各种可编程资源可以高效地配合其软件正确实现用户电路功能. 相似文献
19.
J.R. Raguet R. Laffont R. Bouchakour V. Bidal A. Regnier J.M. Mirabel 《Solid-state electronics》2008,52(10):1525-1529
A new 0.56 μm2 dual-gate EEPROM transistor is presented in this paper. To optimize the cell layout, a new model based on previous work has been developed. This concept allows single bit memory operations with high density; new cell programming conditions has been defined to optimize electrical behavior. Concept has been validated in an EEPROM standard technology from STMicroelectronics and allows a cell area reduction of above 50%. With appropriate potentials, the cell produces a programming window of 4 V. Moreover, this dual-gate transistor in static mode becomes an adjustable threshold voltage transistor which can be used in logic circuit or RFID applications. 相似文献
20.
Hoskote Y. Bloechel B.A. Dermer G.E. Erraguntla V. Finan D. Howard J. Klowden D. Narendra S.G. Ruhl G. Tschanz J.W. Sriram Vangal Veeramachaneni V. Wilson H. Jianping Xu Borkar N. 《Solid-State Circuits, IEEE Journal of》2003,38(11):1866-1875
This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This prototype chip employs a high-speed core and a specialized instruction set. It includes hardware support for dynamically reordering out-of-order packets. In a 90-nm CMOS process, the 8-mm/sup 2/ experimental chip has 460 K transistors. First silicon has been validated to be fully functional and achieves 9.64-Gb/s packet processing performance at 1.72 V and consumes 6.39 W. 相似文献