多项式拟合在log-add算法单元中的应用及其FPGA实现

综合考虑面积和速度等因素,采用一次多项式拟合实现了简单快速的log-add算法单元。实验结果表明,在相同的精度要求下,其FPGA实现资源占用合理,硬件开销好于其他次数的多项式拟合实现方案。     

基于FPGA的IEEE802.11协议帧生成器的设计

IEEE 802.11, the most popular standard, defines the protocols which covers all of Ethernet based wireless communication. This paper presented an implementation of IEEE 802.11 Frame Generator, which used FPGA as a hardware platform. This generator constructs the 802.11 frame and supplied it to DSSS as signal to be sent. There are 3 modules in this design. The 1st is the global control module, the 2nd module is CRC- 32 check and the 3rd is used to produce frame serial number. The characteristic of this de- sign is that the signal process and the transmission are made at the same time, i.e. real time processing. That is important to the wireless network device, which has narrower bandwidth and lower process energy. The Verilog HDL codes, block diagram of the whole system, and the simulation results were described in this paper.     

基于ARM和FPGA的经济型数控系统硬件设计与实现

为解决目前经济型数控系统功能单一、运算能力不强、控制精度较低的问题,提出并实现了一种经济型数控系统硬件设计方案.该方案以ARM处理器EP9315作为主控芯片,应用FPGA实现反馈编码器和进给轴控制功能,并采用单片机MSP430完成模拟主轴控制和A/D采样功能.在实现通用的数控接口功能的基础上,还实现了网络、USB、CAN等通信接口功能,为数控系统网络化和今后的功能扩展提供了多种硬件支持.仿真和系统实验结果表明,该系统样机各项功能、性能达到数控系统的较高水平.     

基于FPGA的并行DDS信号发生器的设计与实现

针对DDS(直接数字频率合成)电路的运算速度受相位累加器的累加速度和ROM读取速度的约束问题,采用多路并行和流水线相结合的方法改进了DDS电路的结构,有效地扩展了DDS电路的输出带宽。通过在FPGA内设计基于双DDS电路结构的信号发生器,用数字的方法直接实现了标准波形和各种调制波形的双通道输出。该方案结构简单,控制灵活,实验测试结果表明,该信号发生器能输出稳定、高带宽、高速度、高精度的信号波形。     

FPGA implementation of an enhanced chaotic-KASUMI block cipher

The radio link is a broadcast channel used to transmit data over mobile networks. Because of the sensitivity of this network part, a security mechanism is used to ensure users’ information. For example, the third generation of mobile network security is based on the KASUMI block cipher, which is standardized by the Third Generation Partnership Project (3GPP). This work proposes an optimized and enhanced implementation of the KASUMI block cipher based on a chaotic generator. The purpose is to develop an efficient ciphering algorithm with better performance and good security robustness while preserving the standardization. The proposed design was implemented on several Xilinx Virtex Field Programmable Gate Arrays (FPGA) technologies. The synthesis results and a comparison with previous works prove the performance improvement of the proposed cipher block in terms of throughput, used hardware logic resources, and resistance against most cryptanalysis attacks.     

基于FPGA实现DES算法的性能分析

本文在分析DES算法机理的基础上,详细介绍了算法各个环节的实现方法,给出了算法流水线与状态机方案的设计实例,并对不同方案的测试结果进行了分析比较。     

基于AVS的变字长解码器的设计及其FPGA验证

提出了一个完整的AVS变字长解码器的硬件架构,在设计中采用加入FIFO的方法构成流水结构,并尽量减少变字长解码器中各子模块的运行节拍,大大提高了系统的运行速度。本设计已经通了FPGA验证。该变字长解码器不仅可以成为其他AVS解码器的硬件加速器,同时由于视频编解码标准的相似性,稍加改动即可应用在其他的视频标准中。     

说话人识别系统中VQ判决模块的FPGA实现

目前,基于PC或DSP的系统其处理能力无法满足海量语音信号高速处理需求的增长。本文分析了VQ(矢量量化)搜索算法的硬件实现复杂度,针对说话人识别过程中运算量最大、耗时最长的判决过程,提出了一种基于标签的说话人判决模型实现方案。该设计用FPGA实现,可对多路电话信道说话人进行实时判决识别。     

基于FPGA的多功能图像目标发生器的设计与实现

本文介绍了一种基于FPGA的图像目标发生器的设计方法,介绍了它的设计原理、硬件电路结构、各功能的实现方法。该图像发生器能产生灰度阶图像、静态目标图像和运动目标图像,用来对图像采集系统进行评估。     

AES中SubBytes算法在FPGA的实现

介绍了AES中,SubBytes算法在FPGA的具体实现.构造SubBytes的S-Box转换表可以直接查找ROM表来实现.通过分析SubBytes算法得到一种可行性硬件逻辑电路,从而实现SubBytes变换的功能.     

数字电视CAS中DES加密模块的FPGA实现

一种基于 FPGA 的数据加密标准算法的实现。就资源优先和性能优先分别使用循环法和流水线法对 DES 加密算法进行了设计,并对其进行了比较。通过采用子密钥简单产生和 ROM 优化 S盒的方法,对流水线法进行改进,达到了资源占用率低、加密速度快的效果。     

H.264中自适应二进制算术编码器的FPGA实现

H.264是目前国际上最新、最有前途的视频压缩标准,基于上下文的自适应二进制算术编码是H.264中一种高效的熵编码,但算法比较复杂,执行速度不高。本文提出一种基于流水线的自适应二进制算术编码器的FPGA结构。在实现过程中,对原有的软件流程进行了部分改进以满足硬件实现要求,采用流水线及并行处理技术设计整个电路。     

An FPGA implementation of real-time K-means clustering for color images

K-means clustering is a very popular clustering technique, which is used in numerous applications. In the k-means clustering algorithm, each point in the dataset is assigned to the nearest cluster by calculating the distances from each point to the cluster centers. The computation of these distances is a very time-consuming task, particularly for large dataset and large number of clusters. In order to achieve high performance, we need to reduce the number of the distance calculations for each point efficiently. In this paper, we describe an FPGA implementation of k-means clustering for color images based on the filtering algorithm. In our implementation, when calculating the distances for each point, clusters which are apparently not closer to the point than other clusters are filtered out using kd-trees which are dynamically generated on the FPGA in each iteration of k-means clustering. The performance of our system for 512 × 512 and 640 × 480  pixel images (24-bit full color RGB) is more than 30 fps, and 20–30 fps for 756 × 512 pixel images in average when dividing to 256 clusters.

快速视频去雾改进算法的FPGA实现

内窥镜去雾算法在医疗领域具有广泛应用,为临床医生提供清晰、实时的图像。去雾技术虽然已经取得较大的进步,但去雾算法的复杂度较高,在内窥镜等复杂情况下硬件实现较为困难。为了在硬件上实现内窥镜实时去雾效果,对暗通道先验算进行改进,降低硬件资源消耗和时间复杂度。该改进算法选择适合硬件的大气光照强度估计值、透射率补偿值以及采用流水线结构实现有雾图像的处理。采用Xilinx的ZYNQ7020实现该算法硬件电路,实时处理分辨率为640×480的视频图像,速度可达到260 fps,消耗LUT仅为1.28K,寄存器619个单元。实验结果表明,相比于传统算法,改进算法具有处理速度快、功耗低、可移植性强的特点,满足内窥镜需要实时处理视频的要求。     

基于FPGA的三角函数数字发生器设计

系统而严格地论证与实现了一个基于FPGA与直接数字式频率合成技术的三角函数正弦数字信号发生器,首先介绍了DDS技术的发展历史及其在无线通信系统中的重要作用,接下来阐述了它的工作原理、系统结构,以及理论上的可行性与正确性,最后给出了其实际设计过程、RTL结构图与仿真波形测试结果。     

FPGA implementation of bearing tracking using passive array for underwater acoustics

Within the scope of this study, a Field Programmable Gate Array (FPGA) based system which calculates bearing angles by analyzing the signals emitted by vessels in underwater environment is proposed. An array consisting of 3 non-directional hydrophones were designed and used in tests. Minimum Variance Distortionless Response (MVDR) algorithm was used in the bearing calculations according to the reference hydrophone. In marine tests, hydrophone array was integrated into the buoy, and then tested. The angle between the reference hydrophone and the magnetic north is calculated in order to correct the errors caused by the immobility of the buoy and underwater array. In the developed system, all operations were carried out on Artix 7 FPGA. Fixed point number format is used and implementation stages are designed as pipeline architecture. In the marine tests performed, it was monitored in real time that the bearing information calculated by the system was compatible with the route of the vessel used in the tests. The signals received by bearing information and the hydrophones were recorded. The records were run offline, and the calculated values were compared. The results obtained showed that the developed FPGA-based system successfully calculates the bearing angle of the vessels by passive listening.     

GSM全速率语音编码中Schur递归算法的FPGA实现

Schur递归算法是GSM全速率语音编码算法中计算短期滤波参数的一个关键部分。由于它是一个典型的双循环结构,所以在算法的FPGA实现中也具有代表意义,本文对Schur递归算法的特点进行了详细的分析,提出了一种利用FPGA实现Schur递归算法的方案,并对其实现过程中各模块的设计方法进行了详细的分析。     

基于FPGA的量化推理CNN加速系统研究与设计

基于FPGA的量化推理设计了CNN加速系统;通过对主流的深度神经网络结构的运算特性分析,使用(Density-Based Spatial Clustering of Applications with Noise) DBSCAN聚类算法截取阈值的INT8量化推理方法,融合深度神经网络全连接,减少数据运算位宽和压缩网络大小,在准确率损失很小的情况下有效压缩了网络结构;基于LeNet-5、VGG-16与ResNet-50的CNN网络结构,设计出量化CNN加速系统并进行校验;实验结果表明,网络参数和输入特征数据量化精度为8-bits时,网络压缩率在25%的情况下,网络准确率的损失低于1%;在Xilinx XC7K325平台上量化推理CNN加速系统的运行频率为450 MHz,与其他相似类型的加速器比较,其GOPS性能提升2倍。     

获取目标最佳极化算法的FPGA实现

根据带门限的序列Jacobi方法,提出了一种实时获取目标最佳极化的FPGA实现方法。该方法精简了对待求矩阵最大非对角元素的搜索过程,并在FPGA中采用并行结构的运算模块设计,优化了有限状态机(FSM)的执行时序,从而避免了CORDIC算法繁琐的迭代过程,减少了程序运行时间。FPGA实现结果表明,该方法的执行速度比CORDIC算法至少提高了21%,具有较高的实时性。     

MIMO OFDM系统中一种V-BLAST检测算法的FPGA实现

给出了一种V-BLAST检测算法的FPGA实现方案,该算法基于Greville求伪逆的方法。设计主要考虑了流水线操作和并行度处理。算法在Xilinx公司的Vertex Ⅱ Pro系列FPGA中实现,在B3G TDD MIMO OFDM系统硬件平台上进行了验证,性能良好。