A novel technique to decouple electrical and thermal effects in SOA limitation of power LDMOSFET

This letter reports a novel technique to isolate thermal and electrical failure mechanisms in a power LDMOSFET device by deactivating the parasitic bipolar transistor while maintaining the MOS gate control. It is shown that the energy capability of the device remains constant as a function of the drain voltage in the event of a purely thermal failure, whereas the standard device shows a decrease in energy capability indicating electrothermal coupling. Nevertheless, the standard device energy capability is close to that obtained in the case of pure thermal failure, indicating that the thermal phenomenon dominates in determining the device failure and that electrical effects, though present, only minutely influence the device failure.     

表面注入D-RESURF器件耐压模型

建立表面注入双重降低表面电场(D-RESURF)结构击穿电压模型。D-RESURF器件在衬底纵向电场和Pb区附加电场的影响下,漂移区电荷共享效应增强,优化漂移区掺杂浓度增大,器件导通电阻降低。分析漂移区浓度和厚度对击穿电压的影响,获得改善击穿电压和导通电阻折中关系的途径。在满足最优表面电场和完全耗尽条件下,导出吻合较好的二维RESURF判据。在理论的指导下,成功研制出900 V的D-RESURF高压器件。     

A floating RESURF (FRESURF) LD-MOSFET device concept

This letter reports a novel device concept, which is an extension of the conventional reduced surface field (RESURF) concept. A heavily doped n-type floating region is introduced into the conventional device structure which allows the breakdown capability of the device to be increased significantly while at the same time making it high-side capable. This floating RESURF (FRESURF) device concept allows the realization of significantly higher breakdown voltage in a thin epitaxy based power integrated circuit (IC) technology. A FRESURF lateral double-diffused power MOS transistor is designed, fabricated and reported for the first time with breakdown voltages as high as 90 V as opposed to 55 V obtained from conventional device sharing same process and drift region doping.     

A double RESURF LDMOS with drain profile engineering for improvedESD robustness

This letter reports a novel 50 V lateral power MOSFET structure that is self-protecting with respect to electrostatic discharge (ESD) strikes. This device features a double RESURF technique in conjunction with a deep drain engineered profile that eliminates soft leakage degradation after snapback, thus demonstrating immunity to filamentation. Maximum second breakdown current (I_t2) of 16 mA/μm has been realized in a 100 ns transmission line pulse (TLP) measurement even with a higher holding voltage of 20 V. ESD protection level in excess of 5 kV with an equivalent human body model (HBM) has been shown to be feasible for this device without significant compromise in device size     

基于漏区边界曲率分析的射频RESURF LDMOS耐压与导通电阻优化

分析了漏区边界曲率半径与射频RESURF LDMOS击穿电压的关系,指出漏区边界的弯曲对RESURF技术的效果具有强化作用.理论分析与模拟结果表明,满足RESURF条件时,提高漂移区掺杂浓度或掺杂深度的同时相应减小漏区边界的曲率半径,可以在维持击穿电压不变的前提下,明显降低导通电阻.     

薄外延阶梯掺杂漂移区RESURF耐压模型

提出薄外延阶梯掺杂漂移区RESURF结构的耐压解析模型。借助求解二维Po isson方程,获得薄外延阶梯掺杂漂移区的二维表面电场和击穿电压的解析表达式。基于此耐压模型研究了不同阶梯漂移区数(n=1、2、3、5)的击穿特性,计算了击穿电压与结构参数的关系,其解析结果与数值结果吻合较好。在相同长度下,阶梯掺杂漂移区结构(n=3)击穿电压由均匀漂移区(n=1)的200 V提高到250 V,增加25%。该模型可用于薄外延阶梯掺杂和线性掺杂漂移区RESURF器件的设计优化。     

新型双RESURF TG-LDMOS器件结构

研究了采用双RESURF技术的槽栅横向双扩散MOSFET(DRTG-LDMOS).讨论了双RESURF技术对击穿电压的影响,以及DRTG-LDMOS的电容特性.与传统的槽栅器件结构相比,新结构在相同的漂移长度和导通电阻下,击穿电压提高了30V,并表现出优异的频率特性.     

A novel double RESURF LDMOS and a versatile JFET device used as internal power supply and current detector for SPIC

In this paper, a novel double RESURF LDMOS with multiple rings in non-uniform drift region is proposed and successfully fabricated. The proposed device maximizes the benefits of the double RESURF technique by optimizes key process and device geometrical parameters in order to achieve the lowest on-resistance with the desired breakdown voltage. In addition, a versatile JFET device is firstly developed. The JFET device cannot only be used as the current detector, but also be used as the internal power supply for SPIC. Besides, it is compatible with Bipolar-CMOS technology, without any additional processes required.     

新型双RESURF TG-LDMOS器件结构

研究了采用双RESURF技术的槽栅横向双扩散MOSFET（DRTG-LDMOS），讨论了双RESURF技术对击穿电压的影响，以及DRTG-LDMOS的电容特性，与传统的槽栅器件结构相比，新结构在相同的漂移长度和导通电阻下，击穿电压提高了30V，并表现出优异的频率特性；     

半桥驱动芯片中LDMOS的设计仿真

借助工艺和器件仿真软件,对一种用于功率MOSFET和IGBT栅极驱动的半桥驱动芯片中的横向高压功率器件LDMOS进行了设计与仿真。该器件采用了双RESURF技术及双层浮空场板结构,通过对双层浮空场板层之间的距离以及双RESURF结构的ptop层的长度和浓度的优化设计,利用传统的Bi-CMOS工艺获得击穿电压689V和比导通电阻273×10–3.cm2的LDMOS。     

RESURF AlGaN/GaN HEMT for high voltage power switching

A novel HEMT configuration based on the RESURF technique is proposed for very high voltage power switching applications. It employs a p-n junction below the 2-DEG channel and two field plates, one extending from the gate and the other from the drain, to distribute the electric field over the gate to drain separation. 2-D simulations indicate a breakdown voltage >1 KV at on-resistance of ~1 mΩ·cm² (neglecting contact resistances) for the device     

有n埋层结构的1200V横向变掺杂双RESURF LDMOS研制

提出有n埋层的横向变掺杂双RESURF 新结构高压LDMOS器件.该结构器件与常规LDMOS相比,采用了相对较薄的外延层,使之与标准CMOS工艺的兼容性得到了改善.基于二维器件仿真软件MEDICI分析了n埋层的浓度、长度和p－降场层的杂质浓度分布对器件耐压的影响,并进行了器件和工艺的优化设计.在国内工艺生产线成功地研制出1200V高压LDMOS,并已用于1200V功率集成电路中.     

Simulation and Fabrication Studies of Semi‐superjunction Trench Power MOSFETs by RSO Process with Silicon Nitride Layer

In this letter, we propose a new RESURF stepped oxide (RSO) process to make a semi‐superjunction (semi‐SJ) trench double‐diffused MOSFET (TDMOS). In this new process, the thick single insulation layer (SiO₂) of a conventional device is replaced by a multilayered insulator (SiO₂/SiN_x/TEOS) to improve the process and electrical properties. To compare the electrical properties of the conventional RSO TDMOS to those of the proposed TDMOS, that is, the nitride_RSO TDMOS, simulation studies are performed using a TCAD simulator. The nitride_RSO TDMOS has superior properties compared to those of the RSO TDMOS, in terms of drain current and on‐resistance, owing to a high nitride permittivity. Moreover, variations in the electrical properties of the nitride_RSO TDMOS are investigated using various devices, pitch sizes, and thicknesses of the insulator. Along with an increase of the device pitch size and the thickness of the insulator, the breakdown voltage slowly improves due to a vertical field plate effect; however, the drain current and on‐resistance degenerate, owing to a shrinking of the drift width. The nitride_RSO TDMOS is successfully fabricated, and the blocking voltage and specific on‐resistance are 108 V and 1.1 mΩcm², respectively.     

Design of 700 V triple RESURF nLDMOS with low on-resistance

A 700 V triple RESURF nLDMOS with a low specific on-resistance of 100 mΩ·cm~2 is designed.Compared with a conventional double RESURF nLDMOS whose P-type layer is located on the surface of the drift region,the P-type layer of a triple RESURF nLDMOS is located within it.The difference between the locations of the P-type layer means that a triple RESURF nLDMOS has about a 30%lower specific on-resistance at the same given breakdown voltage of 700 V.Detailed research of the influences of various parameters on breakdown voltage,specific on-resistance,as well as process tolerance is involved.The results may provide guiding principles for the design of triple RESURF nLDMOS.     

A novel high-performance asymmetric hetero-doped S/D high-voltage MOSFET

A novel high-voltage MOSFET structure, using a simple yet effective concept of an asymmetric hetero-doped source/drain (S/D) is proposed. The asymmetric hetero-doped S/D reduces the on-state resistance of the transistor due to the high doping used for device drain drift, provides excellent ruggedness for parasitic NPN turned-on due to a minimized n/sup +/ source spacer, and also raises the device breakdown voltage due to charge compensation in the composite drain drift region. Therefore, the asymmetric hetero-doped S/D structure allows the high voltage MOSFET to have a high current handling capability with a small device size. This in turn causes the R (sp, on) to be low, leading to high performance for the power device when used in a power integrated circuit. Measured results show that a 24-V breakdown voltage new device with a low-cost two-layer metal (Al) back-end achieves very low R (sp, on) of 0.166 m/spl Omega//spl middot/cm/sup 2/. Furthermore, the new device with a 65-V high-side capability achieves good isolation performance even when switching S/D to -20 V and also gets a cutoff frequency of 13 GHz at a gate voltage of 5.5 V.     

Breakdown Voltage Improvement of p‐LDMOSFET with an Uneven Racetrack Source for PDP Driver IC Applications

We investigated the electrical characteristics of p‐channel double‐diffused MOSFETs (p‐LDMOSFETs) with an uneven racetrack source (URS) and a conventional racetrack source (CRS) for PDP driver IC applications. The breakdown voltage of the p‐LDMOSFET with the URS in off‐state was nearly the same as the p‐LDMOSFET with the CRS. However, the breakdown voltage of the p‐LDMOSFET with the URS in on‐state was about 30% higher than that of the p‐LDMOSFET with the CRS, while the saturated drain current of the p‐LDMOSFET with the URS was only about 4% lower than that of the p‐LDMOSFET with the CRS.     

Characteristics of AlGaN/GaN/AlGaN double heteroj unction HEMTs with an improved breakdown voltage

正We studied the performance of AlGaN/GaN double heterojunction high electron mobility transistors (DH-HEMTs) with an AlGaN buffer layer,which leads to a higher potential barrier at the backside of the twodimensional electron gas channel and better carrier confinement.This,remarkably,reduces the drain leakage current and improves the device breakdown voltage.The breakdown voltage of AlGaN/GaN double heterojunction HEMTs (~ 100 V) was significantly improved compared to that of conventional AlGaN/GaN HEMTs(~50 V) for the device with gate dimensions of 0.5 x 100μm and a gate-drain distance of 1μm.The DH-HEMTs also demonstrated a maximum output power of 7.78 W/mm,a maximum power-added efficiency of 62.3%and a linear gain of 23 dB at the drain supply voltage of 35 V at 4 GHz.     

Improved high-voltage lateral RESURF MOSFETs in 4H-SiC

High-voltage lateral RESURF metal oxide semiconductor field effect transistors (MOSFETs) in 4H-SiC have been experimentally demonstrated, that block 900 V with a specific on-resistance of 0.5 Ω-cm² . The RESURF dose in 4H-SiC to maximize the avalanche breakdown voltage is almost an order of magnitude higher than that of silicon; however this high RESURF dose leads to oxide breakdown and reliability concerns in thin (100-200 nm) gate oxide devices due to high electric field (>3-4 MV/cm) in the oxide. Lighter RESURF doses and/or thicker gate oxides are required in SiC lateral MOSFETs to achieve highest breakdown voltage capability     

Double RESURF nLDMOS功率器件的优化设计

基于漂移区表面具有单个P-top层Double RESURF nLDMOS的结构和耐压机理,提出了具有P-top层终端结构的Double RESURF nLDMOS结构,并通过利用SENTAURUS TSUPREM4和DEVICES软件进行优化设计。P-top层终端结构不仅降低了击穿电压对P-top层参数的敏感度,而且在漂移区引入一个附加的电场峰值,使漂移区电场分布进一步趋于平坦化。与传统Single RESURF和普通Double RESURF器件相对比,击穿电压可以分别提高约13.5%和4%,导通电阻却提高了11.8%和6%,但在满足击穿电压相等的条件下,该结构通过控制P-top层的位置和漂移区剂量可以使导通电阻降低约37%。     

Lateral RESURF MOSFET fabricated on 4H-SiC(0001/sup ~/) C-face

Lateral reduced surface field (RESURF) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated on 4H-SiC(0001/sup ~/) carbon face (C-face) substrates. The channel mobility of a lateral test MOSFET on a C-face was 41 cm/sup 2//V/spl middot/s, which was much higher than 5 cm/sup 2//V/spl middot/s for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was 79/spl Omega/ /spl middot/ cm/sup 2/, at a gate voltage of 25 V and drain voltage of 1 V. The breakdown voltage was 460 V, which was 79% of the designed breakdown voltage of 600 V. We measured the temperature dependence of R/sub on, sp/ for the RESURF MOSFET on the C-face. The R/sub on, sp/ increased with the increase in temperature.