Clock Feedthrough in CMOS Analog Transmission Gate Switches

An analysis of clock feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for clock feedthrough and a related model of a transmission gate switch are established in the current-voltage domain. A region map is developed for the TG switch during the period when both devices are turned off. The region map is further divided into zones. From these region and zone maps, the sign and relative magnitude of the clock feedthrough noise can be efficiently estimated for different signal levels. Placing the input voltage near half of the power supply voltage is a useful technique for minimizing clock feedthrough noise. A model of clock feedthrough noise as compared with SPICE simulations exhibits less than 3% error. This research was supported in part by the Semiconductor Research Corporation under Contract No. 99-TJ-687, the DARPA/ITO under AFRL Contract F29601-00-K-0182, grants from the New York State Office of Science, Technology & Academic Research to the Center for Advanced Technology—Electronic Imaging Systems and to the Microelectronics Design Center, and by grants from Xerox Corporation, IBM Corporation, Intel Corporation, Lucent Technologies Corporation, and Eastman Kodak Company. Weize Xu received the B.S. degree from Nanjing University of Posts and Telecommunications, China in 1982, and the M.S. degrees from the University of Rhode Island in 1993, both in electrical engineering. Since 1997, he has been a senor research engineer and analog IC design specialist at Eastman Kodak Company. His research interests include high speed analog IC designs, pipelined A/D converter, low power switched capacitor circuit analysis and design, CMOS image sensor design, and analysis of noise in mixed signal ICs. He currently is a Ph.D candidate at the University of Rochester. Eby G. Friedman (S'78-M'79-SM'90-F'00) received the B.S. degree from Lafayette College in 1979, and the M.S. and Ph.D. degrees from the University of California, Irvine, in 1981 and 1989, respectively, all in electrical engineering. From 1979 to 1991, he was with Hughes Aircraft Company, rising to the position of manager of the Signal Processing Design and Test Department, responsible for the design and test of high performance digital and analog IC's. He has been with the Department of Electrical and Computer Engineering at the University of Rochester since 1991, where he is a Distinguished Professor, the Director of the High Performance VLSI/IC Design and Analysis Laboratory, and the Director of the Center for Electronic Imaging Systems. He also enjoyed a sabbatical at the Technion—Israel Institute of Technology during the 2000/2001 academic year. His current research and teaching interests are in high performance synchronous digital and mixed-signal microelectronic design and analysis with application to high speed portable processors and low power wireless communications. He is the author of more than 250 papers and book chapters, several patents, and the author or editor of seven books in the fields of high speed and low power CMOS design techniques, high speed interconnect, and the theory and application of synchronous clock distribution networks. Dr. Friedman is the Regional Editor of the Journal of Circuits, Systems, and Computers, a Member of the editorial boards of the Proceedings of the IEEE, Analog Integrated Circuits and Signal Processing microelectronics Journal, and Journal of VLSI Signal Processing, a Member of the Circuits and Systems (CAS) Society Board of Governors, and a Member of the technical program committee of a number of conferences. He previously was the past Editor-in-Chief of the IEEE Transactions on VLSI Systems, a Member of the editorial board of the IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Chair of the IEEE Transactions on VLSI Systems steering committee, CAS liaison to the Solid-State Circuits Society, Chair of the VLSI Systems and Applications CAS Technical Committee, Chair of the Electron Devices Chapter of the IEEE Rochester Section, Program or Technical chair of several IEEE conferences, Guest Editor of several special issues in a variety of journals, and a recipient of the Howard Hughes Masters and Doctoral Fellowships, an IBM University Research Award, an Outstanding IEEE Chapter Chairman Award, and a University of Rochester College of Engineering Teaching Excellence Award. Dr. Friedman is a Senior Fulbright Fellow and an IEEE Fellow.     

一种高性能CMOS LVDS接收电路的设计

提出了一种符合IEEE Std 1596.3-1996[1]标准,适用于芯片间高速数据传输的低电压差分信号(LVDS)接收电路;有效地解决了传统电路结构在电源电压降至3.3 V或更低以后不能稳定工作在标准规定的整个输入共模电平范围内的问题,电路能在符合标准的0.05~2.35 V输入共模电平范围内稳定工作,传输速率可达1.6 Gb/s,平均功耗1.18 mW。设计基于HJTC(和舰科技)Logic 0.18μm 1.8 V/3.3 V CMOS工艺,使用3.3 V厚栅MOS管和1.8 V薄栅MOS管。     

一种新型的高性能CMOS电流比较器电路

分析了目前几种高性能连续时间 CMOS电流比较器的优缺点 ,提出了一种新型 CMOS电流比较器电路 .它包含一组具有负反馈电阻的 CMOS互补放大器、两组电阻负载放大器和两组 CMOS反相器 .由于 CMOS互补放大器的负反馈电阻降低了它的输入、输出阻抗 ,从而使电压的变化幅度减小 ,所以该电流比较器具有较短的瞬态响应时间和较快的速度 .电阻负载放大器的使用减小了电路的功耗 .利用 1.2 μm CMOS工艺 HSPICE模型参数对该电流比较器的性能进行了模拟 ,结果表明该电路的瞬态响应时间达到目前最快的 CMOS电流比较器的水平 ,而功耗则低于这些比较器 ,具有最大的速     

高性能Rail-to-Rail恒定跨导CMOS运算放大器

基于UMC的0.6μm BCD 2P2M工艺,探讨了一种高性能Rail-to-Rail恒定跨导CMOS运算放大器.该运算放大器的输入级采用互补差分对,其尾电流由共模输入信号来控制,以此来保证输入级的总跨导在整个共模范围内保持恒定.输出级采用ClassAB类控制电路,并且将其嵌入到求和电路中,以此减少控制电路电流源引起的噪声和失调.为了优化运算放大器低频增益、频率补偿、功耗及谐波失真,求和电路采用了浮动电流源来偏置.该运算放大器采用米勒补偿实现了18MHz的带宽,低频增益约为110dB,Rail-to-Rail引起的跨导变化约为15%,功耗约为10mW.     

一种新型的高性能CMOS电流比较器电路

分析了目前几种高性能连续时间CMOS电流比较器的优缺点,提出了一种新型CMOS电流比较器电路．它包含一组具有负反馈电阻的CMOS互补放大器、两组电阻负载放大器和两组CMOS反相器．由于CMOS互补放大器的负反馈电阻降低了它的输入、输出阻抗,从而使电压的变化幅度减小,所以该电流比较器具有较短的瞬态响应时间和较快的速度．电阻负载放大器的使用减小了电路的功耗．利用1.2μm CMOS工艺HSPICE模型参数对该电流比较器的性能进行了模拟,结果表明该电路的瞬态响应时间达到目前最快的CMOS电流比较器的水平,而功耗则低于这些比较器,具有最大的速度/功耗比．此外,该CMOS电流比较器结构简单,性能受工艺偏差的影响小,适合应用于高速/低功耗电流型集成电路中．     

一种高性能CMOS带隙电路的设计

文章提出一种CMOS带隙参考源（BGR）电路设计，它可以在很宽的电压范围内有效的工作，能够在12．8V，10V范围内实现稳定工作，抗干扰能力强，结构相对简单，由CMOS运放，二极管以及电阻组成，用常规的0．6um CMOS工艺制作，在模拟环境下仿真结果表明其最小工作电压为2．75V，完全能够满足锁相环设计的要求。     

一种高性能共模反馈CMOS运算放大器

介绍了一种具有高增益,高电源抑制比(CMRR)和大带宽的两级共源共栅运算放大器。此电路在两级共源共栅运算放大器的基础上增加共模反馈电路,以提高共模抑制比和增加电路的稳定性。电路采用0.35μm标准CMOS工艺库,在Cadence环境下进行仿真。结果显示,该放大器增益可达到101 dB,负载电容为10 pF时,单位增益带宽大约为163 MHz,共模抑制比可达101dB,电路功耗仅为0.5 mW。     

Generic and Accurate Whitebox Behavioral Model for Fast Simulation of Analog Effects in Nanometer CMOS Digital Logic Circuits

Digital CMOS circuits are praised because of their noise immunity. However, lowering power supply voltages and shrinking device sizes, in combination with the rising electromagnetic pollution, have made this statement no longer true. An accurate behavioral model is presented for the analog simulation of digital logic circuits. The model building is automated and scalable in the sense that it allows a tradeoff between model-building speed and accuracy. The proposed model is validated on a seven-stage CMOS ring oscillator and a 112-transistor 4-bit adder, excellent test cases to demonstrate the accuracy. The RMS error remains below 5% in case of electromagnetic interference, and below 2% in all other cases, while achieving speed-ups up to 400 $times$.      

A High-Performance CMOS Voltage-Controlled Oscillator for Ultra-Low-Voltage Operations

In this paper, a novel circuit topology of voltage-controlled oscillators (VCOs) suitable for ultra-low-voltage operations is presented. By utilizing the capacitive feedback and the forward-body-bias (FBB) technique, the proposed VCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of phase noise, tuning range, and output swing. Using a standard 0.18-mum CMOS process, a 5.6-GHz VCO is designed and fabricated for demonstration. Consuming a dc power of 3 mW from a 0.6-V supply voltage, the VCO exhibits a frequency tuning range of 8.1% and a phase noise of -118 dBc/Hz at 1-MHz offset frequency. With an FBB for the cross-coupled transistors, the fabricated circuit can operate at a supply voltage as low as 0.4 V. The measured tuning range and phase noise are 6.4% and -114 dBc/Hz, respectively     

适用于笔记本电脑的高性能CMOS LVDS驱动器的设计

提出了一种适用于笔记本电脑平板显示嚣接口的高性能CMOS LVDS(Low Voltage Differential Signaling)驱动器的设计方法。用高性能CMOS LVDS驱动器作I／O接口单元是减小当前CMOS工艺芯片内外速度差异的重要手段。文章着重分析了高性能CMOS LVDS驱动器的电路结构及其工作原理，采用TSMC的0．25μm CMOS工艺模型，在Cadence环境下用Spectre仿真器进行模拟，给出了该驱动器的仿真结果。     

SOS/CMOS as a High-Performance LSI Device

To realize a high-performance LSI, the devices used should satisfy the following requirements: 1) high-speed operation, 2) low power consumption, 3) easy designability, and 4) high integration capability. SOS/CMOS has been examined both experimentally and theoretically for these aspects. Ideal CMOS operation with /spl tau//sub pd/ ~ 100 ps with 0.1-pJ energy required to switch an inverter is obtained. 1-GHz operation is confirmed on dynamic 1/16 frequency dividers with 1.0-/spl mu/m effective channel-length devices. Using the same device, a maximum multiplying time, /spl tau//sub mul/ ~ 25 ns at 5 V with 15-mW average power at 10/sup 7/ multiplications/s is obtained on a 4 X 4 parallel multiplier. The above result agrees with circuit simulation predictions without including stray capacitance associated with the wiring. The same simulation predicts rmul ~ 60 ns with a maximum power dissipation of 200 mW at 16-MHz operation for a 16 X 16 parallel multiplier. This prediction is also confirmed experimentally. These facts indicate good designability of SOS/CMOS. For larger scale integration capability estimation, power dissipation and wiring delay were examined theoretically for bulk NMOS, bulk CMOS, and SOS/CMOS. The results indicate that for smaller scale integration, bulk NMOS and SOS/CMOS operate faster than bulk CMOS. However, for larger scale integration, SOS/CMOS operates faster than bulk CMOS which, in turn, operates faster than bulk NMOS.     

Fast and Automated Electromigration Analysis for CMOS RF PA Design

This paper presents fast and automated electromigration (EM) reliability modeling by using automated modeling generation (AMG) algorithm. The AMG converts human based EM modeling into an automated modeling and simulation process with the help of ANSYS parametric design language (APDL) program. For automating the neural model training process, training-driven adaptive sampling is applied to integrate data generation, data distributions determination, model structure adaptation, training and testing into a unified framework. Fully automated reliability model construction and simulation is achieved for the first time. This method effectively shortens the period of EM modeling by using dynamic sampling method. Furthermore, the heat generation from active devices has been considered to describe the heat effect on the interconnect reliability. Through the proposed technique, the allowable sizes, temperature and output power of a CMOS radio frequency power amplifier (RF PA) are derived to give reliability criteria for PA designer.     

Optical-Fiber Feedthrough in Pressure Housing

The structure for introducing fibers into the pressure housing of a submarine optical repeater is studied. As a result of investigations into sealing materials, fiber strength, and optical characteristics, the following structure is adopted. Fibers, whose primary coat is metal instead of silicone, are fixed by epoxy resin to withstand water pressure, and the outside surface of the resin is covered with solder to keep the resin free from water vapor. Experimental results show that this structure meets the requirements.     

Logic synthesis of race-free asynchronous CMOS circuits

A synthesis method for generating race-free asynchronous CMOS circuits that are independent of the internal and output delays is presented. The design method is based on the properties of the negative gates. An inertial delay is associated with each negative gate in a CMOS circuit. Such a gate model is quite realistic. The basic principle of the method presented is to augment and to modify the original flow table in such a way that the obtained logic diagram contains only negative gates. In addition, the synthesis method is capable of avoiding any race, and consequently any critical race or hazard. The method minimizes the number of internal variables and therefore the number of gates, providing new simple cells for fast and low-power integrated circuits     

A VLSI High-Performance Priority Encoder Using Standard CMOS Library

A novel high-performance priority encoder design using standard CMOS library cell is proposed. The new encoder design implementation accommodates both high- and low-priority functionalities with scalable design structure through a special prefixing scheme. The prefixing scheme is applied to minimize the entire propagation delay and exploit the shared hardware between the high- and low-priority evaluation logics circuitry. The proposed encoder shows significant improvement in terms of speed, robustness for top-level floor plan routing, and modularity with pattern structure in compared to the existing encoder designs. Simulation results are conducted for different encoder inputs through 0.15-$muhbox m$TSMC CMOS technology, where 32-bit priority encoder is used as a test vehicle for comparison improvement measurements. The expected results show that the 32-bit encoder is operating at a maximum of 667-MHz operating frequency with total count of 1106 transistors and a maximum power consumption of total 13.8 mW.     

The Design of High-Performance Analog Circuits on Digital CMOS Chips

Devices available in digital oriented CMOS processes are reviewed, with emphasis on the various modes of operation of a standard transistor and their respective merits, and on additional specifications required to apply devices in analog circuits. Some basic compatible analog circuit techniques and their related tradeoffs are then surveyed by means of typical examples. The noisy environment due to cohabitation on the chip with digital circuits is briefly evoked.     

Switch-Level Test-Vector Generation for CMOS Combinational Logic

A method is proposed of test-vector generation for stuck-open and other faults in CMOS combinational circuits represented at the switch level. It consists in solving three problems: (1) Identify a stimulus that should be applied to the element under test. (2) Trace a path through which the response could reach an output node. (3) Find a set of input values that could drive internal nodes to logic levels determined in solving problems (1) and (2). The method is illustrated with an example.     

Feedthrough in emitter-coupled logic circuits

Emitter coupled logic circuits transient noise behavior is examined. The mechanisms and causes of feedthrough are analyzed using, first, approximate expressions and, second, an accurate model. The experimental observations of feedthrough give ample evidence of good agreement between the theoretical and computational results. An accurate appraisal of the causes of feedthrough, such as C/SUB b//SUB e/, C/SUB b//SUB c/, c/SUB i//SUB d/, C/SUB i//SUB t/, C/SUB p/, and C/SUB c//SUB u//SUB s/ determine the main factors that offer scope for improvement.     

对称三进制逻辑CMOS电路的试制

根据有关对称三进制逻辑的资料,结合CMOS电路生产工艺特点,设计并试制了对称三值逻辑CMOS系列电路。其中包括倒相器与非门、或非门、变形反相器和T门共五种基本电路。本文叙述了设计方案,生产工艺及结果讨论。     

开关电流电路中的时钟馈入效应

本文采用ＭＯＳ开关的集总时变ＲＣ模型，对开关电流（ＳＩ）电路中的时钟馈入效应进行了详细的理论分析，导出了开关电流镜中钟馈电压和钟馈电流的表达式，从而揭示出了钟馈电压／电流与工艺参数、ＭＯＳ器件尺寸、时钟信号幅值及其下降沿斜率等之间的内在关系。用它可对ＳＩ电路中时钟馈入的影响进行快速预测。文中的理论分析与ＳＰＩＣＥ仿真结果相一致。所提供的结果对于设计高精度低功耗ＳＩ电路有应用价值。