Investigation of interconnect capacitance characterization usingcharge-based capacitance measurement (CBCM) technique andthree-dimensional simulation

This paper examines the recently introduced charge-based capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure     

采用轴对称二维有限元法提取过孔分布电容

采用简便的两维轴对称有限元法分析了四层印制电路板的过孔电容。将极坐标形式的拉普拉斯方程变换成直角坐标形式,避免了复杂的椭圆积分。将过孔的电容分层处理,分析了过孔的高度、半径、焊盘半径等参数对过孔电容的影响。与有限元分析软件ANSYS进行了对比,计算结果基本一致。此方法可用于任意层复杂印制电路板过孔电容的提取,所得结论有助于过孔的等效电路建模以及高速PCB的信号完整性分析。     

Lumped Capacitance, Open-Circuit End Effects, and Edge-Capacitance of Microstrip-Like Transmission Lines for Microwave and Millimeter-Wave Applications

A detailed analysis of lumped capacitance, open-circuit end effects, and edge-capacitance of finite-length strip conductors embedded in multilayer, isotropic dielectrics without sidewalls is presented. The analysis uses the well-known variational technique, in conjunction with the transverse transmission-line technique. The lumped capacitances of square and rectangular conductor patches in sandwiched microstrip, inverted microstrip, and suspended microstrip are computed. Further, extensive data on the open-circuit end effects and edge-capacitances of finite-length strip conductors in these rnicrostrip-like transmission lines are generated. Using the method presented, the analysis of lumped capacitance, open-circuit end effects, and edge-capacitances of finite-length strip conductors in various microstrip-like structures reduces to the determination of a single admittance parameter. This parameter can be simply obtained from the transmissionline equivalent circuit.     

基于边界元法的二维VLSI版图电容提取

提出了一种用边界元法计算ＶＬＳＩ版图电容的方法，通过求解二维拉普拉斯方程，直接得到版图中各种类型的电容的值。该方法提取数据准确简单，占用内存少，计算效率高，且有较高的精度。用该方法对几种典型的ＶＬＳＩ版图电容进行提取，均取得较好的结果。     

Explicit Analytical Charge and Capacitance Models of Undoped Double-Gate MOSFETs

An analytical, explicit, and continuous-charge model for undoped symmetrical double-gate (DG) MOSFETs is presented. This charge model allows obtaining analytical expressions of all total capacitances. The model is based on a unified-charge-control model derived from Poisson's equation and is valid from below to well above threshold, showing a smooth transition between the different regimes. The drain current, charge, and capacitances are written as continuous explicit functions of the applied bias. We obtained very good agreement between the calculated capacitance characteristics and 2-D numerical device simulations, for different silicon film thicknesses.     

The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.     

An accurate gate length extraction method for sub-quarter micronMOSFET's

By comparing measured and simulated gate-to-source/drain capacitances, C_gds, an accurate gate length extraction method is proposed for sub-quarter micron MOSFET's applications. We show that by including the 2-D field effect on the fringing capacitance, the polysilicon depletion and the quantum-well effects in the C_gds simulation, the polysilicon gate length, L_poly, can be accurately determined for device lengths down to the 0.1 μm regime. The accuracy of this method approaches that of cross-sectional TEM on the device under test, but without destroying the device. Furthermore, we note that as a result of accurate L_poly extraction, the source/drain lateral diffusion length, L_diff , and effective channel length, L_eff, can also be determined precisely. The accuracy of L_diff is confirmed by examining their consistency with experimentally obtained 2-D source/drain profile     

Electrical characterization of ball grid array packages fromS-parameter measurements below 500 MHz

Ball grid array (BGA) packages have been characterized from one port S-parameter measurements by shorting and opening the connection on the ball side of BGA packages. Transmission line parameters (resistance, inductance and capacitance) using the Γ equivalent circuit model are extracted from the measured S₁₁ parameter. Extracted resistances are strongly dependent on frequency, but extracted inductances and capacitances are nearly constant up to 500 MHz. Extracted capacitances are well matched to those measured from an LCR meter and calculated from a three-dimensional (3-D) simulator, Capacitance in a transmission line plays an important role in electrical performance for packages so that we may model a transmission line as a single capacitor. Extracted capacitances using the single capacitor model also well represent the measured S₁₁. These results suggest that the single capacitor model can be efficiently used for the transmission line model in BGA packages up to 500 MHz     

An efficient solver for the three-dimensional capacitance of theinterconnects in high speed digital circuit by the multiresolutionmethod of moments

The computation of the equivalent capacitances for three-dimensional (3-D) interconnects features large memory usage and long computing time. In this paper, a matrix sparsification approach based on multiresolution representation is applied with the method of moments (MoM) to calculate 3-D capacitances of interconnects in a layered media. Instead of direct expansion of the charge distribution by the orthogonal wavelet basis functions, the large full matrix resulting from discretization of the integral equations is taken as a discrete image and sparsified by two-dimensional (2-D) multiresolution representations. The inverse of the obtained sparse matrix is efficiently implemented by Schultz's iterative approach. Several numerical examples are given and the results obtained show that the proposed method significantly sparsifies the matrix equation and the capacitance parameters computed by the matrix equation with high sparsity agree well with the results of other reports and those computed by an established capacitance extractor FASTCAP     

Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation

This paper reports an analysis of the gate-source/drain capacitance behavior of a narrow-channel fully depleted (FD) silicon-on-insulator (SOI) NMOS device considering the three-dimensional (3-D) fringing capacitances. Based on the 3-D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.05 /spl mu/m, the inner-sidewall-oxide fringing capacitance (C/sub FIS/), due to the fringing electric field at the edge of the mesa-isolated structure of the FD SOI NMOS device biased at V/sub G/=0.3 V and V/sub D/=1 V, is the second largest contributor to the gate-source capacitance (C/sub GS/). Thus, when using nanometer CMOS devices with a channel width smaller than 0.1 /spl mu/m, C/sub FIS/ cannot be overlooked for modeling gate-source/drain capacitance (C/sub GS//C/sub GD/).     

The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

The effect of interconnect coupling capacitances on neighboring CMOS logic gates driving coupled interconnections strongly depends upon signal activity. A transient analysis of two capacitively coupled CMOS logic gates is presented in this paper for different combinations of signal activity. The uncertainty of the effective load capacitance and propagation delay due to signal activity is addressed. Analytical expressions characterizing the output voltage and propagation delay are also presented for different signal activity conditions. The propagation delay based on these analytical expressions is within 3% as compared to SPICE, while the estimated delay neglecting the difference between the load capacitances can exceed 45%. The logic gates should be properly sized to balance the load capacitances in order to minimize any uncertainty in the delay and load. The peak noise voltage on a quiet interconnection determined from the analytical expressions is within 4% of SPICE. The peak noise voltage on a quiet interconnection can be minimized if the effective output conductance of the quiet logic gate driving the interconnect is increased.     

Methodology for characterization of high-speed multi-conductor metal interconnections and evaluation of measurement errors

Analysis and design of interconnects in high speed integrated circuits and systems involves models in the form of multiconductor transmission lines. The fundamental parameters of those models are matrices of capacitance, (C), inductance, (L), resistance, (R), and conductance (G). We present a methodology for measurement of entries in capacitance matrix. The entries of capacitance matrices can be calculated using numerical solvers of electrostatic fields established under the assumption of suitable biasing of interconnect structures. Numerical calculations of complete field equations are very complex and expensive in terms of computer time, therefore several approximations are made in constructing interconnect dedicated software packages available on the market. Because of these approximations it is necessary to validate the calculations via measurements. Calculation of the off-diagonal entries of capacitance matrix from measurements of "two-terminal" capacitances is strongly corrupted by the measuring errors. The method involves direct capacitance measurement in multi-conductor structures and provides analysis of accuracy.     

The Capacitances and Surface-Charge Distributions of a Shielded Balanced Pair

The capacitance matrix of a straight pair of uniform wires symmetrically placed in a shield is determined theoretically. Exact expressions for the elements of the capacitance matrix are determined as particular elements of the inverse of an infinite matrix which relates the Fourier coefficients of the surface-charge densities on the inner conductors and the shield to the applied voltage excitations on the cable conductors. If the wire diameter is small relative to the wire separation, and if the wire separation is small relative to the shield diameter, then accurate numerical approximations for the elements of the capacitance matrix are obtained to any degree of accuracy by suitably truncating the infinite matrix. Once the elements of the capacitance matrix are determined, then the distributions of the surface-charge densities on the peripheries of the inner conductors, and the shield are determined for any arbitrary excitation of the cable structure. In particular, the various capacitances associated with the cable structure, e.g., the direct, ground, and mutual capacitances, are determined from a comparison of the surface-charge densities resulting from a "balanced" excitation and a "longitudinal" excitation. The Fourier coefficients of the surface-charge densities are required to determine the propagation parameters and the associated propagation modes of the cable structure. The surface-charge distributions are evaluated numerically for a typical standard production cable using 22-gauge wires. The results of this paper will be extended by a perturbational method to include twisted wires in a shield; also, certain types of asymmetries in the cable geometry will be considered. Hence, the propagation constants and the associated propagation modes of unbalanced and/or twisted shielded pair cables can also be determined.     

Hot-carrier-induced alterations of MOSFET capacitances: aquantitative monitor for electrical degradation

In this paper, combined gate-to-channel (C_GSD) and gate-to-bulk (C_GB) capacitance measurements are used in order to extract quantitative information about hot-carrier degradation in MOS transistors. An analytical model, explaining the results of accelerated degradation experiments, is presented to establish a simple relationship between C_GSD and C_GB changes and the stress-induced charges Q_ox and Q_it trapped in the oxide or in interface states, respectively. A method, validated by means of two-dimensional (2-D) numerical simulations, is proposed to determine Q_ox and Q_it directly from the measured capacitances, and is applied to experimental data. The new technique considerably improves the capabilities of previous capacitive methods because it can yield a quantitative determination of Q_ox and Q_it     

Analysis of on-chip spiral inductors using the distributed capacitance model

In this paper, a distributed capacitance model (DCM) for monolithic spiral inductors is developed to predict the equivalent coupling capacitances C/sub p/ between the two terminals and the equivalent capacitance between the metal track and the substrate C/sub sub/. Therefore, the characteristics of inductors such as the S parameter, the quality factor Q, and the self-resonant frequency f/sub SR/ can be predicted by its series inductance, equivalent capacitances, and series resistance. A large number of inductors have been implemented in 0.25- and 0.35-/spl mu/m CMOS processes to demonstrate the prediction accuracy. For planar and multilayer inductors, DCM can provide a quick and accurate assessment to the design of monolithic spiral inductors.     

Calculation of distributed capacitances of spiral resonators

A method for calculating the distributed capacitances and resonant frequencies of spiral resonators is described. First, the charge distribution on a spiral is found by a simplified model and the moment method, then the distributed capacitance is calculated. The equivalent inductance of the spiral resonator is then evaluated according to a standard formula, and the resonant frequencies are finally computed. The calculated results are compared with experimental data, and a good agreement between them is shown     

Analysis of nearly cylindrical antennas and scattering problemsusing a spectrum of two-dimensional solutions

This paper presents a powerful method for analysing antennas which can be considered principally two-dimensional (2-D) or cylindrical, except for some three-dimensional (3-D) physical or equivalent sources, e.g., dipoles or slots. It is shown by Fourier transform techniques that such antennas can be analyzed as 2-D problems with harmonic longitudinal field variation. The radiation pattern can often be determined directly from a finite set of such 2-D solutions, each one obtained by any method, e.g., the moment method. The mutual interaction between the cylindrical scatterer and the sources must be calculated to determine the exact current distribution on the sources and their impedances or admittances. This is facilitated by performing an inverse Fourier transform of an infinite spectrum of the numerical 2-D solutions followed by a moment method solution in the spatial domain to satisfy the boundary conditions on the 3-D equivalent sources themselves. The inverse Fourier transform is simplified by the use of asymptote extraction. The method is in itself a hybrid technique as one method is used to solve the harmonic 2-D problem, and the other to solve for the source currents     

A novel capacitive micro-accelerometer with grid strip capacitances and sensing gap alterable capacitances

The comb capacitances fabricated by deep reactive ion etching (RIE) process have high aspect ratio which is usually smaller than 30 : 1 for the complicated process factors, and the combs are usually not parallel due to the well-known micro-loading effect and other process factors, which restricts the increase of the seismic mass by increasing the thickness of comb to reduce the thermal mechanical noise and the decrease of the gap of the comb capacitances for increasing the sensitive capacitance to reduce the electrical noise. Aiming at the disadvantage of the deep RIE, a novel capacitive micro-accelerometer with grid strip capacitances and sensing gap alterable capacitances is developed. One part of sensing of inertial signal of the micro-accelerometer is by the grid strip capacitances whose overlapping area is variable and which do not have the non-parallel plate's effect caused by the deep RIE process. Another part is by the sensing gap alterable capacitances whose gap between combs can be reduced by the actuators. The designed initial gap of the alterable comb capacitances is relatively large to depress the effect of the maximum aspect ratio (30 : 1) of deep RIE process. The initial gap of the capacitance of the actuator is smaller than the one of the comb capacitances. The difference between the two gaps is the initial gap of the sensitive capacitor. The designed structure depresses greatly the requirement of deep RIE process. The effects of non-parallel combs on the accelerometer are also analyzed. The characteristics of the micro-accelerometer are discussed by field emission microscopy (FEM) tool ANSYS. The tested devices based on slide-film damping effect are fabricated, and the tested quality factor is 514, which shows that grid strip capacitance design can partly improve the resolution and also prove the feasibility of the designed silicon-glass anodically bonding process.     

Microwave noise modeling for InP-InGaAs HBTs

Analytical expressions for the noise parameters of microwave InP double heterojunction bipolar transistors (DHBTs) are presented in this paper. These expressions are derived from an accurate small-signal and noise equivalent-circuit model, which takes into account the influences of the base-collector capacitance and the base resistance distributed nature. Pad capacitances and series inductances are also included. Further simplified expressions for noise parameters in the low-frequency range are given. Good agreement is obtained between measured and calculated results up to 20 GHz for InP-InGaAs DHBTs with a 5/spl times/5 /spl mu/m/sup 2/ emitter area over a wide range of bias points.