Simulation of slow current transients and current collapse in GaN FETs

Two-dimensional transient simulations of GaN MESFETs are performed in which a three-level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are considered. When the drain voltage V _D is raised abruptly (while keeping the gate voltage V _G constant), the drain current I _D overshoots the steady-state value, and when V _D is lowered abruptly, I _D remains a low value for some periods, showing drain-lag behavior. These are explained by the deep donor’s electron capturing and electron emission processes. We also calculate a case when both V _D and V _G are changed abruptly from an off point, and quasi-pulsed I-V curves are derived from the transient characteristics. It is shown that the drain currents in the pulsed I-V curves are rather lower than those in the steady state, indicating that so-called current collapse could occur due to deep levels in the semi-insulating buffer layer. It is also shown that the current collapse is more pronounced when V _D is lowered from a higher voltage during turn-on, because the trapping effects become more significant.     

Simulation of Lag Phenomena and Pulsed I-V Curves of Compound Semiconductor FETs as Affected by Impact Ionization

Turn-on characteristics of GaAs MESFETs are simulated when the gate and the drain voltages are changed abruptly, and quasi-pulsed I-V curves are derived from them. It is discussed how the slow current transients (lag phenomena) and the pulsed I-V curves are affected by the existence of substrate traps and surface states. It is also discussed how the characteristics are influenced by impact ionization of carriers.     

Physical investigation of trap-related effects in power HFETs and their reliability implications

This paper presents a detailed physical investigation of trapping effects in GaAs power HFETs. Two-dimensional numerical simulations, performed using a hydrodynamic model that includes impact ionization, are compared with experimental results of fresh as well as hot-carrier-stressed HFETs in order to gain insight of intertwined phenomena such as the kink in the dc output curves, the hot-carrier degradation of the drain current, and the impact-ionization-dominated reverse gate current. Thoroughly consistent results show that: 1) the kink effect is dominated by the traps at the source-gate recess surface; and 2) as far as the hot-carrier degradation is concerned, only a simultaneous increase of the trap density at the drain-gate recess surface and at the channel-buffer interface (again at the drain side of the channel) is able to account for the simultaneous decrease of the drain current and the increase of the impact-ionization-dominated reverse gate current.     

Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling

Drain current multiplication in vertical MOSFETs due to body isolation by the drain depletion region and gate–gate charge coupling is investigated at pillar thicknesses in the range of 200–10 nm. For pillar thickness >120 nm depletion isolation does not occur and hence the body contact is found to be completely effective with no multiplication in drain current, whereas for pillar thicknesses <60 nm depletion isolation occurs for all drain biases and hence the body contact is ineffective. For intermediate pillar thicknesses of 60–120 nm, even though depletion isolation is apparent, the body contact is still effective in improving floating body effects and breakdown. At these intermediate pillar thicknesses, a kink is also observed in the output characteristics due to partial depletion isolation. The charging kink and the breakdown behavior are characterized as a function of pillar thickness, and a transition in the transistor behavior is seen at a pillar thickness of 60 nm. For pillar thickness greater than 60 nm, the voltage at which body charging occurs decreases (and the normalized breakdown current increases) with decreasing pillar thickness, whereas for pillar thickness less than 60 nm, the opposite trend is seen. The relative contributions to the drain current of depletion isolation and the inherent gate–gate charge coupling are quantified. For pillar thickness between 120 and 80 nm, the rise in the drain current is found to be mainly due to depletion isolation, whereas for pillar thicknesses <60 nm, the increase in the drain current is found to be governed by the inherent gate–gate charge coupling.     

1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps

Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO₂ interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO₂ interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.     

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

Bipolar Charge Trapping Induced Anomalous Negative Bias-Temperature Instability in HfSiON Gate Dielectric pMOSFETs

Negative bias-temperature (NBT) stress-induced drain current instability in a pMOSFET with a gate stack is investigated by using a fast transient measurement technique. We find that in certain stress conditions, the NBT-induced current instability evolves from enhancement mode to degradation mode, giving rise to an anomalous turn-around characteristic with stress time and stress gate voltage. Persistent poststress drain current degradation is found in a pMOSFET, as opposed to drain current recovery in its n-type MOSFET counterpart. A bipolar charge trapping model along with trap generation in a HfSiON gate dielectric is proposed to account for the observed phenomena. Poststress single charge emissions from trap states in HfSiON are characterized. Charge pumping and carrier separation measurements are performed to support our model. The impact of NBT stress voltage, temperature, and time on drain current instability mode is evaluated.     

A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs

A tunneling probability-based drain current model for tunnel field-effect transistors (FETs) is presented. First, an analytical model for the surface potential and the potential at the channel–buried oxide interface is derived for a Gate-on-Source/Channel silicon on insulator (SOI)-tunnel FET (TFET), considering the effect of the back-gate voltage. Next, a drain current model is derived for the same device by using the tunneling probability at the source–channel junction. The proposed model includes physical parameters such as the gate oxide thickness, buried oxide thickness, channel thickness, and front-gate oxide dielectric constant. The proposed model is used to investigate the effects of variation of the front-gate voltage, drain voltage, back-gate voltage, and front-gate dielectric thickness. Moreover, a threshold voltage model is developed and the drain-induced barrier lowering (DIBL) is calculated for the proposed device. The effect of bandgap narrowing is considered in the model. The model is validated by comparison with Technology Computer-Aided Design (TCAD) simulation results.     

A physically based,accurate compact model of direct tunneling gate current considering quantum mechanical effects in nanoscale metal‐oxide‐semiconductor field‐effect transistors

We present a physically based, accurate model of the direct tunneling gate current of nanoscale metal‐oxide‐semiconductor field‐effect transistors considering quantum mechanical effects. Effect of wave function penetration into the gate dielectric is also incorporated. When electrons tunnel from the metal oxide semiconductor inversion layer to the gate, the eigenenergies of the quasi‐bound states turn out to be complex quantities. The imaginary part of these complex eigenenergies, Γ_ij, are required to estimate the finite lifetimes of these states. We present an empirical equation of Γ_ij as a function of surface potential. Inversion layer electron concentration is determined using eigenenergies, calculated by modified Airy function approximation. Hence, a compact model of direct tunneling gate current is proposed using a novel approach. Good agreement of the proposed compact model with self‐consistent numerical simulator and published experimental data for a wide range of substrate doping densities and oxide thicknesses states the accuracy and robustness of the proposed model. The proposed model can well be extended for devices with high‐κ/stack gate dielectrics introducing necessary modifications. Copyright © 2011 John Wiley & Sons, Ltd.     

Two-dimensional analytical model of threshold voltage and drain current of a double-halo gate-stacked triple-material double-gate MOSFET

We have developed a two-dimensional analytical model for the channel potential, threshold voltage, and drain-to-source current of a symmetric double-halo gate-stacked triple-material double-gate metal–oxide–semiconductor field-effect transistor (MOSFET). The two-dimensional Poisson’s equation is solved to obtain the channel potential. For accurate modeling of the device, fringing capacitance and effective surface charge are considered. The basic drift–diffusion equation is used to model the drain-to-source current. The midchannel potential of the device is used instead of the surface potential in the current modeling, considering the fact that the punch-through current is not confined only to the surface in a fully depleted MOSFET. An expression for the pinch-off voltage is derived to model the drain current in the saturation region accurately. Various short-channel effects such as drain-induced barrier lowering, gate leakage, threshold voltage, and roll-off have also been investigated. This structure shows excellent ability to suppress various short-channel effects. The results of the proposed model are validated against data obtained from a commercially available numerical device simulator.     

Collapse of MOSFET drain current after soft breakdown

Gate-oxide soft breakdown (SB) can have a severe impact on MOSFET performance even when not producing any large increase of the gate leakage current. The SB effect on the MOSFET characteristics strongly depends on the channel width W: drain saturation current and MOSFET transconductance dramatically drop in transistors with small W after SB. As W increases, the SB effect on the drain current fades. The drain saturation current and transconductance collapse is due to the formation of an oxide defective region around the SB spot, whose area is much larger than the SB conductive path. Similar degradation can be observed even in heavy ion irradiated MOSFETs where localized damaged oxide regions are generated by the impinging ions without producing any increase of gate leakage current.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications

Vertically stacked dielectric separated independently controlled gates can be used to realize dual-threshold voltage on a single silicon channel MOS device. This approach significantly reduces the effective layout area and is similar to merging two transistors in series. This multiple independent gate device enables the design of new class of compact logic gates with low power and reduced area. In this paper, we present the junctionless concept based twin gate transistor for digital applications. To analyse the appropriate behaviour of device, this paper presents the modeling, simulation and digital overview of novel gate-all-around junctionless nanowire twin-gate transistor for advanced ultra large scale integration technology. This low power single MOS device gives the full functionality of “AND” gate and can be extended to full functionality of 2-input digital “NAND” gate. To predict accurate behaviour, a physics based analytical drain current model has been developed which also includes the impact of gate depleted source/drain regions. The developed model is verified using ATLAS 3D device simulator. This single channel device can function as “NAND” gate even at low operating voltage.     

FERROELECTRIC GATE FET MEMORY BASED ON CONDUCTION OF FERROELECTRIC-INSULATOR INTERFACE

ABSTRACT

A new type of ferroelectric gate field effect transistor (FET) using ferroelectric-insulator interface conduction has been proposed. Drain current flows along the interface between ferroelectric and insulator layers and needs no semiconductor. This FET consists of source and drain electrodes on ferroelectric film (Pb(Zr_0.52Ti_0.48)O₃(PZT)) prepared on Pt/TiO₂/SiO₂/Si substrate, and gate electrode on HfO₂ insulator film on the PZT film between the source and the drain electrodes. Drain current flows through the interface of the ferroelectric and the insulator. Drain current versus gate voltage characteristics shows clockwise hysteresis loop similarly to the conventional p-channel FET with ferroelectric gate. The FET shows that the On/Off ratio of the conduction current is about 10⁵ and the Off state current is about 10^{? 10}A.     

MOSFET开关过程的研究及米勒平台振荡的抑制

设计功率MOSFET驱动电路时需重点考虑寄生参数对电路的影响。米勒电容作为MOSFET器件的一项重要参数,在驱动电路的设计时需要重点关注。重点观察了MOSFET的开通和关断过程中栅极电压、漏源极电压和漏源极电流的变化过程,并分析了米勒电容、寄生电感等寄生参数对漏源极电压和漏源极电流的影响。分析了栅极电压在米勒平台附近产生振荡的原因,并提出了抑制措施,对功率MOSFET的驱动设计具有一定的指导意义。     

Thermally-stimulated current and dielectric loss measurement ofpolypropylene and Teflon-FEP films immersed in diarylethane

Some properties of oil/PP (biaxially stretched polypropylene) and oil/FEP (Teflon FEP) composite insulators have been investigated with TSC (thermally stimulated current) techniques. The oil/PP system showed three TSC peaks originating from carriers captured in the swollen surface region of the PP. The TSC spectra depended strongly on the polarity of the poling voltage and on the impregnating temperature. Their analysis yielded information on the carrier traps existing near the PP surface in the oil/PP interface region. On the other hand, the TSC spectrum of the oil/FEP system has a small impregnating temperature dependence and a small effect of the poling voltage polarity. The difference in TSC between oil/PP and oil/FEP systems is closely related to the difference in the oil-polymer interaction. The TSC is a useful method for investigating carrier traps in the surface region and their change due to the oil-polymer interaction. To investigate further the relation between the carrier traps and tanδ, collecting bias TSC was measured on a specimen to which an ac voltage was applied. The results indicate that the decrease in tanδ during the ac voltage application depends on the amount of trapped carriers near the polymer's surface or, the decrease in carriers in the oil     

PIMOD processing and properties of a LiNbO3-based MFSFET for nonvolatile memories

Abstract

The photo-induced metallo-organic decomposition (PIMOD) process has been successfully used to deposit a lithium niobate thin film acting as the gate oxide of the conventional MFSFET structure. The use of the low-temperature PIMOD process for thin film deposition has increased the device yields of the molybdenum liftoff for small area isolation. The electronic alteration of the properties of the ferroelectric gate transistor was previously shown to be caused by charges in the semiconductor being injected into the ferroelectric film. To prevent this problem, a thin SiO₂ buffer layer was thermally grown on the silicon substrate immediately before lithium niobate deposition. The silicon-lithium niobate interface was stabilized and the charge injection effect was eliminated due to the formation of the buffer layer. The channel current was shown to be greatly altered by the application of voltage pulses between the gate of the device and the substrate. Upon switching, the change in surface conductivity of the semiconductor was the same as that expected for ferroelectric switching.