Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.     

湿热环境下倒装焊无铅焊点的可靠性

对板上倒装芯片底充胶进行吸湿实验,并结合有限元分析软件研究了底充胶在湿敏感元件实验标准MSL—1条件下吸湿和热循环阶段的解吸附过程,测定了湿热环境对Sn3.8Ag0.7Cu焊料焊点可靠性的影响,并用蠕变变形预测了无铅焊点的疲劳寿命。结果表明:在湿热环境下,底充胶材料内部残留的湿气提高了焊点的应力水平。当分别采用累积蠕变应变和累积蠕变应变能量密度寿命预测模型时,无铅焊点的寿命只有1740和1866次循环周期。     

Thermal cycling lifetime of flip chip on board circuits with solder bumps and isotropically conductive adhesive joints

Flip chip on board (FCOB) circuits with solder bumps or isotropically conductive adhesives (ICA) may be subject to joint failure during thermal cycling. Although use of epoxy underfill can increase the lifetime significantly, there is still a risk of failure if the material properties of the underfill material are not adequate to prevent excessive values of stress and strain in the joints. This paper presents experimental measurements of the number of thermal cycles to failure for both solder reflow and ICA joint FCOB circuits. Measurements have been carried out for several different material systems with various types of underfill. The measurements of solder bump lifetime are compared to a lifetime model based on analytical calculations of solder strain. For an underfill type without filler (CTE=58 ppm//spl deg/C), the measurements are in excellent agreement with the model predictions, both giving an average lifetime of around 1500 thermal cycles between -55 and 125/spl deg/C. For two filled types of underfill with CTE nearly matched to that of solder, the measured average lifetimes vary from around 2700 to 5500 cycles. The corresponding model predictions are around 6000 and 7000 cycles, respectively. Measurements of the lifetime of FCOB's with ICA connections have been carried out for two different material systems. The obtained lifetimes vary between approximately 500 and 4000 cycles. No systematic lifetime variation with the thermal expansion of the underfill has been observed, but the lifetime seems to be dependent on the properties of the bump on the chip pad. Delamination, for instance at the ICA/bump interface, is found to be an important cause of failure.     

固化残余应力对倒装焊器件热–机械可靠性的影响

采用底充胶的与固化过程相关的粘弹性力学模型,通过有限元仿真的方法,模拟了底充胶的整个固化过程,计算出了热循环加载下硅片、底充胶/硅片界面、底充胶内部的应力分布及其幅值大小.结果表明:底充胶的固化过程及由此产生的固化残余应力不但使得硅片中的最大垂直开裂应力位置偏离中心线达1.6 mm之多,而且还劣化了热循环加载下底充胶中应力幅值约6.25%.最后得出了固化残余应力对倒装焊器件热–机械可靠性的影响是不可忽略的结论.     

固化残余应力对倒装焊器件热-机械可靠性的影响

采用底充胶的与固化过程相关的粘弹性力学模型,通过有限元仿真的方法,模拟了底充胶的整个固化过程,计算出了热循环加载下硅片、底充胶/硅片界面、底充胶内部的应力分布及其幅值大小。结果表明:底充胶的固化过程及由此产生的固化残余应力不但使得硅片中的最大垂直开裂应力位置偏离中心线达1.6 mm之多,而且还劣化了热循环加载下底充胶中应力幅值约6.25%。最后得出了固化残余应力对倒装焊器件热–机械可靠性的影响是不可忽略的结论。     

Die stress characterization in flip chip on laminate assemblies

Minimizing device side die stresses is especially important when multiple copper/low-k interconnect redistribution layers are present. Mechanical stress distributions in packaged silicon die resulting during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, measurements of thermally induced stresses in flip chip on laminate assemblies are presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from -40 to +150/spl deg/C. Using these measurements and ongoing numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.     

Guidelines to select underfills for flip chip on board assemblies and compliant interposers for chip scale package assemblies

The effect of thermomechanical properties of underfill and compliant interposer materials, such as coefficient of thermal expansion (CTE) and stiffness (Young's modulus) on reliability of flip chip on board (FCOB) and chip scale packages (CSPs) under thermal cycling stresses is investigated in this study. Quasi-three-dimensional viscoplastic stress analysis using finite element modeling (FEM) is combined with an energy partitioning (EP) model for creep-fatigue damage accumulation to predict the fatigue durability for a given thermal cycle. Parametric FEM simulations are performed for five different CTEs and five different stiffnesses of the underfill and compliant interposer materials. The creep work dissipation due to thermal cycling is estimated with quasi 3-D model, while 3-D model is used to estimate the hydrostatic stresses. To minimize the computational effort, the 3-D analysis is conducted only for the extreme values of the two parameters (CTE and stiffness) and the results are interpolated for intermediate values. The results show that the stiffness of the underfill material as well as the CTE play important role in influencing the fatigue life of FCOB assemblies. The fatigue durability increases as underfill stiffness and CTE increase. In the case of compliant interposers, the reverse is true and durability increases as interposer stiffness decreases. Furthermore, the interposer CTE affects the fatigue durability more significantly than underfill CTE, with durability increasing as CTE decreases. The eventual goal is to define the optimum design parameters of the FCOB underfill and CSP interposer, in order to maximize the fatigue endurance of the solder joints under cyclic thermal loading environments.     

A novel flip chip technology using nonconductive resin sheet

The process flow of this new packaging system is as follows. First, epoxy base resin sheet is laminated onto substrate to cover the substrate surface including land electrodes. Bumped chip alignment and attachment was done through the resin sheet, in the second stage with pressure and temperature. The bumps under the chip penetrate with removal of resin sheet material eventually reaching to the metal land of the substrate in this process. Metal connection and curing of the interface resin have been completed in the third stage. This new process has the potential to make flip chip packages simple compared with the current process using liquid resin with dispensing system. The throughput time can be reduced to less than 10 s/unit in actual model case even for large flip chip package which has over 15×15 (mm) square area IC chips. The other advantages are thermal stability of material in the process, moisture related performance, and warpage control performance. For current underfill process the only choice is to use anhydride type resin system which has many disadvantages. This new process made it possible to introduce moisture and thermally stable epoxy resin with phenol curing system for flip chip packaging. Drastic process ability improvement can be achieved by the new process and material. As a typical improvement of thermal shock performance, it was confirmed that the life of chip damage is over 10 times longer by flip chip bonding parameters which can be controlled only by this new flip chip packaging process     

Interfacial behavior of a flip-chip structure under thermal testing

In this paper, the interfacial behavior of a flip-chip structure under thermal testing was investigated using high sensitivity, real-time Moire interferometry. The model package studied was a sandwich structure consisting of a silicon chip, epoxy underfill and FR4 substrate. The behavior of FR4-underfill and silicon-underfill interfaces of the specimen under certain thermal loading was examined. The results show that the shear strain variation increases significantly along the interfaces, with the maximum shear strain concentration occurring at the edge of the specimen. At the edge, the maximum shear strain occurs at the silicon-underfill interface, and the FR4-underfill interface experiences a slightly lower shear strain. The creep effect is more dominant in the FR4-underfill interface when the specimen is heated for 2 h at 100/spl deg/C. Upon cooling to 20/spl deg/C, both the interfaces of the specimen experience partial strain recovery.     

Dependence of Flip Chip Solder Reliability on Filler Settling

Thermomechanical reliability of solder joints in flip-chip packages is usually analyzed by assuming a homogeneous underfill ignoring the settling of filler particles. However, filler settling does impact flip chip reliability. This paper reports a numerical study of the influence of filler settling on the fatigue estimation of flip-chip solder joints. In total, nine underfill materials ( 35 vol% silica filler in three epoxies with three filler settling profiles for each epoxy) are individually introduced in a 2-D finite element (FE) model to compare the thermal response of flip chip solder joints that are surrounded by the underfill. The results show that the fatigue indicators for the solder joints (inelastic shear strain increments and inelastic shear strain energy density) corresponding to a gradual, nonuniform filler profile studied in this paper can be smaller than those associated with the uniform filler profile, suggesting that certain gradual filler settling profiles in conjunction with certain resin grades may favor a longer solder fatigue lifetime. The origin of this intriguing observation is in the fact that the solder fatigue indicators are a function of the thermal mismatch among the die, substrate, solder, and underfill materials. The thermal mechanics interplayed among these materials along with a gradual filler profile may allow for minimizing thermal mismatch; and thus lead to lower fatigue indicators.      

Characterization of lead-free solders and under bump metallurgies for flip-chip package

A variety of Pb-free solders and under bump metallurgies (UBMs) was investigated for flip chip packaging applications. The result shows that the Sn-0.7Cu eutectic alloy has the best fatigue life and it possess the most desirable failure mechanism in both thermal and isothermal mechanical tests regardless of UBM type. Although the electroless Ni-P UBM has a much slower reaction rate with solders than the Cu UBM, room temperature mechanical fatigue is worse than on the Cu UBM when coupled with either Sn-3.8Ag-0.7Cu or Sn-3.5Ag solder. The Sn-37Pb solder consumes less Cu UBM than all other Pb-free solders during reflow. However, Sn-37Pb consumes more Cu after solid state annealing. Studies on aging, tensile, and shear mechanical properties show that the Sn-0.7Cu alloy is the most favorable Pb-free solder for flip chip applications. When coupled with underfill encapsulation in a direct chip attach (DCA) test device, the Sn-0.7Cu bump with Cu UBM exhibits a characteristic life or 5322 cycles under -55/spl deg/C/+150/spl deg/C air-to-air thermal cycling condition.     

The effects of underfill on the reliability of flip chip solder joints

Thermal fatigue damage of flip chip solder joints is a serious reliability concern, although it usually remains tolerable with the flip chip connections (of smaller chips) to ceramic boards as practiced by IBM for over a quarter century. However, the recent trend in microelectronics packaging towards bonding large chips or ceramic modules to organic boards means a larger differential thermal expansion mismatch between the board and the chip or ceramic module. To reduce the thermal stresses and strains at solder joints, a polymer underfill is customarily added to fill the cavity between the chip or module and the organic board. This procedure has typically at least resulted in an increase of the thermal fatigue life by a factor of 10, as compared to the non-underfilled case. In this contribution, we first discuss the effects of the underfill to reduce solder joint stresses and strains, as well as underfill effects on fatigue crack propagation based on a finite element analysis. Secondly, we probe the question of the importance of the effects of underfill defects, particularly that of its delamination from the chip side, on the effectiveness of the underfill to increase thermal fatigue life. Finally, we review recent experimental evidence from thermal cycling of actual flip chip modules which appears to support the predictions of our model.     

Exothermic reaction induced eutectic Pb-Sn solder ball melting in the underfill curing process

The effects of exothermic heat generated during underfill curing on the integrity of the solder bumped package, which is an important issue for the package reliability, have been overlooked. In this study, theoretical exotherm of underfill materials during underfill curing has been calculated using a differential scanning calorimeter (DSC) at cure temperature range from 100/spl deg/C to 200/spl deg/C. The calculated exotherm was compared with the exotherm profile measured at the typical cure temperature. The effects of cure temperature, amount of underfill, and initial underfill curing temperature on the exotherm profile of underfill materials have been investigated.     

Parametric study on flip chip package with lead-free solder joints by using the probabilistic designing approach

The low cost tin–lead solders have been widely used in electronic industries for many years, but it is also well known to be one of the major factors for environmental pollution risk. Today, several kinds of lead-free soldered alloy have been developed as a choice for replacement of the high lead solders. However, because of the shortage of the facilitated experiment data for the thermal mechanical kinetics characterisations of these alloy, only very few parts of the parametric influence on reliability of the lead-free soldered flip chip package have been realized. In order to launch a further investigation on this issue, a numerical simulation-based parametric study on a flip chip is implemented in this paper by using the probabilistic designing approach. It combines the response surface strategy and the Monte Carlo random simulation method. The peak values of the inelastic strain and hydrostatic stress in solder joints, as well as the peel stress and the shear stress in the interface between silicon and underfill are investigated and used as response parameters. The response surface approximate functions between the output stress/strain values and the major packaging parameters are produced in the design of experiment (DOE) procedure of the numerical simulations. Statistical results of the parametric influence on lead-free soldered flip chip are also acquired by the Monte Carlo random simulation process. The results of our studies have shown that the different packaging parameters will influence the output stress/strain state of the lead-free soldered flip chip package in a very different way and degree. It is indicated that the substrate thickness is a major factor that should be taken into account for the lead-free package optimization design.     

Mechanical loading of flip chip joints before underfill: the impact on yield and reliability

The underfill-facilitated migration from ceramic to lower cost laminate substrates has become a powerful enabler of direct chip attach by offering lower cost, greater electrical functionality, and a smaller system footprint over comparable packaging technologies. Once underfilled, flip chip on laminate has proven extremely reliable even in severe automotive environments. However, between the process steps of reflow and underfill cure, unprotected flip chip solder joints assembled to laminate boards are susceptible to damage and breakage if mishandled. Here, the survivability and long-term reliability of flip chip joints was studied over a range of applied strains. Mechanical loading of joints was applied via beam deflections of populated, but nonunderfilled, laminate boards. Electrical continuity was monitored before and after testing to determine when the load applied to the flip chip exceeded the joint fracture strength. The propensity for solder joint fracture was then calculated as a function of solder bump size and also as a function of strain rate. Analysis of the mechanical properties of solder revealed assembly strategies which reduce bump damage and eliminate yield loss during the process steps leading up to underfill cure. Both strained and unstrained units were then underfilled and cycled between −50 and +150 °C. While mechanical damage was evident in bump cross-sections of strained flip chip assemblies, the fatigue lives of underfilled solder joints were found to be independent of the size of mechanical loads applied before underfill.     

Development of reworkable underfill from hybrid composite of freeradical polymerization system and epoxy resin

The application of the underfill encapsulant is to enhance the solder joint fatigue life in the flip chip assembly, typically up to an order of magnitude, as compared to the nonunderfilled devices. Most of the current underfills, however, are primarily thermosetting epoxy resin curing system based materials, which transform into an infusible three dimensional network structure, and exhibit appreciable adhesion and reliability, but lack of desirable reworkability after curing. From the standpoint of polymeric material chemistry, other thermoplastic or thermosetting polymer materials could be of great economic/cost interest as encapsulants for some microelectronic packaging applications. In this paper, the experimental focus was devoted to the study of adhesion, reliability and reworkability of the free radical polymerization (FRP) system, as well as its hybrid composites or blends with phenoxy resin or epoxy resin (EPR), which could be potential underfill materials. The study encompassed formulation screening based on adhesion measurement, and assessment on reliability and reworkability performance for selected compositions developed so far     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

Correlation of flip chip underfill process parameters and materialproperties with in-process stress generation

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing     

Rotational solder self-alignment mechanics modeling for a flip chip in the presence of a viscous fluid

Advent of 2.5/3Dimensional (2.5/3D) integration using through-silicon vias (TSVs) enables the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies but the new package configuration poses technical challenges in package assembly process. To pace industry demands, a new alternative, Thermal Compression Bonding (TCB), to the conventional Flip Chip on Board (FCOB) process has been being developed for the 3D stacking. Among process materials, epoxy flux (or no-flow underfill) draws high attention again due to its technical advantages in both TCB and mass reflow process. The conventional mass reflow with epoxy flux could provide outstanding benefits to 2.5D package assembly process. The new Low Cost High Throughput Flip Chip Assembly process is one such process requiring fewer processing steps, lower cycle times, and lower cost. In this new process, underfill is dispensed prior to chip placement, and solder reflow and underfill cure occur simultaneously. This reduces the cycle time required for manufacture; however, the presence of a viscous underfill affects the chips' capacity for self-alignment. In a companion study, self-alignment for a flip chip undergoing rectilinear translation was analyzed. This paper applies an equivalent analysis process to a flip chip undergoing rotation in the presence of a viscous underfill. Details of the modeling process are presented along with parametric studies and contrasted against pure translation case. Conditions and process parameters which are more conducive to realignment and those hampering realignment are presented.     

Yield analysis and process modeling of low cost, high throughputflip chip assembly based on no-flow underfill materials

As a concept to achieve low-cost, high-throughput flip chip on board (FCOB) assembly, a new process has been developed implementing next generation flip chip processing based no-flow fluxing underfill materials. The low-cost, high throughput flip chip process implements large area underfill printing, integrated chip placement and underfill flow and simultaneous solder interconnect reflow and underfill cure. The goals of this study are to demonstrate feasibility of no flow underfill materials and the high throughput flip chip process over a range of flip chip configurations, identify the critical process variables affecting yield, analyze the yield of the high throughput flip chip process, and determine the impact of no-flow underfill materials on key process elements. Reported in this work is the assembly of a series of test vehicles to assess process yield and process defects. The test vehicles are assembled by depositing a controlled mass of underfill material on the chip site, aligning chip to the substrate pads, and placing the chip inducing a compression type underfill flow. The assemblies are reflowed in a commercial reflow furnace in an air atmosphere to simultaneously form the solder interconnects and cure the underfill. A series of designed experiments identify the critical process variables including underfill mass, reflow profile, placement velocity, placement force, and underfill material system. Of particular interest is the fact that the no-flow underfill materials studied exhibit an affinity for unique reflow profiles to minimize process defects