Self-aligned complementary bipolar transistors fabricated with a selective-oxidation mask

This paper deals with a self-aligned complementary transistor (vertical n-p-n and vertical p-n-p) structure that is ideal for high-speed and high-accuracy analog bipolar LSI circuits. The device structure consists of a 2-µm epitaxial layer, a non-LOCOS trench isolation buried with polysilicon, and complementary transistors, which are characterized by self-aligned active base and emitter. The key feature lies in the fabrication process, which forms an active base and emitter by ion implantations through a silicon nitride film by the use of an oxidation film that covers an extrinsic base as a mask [1]. The leakage current at the emitter-base junction can be minimized, because the ion-implantation-induced residual defects are confined in the emitter and the extrinsic base regions. The current gains of both transistors (n-p-n and p-n-p) remain constant down to a collector current of Ic= 10^-9A. The typical distribution of the base-emitter offsets (ΔVBE) of transistor pairs was 0.2 mV as expressed in the standard deviation = 3σ. The maximum values of fTfor n-p-n and p-n-p transistors are 6 and 1.5 GHz, respectively.     

Identification of a corner tunneling current component in advancedCMOS-compatible bipolar transistors

A corner tunneling current component in the reverse-biased emitter-base junction of advanced CMOS compatible polysilicon self-aligned bipolar transistors has been identified by measuring base current as a function of temperature, bias voltage, and emitter shape. This current is found to be an excess tunneling current caused by an increase in defect density in the corners of the emitter and gives rise to three-dimensional effects in small-geometry devices. The devices used for this study were selected from batches aimed at optimizing the emitter-base system. For this reason, the starting material was n-type (~10¹⁶ cm^-3) and provided the collector regions of the transistors. The intrinsic base and lightly doped extrinsic base regions were both implanted at 30 keV to a dose of 1×10¹³ cm^-2. The activation anneal was performed at 1060°C for 20 s in a rapid thermal annealer. Under such conditions, the emitter-base junction is located about 600 Å below the polysilicon-substrate interface     

High-low polysilicon-emitter SiGe-base bipolar transistors

Self-aligned heterojunction bipolar transistors with a high-low emitter profile consisting of a heavily doped polysilicon contact on top of a thin epitaxial emitter cap have been fabricated. The low doping in the single-crystal emitter cap allows a very high dopant concentration in the base with low emitter-base reverse leakage and low emitter-base capacitance. The thin emitter cap is contacted by heavily doped polysilicon to reduce the emitter resistance, the base current, and the emitter charge storage. A trapezoidal germanium profile in the base ensures a small base transit time and adequate current gain despite high base doping. The performance potential of this structure was simulated and demonstrated experimentally in transistors with near-ideal characteristics, very small reverse emitter-base leakage current, and 52-GHz peak f_max, and in unloaded ECL and NTL ring oscillators with 24- and 19-ps gate delays, respectively     

Avalanche-induced 1/f noise in bipolar transistors

It has been proposed that degradation of low current hFE, as a result of avalanching the emitter-base junction of a bipolar transistor, can be attributed to an increase in surface recombination velocity within the emitter-base space-charge region. This work shows that 1/fnoise is also increased during avalanche and that this increase is consistent with a previously reported correlation between surface recombination velocity and 1/fnoise.     

Direct measurement of the potential spike energy in AlGaAs/GaAs single-heterojunction bipolar transistors

A balanced two-step current transport theory, i.e., thermionic emission followed by Shockley diffusion, is applied to study the emitter-base (EB) potential spike energy in the AlGaAs/GaAs single-heterojunction bipolar transistor. It is found, surprisingly, that when the transistor is operated in the active region theI-Vcharacteristics of the collector current (IC) versus base-emitter applied voltage (VBE) exhibits an ideality factor of 1.237. This non-1kT transfer characteristics is due to the bias-dependent potential spike energy at the emitter-base heterojunction. The reverse I-V characteristics of emitter current (IE) versus base-collector bias (VBC), however, shows the traditional 1kT behavior. The difference between ICand IEat the same applied voltage (V_{BE} = V_{BC}) determines the potential spike energy (ΔE). It turns out that Δ E/q = 0.19(V_{BE} - 0.48)whereqis the unit charge. This indicates that the potential spike appears only when the applied voltageV_{BE} > 0.48V.     

The implementation of a reduced-field profile design forhigh-performance bipolar transistors

The first realization of a reduced-field design concept for advanced bipolar devices using the low-temperature epitaxial (LTE) technique to form the base layer is described. By inserting a lightly doped collector (LDC) spacer layer between the heavily doped base and collector regions, it is successfully demonstrated that the collector-base (CB) junction avalanche multiplication can be reduced substantially while maintaining high collector doping for current density consideration. Similar applications of the LDS technique to the emitter-base (EB) junction also results in a lower electric field, thus less EB junction reverse leakage. The feasibility of the reduced-field profile design concept is demonstrated using a LTE-base device structure     

Low-frequency noise in TFSOI lateral n-p-n bipolar transistors

Low-frequency (1/f) noise is characterized as a function of base current density (J_B) on thin-film-silicon-on-insulator (TFSOI) lateral bipolar transistors. In the low injection region of operation, the noise power spectral density was proportional to J_B ^1.8 for J_B<0.4 μA/μm², which suggest that the noise in these devices is primarily dominated by a uniform distribution of noise sources across the emitter-base area. However in the high current region of operation (J_B>0.4 μm²), the noise bias dependence shifts to J_B ^1.2, indicating current crowding effects, alter the contribution of noise sources near the extrinsic base link region of the device. In addition to the expected 1/f noise and shot noise, we have observed a bias dependent generation-recombination (Gm) noise source in some of the devices. This G/R noise is correlated to random-telegraph-signal (RTS) noise resulting from single trapping centers, located at or near the spacer oxide and/or the Si to SIMOX interface, which modulate the emitter-base space charge region     

X-ray lithography induced radiation damage in CMOS and bipolar devices

Radiation effects from a synchroton x-ray lithography source on the performance degradation and long term reliability of high performance self-aligned bipolar devices and deep sub-micron CMOS devices are studied. The hot-carrier properties of the x-ray induced damage in CMOS devices, such as interface states, positive oxide charges and neutral traps have been examined. The effect of these radiation induced defects and their impact on the DRAM circuits in terms of the performance and reliability are discussed. In the self-aligned, double polysilicon bipolar transistor structure interface states and trapped charges can be generated by the radiation source in the sidewall oxide near the emitter-base junction such damage can increase the emitter-base leakage current. This increase of base current can substantially degrade the device current gain at low bias.     

Partial-SOI isolation structure for reduced bipolar transistorparasitics

A bipolar isolation structure with the capability of significantly reducing collector-base capacitance and base resistance is presented. Partial SOI, with SOI surrounding the collector opening, can be used to reduce the collector window width in combination with any emitter-base self-aligned bipolar device structure, and in particular for device structures that feature sublithographic emitter width. Near-ideal transistor Gummel characteristics and a minimum ECL gate delay of 24 ps have been achieved with a nonoptimized lateral device layout, and simulations suggest that sub-20-ps delay at reduced switch current will be possible by using the optimized partial-SOI isolation structure     

Negative transconductance superlattice base bipolar transistor

The operation of a new superlattice base bipolar transistor is reported. Negative transconductance in the common-base transfer characteristic is achieved at an emitter-base voltage in excellent agreement with the bias required to suppress tunnel injection into the first miniband. In the common emitter configuration a corresponding peak in the current gain of the device is obtained as the base current is increased.<>     

The design, fabrication, and characterization of a novel electrode structure self-aligned HBT with a cutoff frequency of 45 GHz

This paper establishes a systematic approach for the design, fabrication, and modeling of a newly proposed self, aligned Al-GaAs/GaAs heterojunction bipolar transistor (HBT) employing a two-dimensional heterostructure device simulator and a heterojunction bi-polar transistor circuit simulator. The developed HBT has an abrupt emitter-base heterojunction, and applies a novel structure in which a single base electrode is placed between two emitter electrodes. A fabricated 3 × 8 µm²two-emitter HBT exhibits a measured current gain cutoff frequency fT= 45 GHz and a maximum oscillation frequency fmax= 18.5 GHz. Results of frequency divider circuit Simulation indicate that the developed HBT would be 1.4 times faster than a conventional HBT in which one emitter electrode is located between two base electrodes.     

Process and device characterization for a 30-GHz fT submicrometer double poly-Si bipolar technology using BF2-implanted base with rapid thermal process

Process and device parameters are characterized in detail for a 30-GHz f_T submicrometer double poly-Si bipolar technology using a BF₂-implanted base with a rapid thermal annealing (RTA) process. Temperature ramping during the emitter poly-Si film deposition process minimizes interfacial oxide film growth. An emitter RTA process at 1050°C for 30 s is required to achieve an acceptable emitter-base junction leakage current with an emitter resistance of 6.7×10^-7 Ω-cm², while achieving an emitter junction depth of 50 nm with a base width of 82 nm. The primary transistor parameters and the tradeoffs between cutoff frequency and collector-to-emitter breakdown voltage are characterized as functions of base implant dose, pedestal collector implant dose, link-base implant dose, and epitaxial-layer thickness. Transistor geometry dependences of device characteristics are also studied. Based on the characterization results for poly-Si resistors, boron-doped p-type poly-Si resistors show significantly better performance in temperature coefficient and linearity than arsenic-doped n-type poly-Si resistors     

On the current dependence of low-frequency noise in bipolar transistors

The bias dependent characteristics of the base input flicker noise or 1/f noise current generator in bipolar transistors is examined. A simple technique is presented for the determination of the flicker noise magnitude at selected low frequencies with varying collector bias current. The results indicate that the bias dependence of the flicker noise is intimately rated to that of the input conductance parameter gπin the common-emitter configuration. Practical methods are given for the determination of the bias-independent noise parameter ρ0, which, in conjunction with the small-signal network parameters, fully characterize the device noise performance at low frequencies, ρ0, is an equivalent noise resistance representing the open-circuit flicker noise voltage at the base terminal at 1 Hz. Results of noise figure measurements on several representative commercially available devices are compared with those calculated with a knowledge of ρ0.     

A novel InP/InAlGaAs negative-differential-resistanceheterojunction bipolar transistor (NDR-HBT) with interestingtopee-shaped current-voltage characteristics

A new and interesting negative-differential-resistance heterojunction bipolar transistor (NDR-HBT) based on the InP/InAlGaAs material system is fabricated successfully and demonstrated. Due to the employment of narrow base and δ-doped sheet at the emitter-base (E-B) heterojunction, the significant and interesting topee-shaped current-voltage (I-V) characteristics are observed in the low current regime. A peak-to-valley current ratio (PVCR) up to 11 in the NDR loci is found. In the higher current regimes, on the other hand, NDR phenomena disappear and the device acts as a normal bipolar transistor. These interesting properties are believed to be attributed mainly to the modulation of potential spike resulting from the specified device structure     

Effect of reverse base current on bipolar and BiCMOS circuits

A detailed study on the effect of reverse base current (RBC) on the switching behavior of bipolar BiCMOS circuits utilizing advanced high-performance bipolar transistors is presented. It is shown that as the collector doping N_c is increased to overcome the Kirk effect (base stretching) during the switching transient, the avalanche-generated reverse base current in the collector-base junction may cause problems for bipolar output devices switching out of saturation. A basic bipolar inverter and various BiCMOS driver circuits were simulated based on measured avalanche multiplication factors from advanced bipolar transistors with various collector doping N _c. In the case of the basic bipolar inverter, the reverse base current may prevent the switching device from being shut off completely during the on-to-off transition and a self-sustained state may result which reduces the output voltage swing. For the common-emitter (CE) BiCMOS driver, a similar self-sustained state may also occur with the added adverse effect of excessive leakage in standby. Design and scaling considerations are discussed     

Hot carrier induced bipolar transistor degradation due to basedopant compensation by hydrogen: theory and experiment

New experimental and analytical results are presented which show that extrinsic and intrinsic base dopant compensation by hydrogen is responsible for large changes in the bipolar transistor parameters of emitter-base breakdown voltage (V_ebo), forward collector current (I_c) and series base resistance (R_bx) when such transistors are operated under avalanche and inverted mode stress conditions. A new physical model has been developed to explain the observed changes in V_ebo and I_c as a function of stress time, and the analytical results are shown to be well correlated with the experimental data. Lastly, the effects of degradation on transistor voltage gain bandwidth (f_max) and emitter coupled bipolar comparator delay (τ_delay) are assessed and discussed in terms of circuit performance degradation     

A new epitaxial lateral overgrowth silicon bipolar transistor

A new device structure and method of fabricating a silicon bipolar transistor is proposed. The device has reduced collector parasitic capacitance and resistance as compared to other advanced bipolar technologies. By using selective and lateral epitaxial overgrowth techniques the buried (N+) layer is not necessary. Two-dimensional computer simulations show theC_{CS} times R_{C}product to be reduced by a factor of 5.45 along with reduced CCB.     

Noise effects in bipolar junction transistors at cryogenic temperatures: Part I

Part I of this investigation involves theoretical and experimental characterization of the noise performance of modern silicon planar bipolar junction transistors (BJT's) above the 1/f noise frequency region in a temperature range of 60-300 K and for several difference bias conditions. At temperatures below approximately 110 K, an excess noise source as measured by the equivalent noise resistance RN, referred to the input of the device, common-base configuration, is revealed. This excess source, resulting from a generation-recombination process within the base region of the device, is shown to have a linear dependence on the base current and base resistance as KIB²rb'b², and an exponential dependence on temperature.     

Thermal stability analysis of AlGaAs/GaAs heterojunction bipolartransistors with multiple emitter fingers

A numerical electro-thermal model was developed for AlGaAs/GaAs heterojunction bipolar transistors (HBT's) to describe the base current, current gain and output power dependence on junction temperature. The model is applied to microwave HBT devices with multi-emitter fingers. The calculated results of the common-emitter, current-voltage characteristics in the linear active region show a “current crush” effect due to inherent nonuniform junction temperature, current density and current gain distribution in the device. The formation of highly localized high temperature regions, i.e., hot spots, occur when the device is operating beyond the current-crush point. This thermally induced current instability imposes an upper limit on the power capability of HBT's. The dependence of this effect on various factors is discussed. These factors include the intrinsic parameters such as the base current ideality factor, the “apparent” valence band discontinuity, and the temperature coefficient of the emitter-base turn-on voltage, as well as the extrinsic factors such as the emitter contact specific resistance, the substrate thermal conductivity and the heat source layout     

Low 1/f noise characteristics of AlGaAs/GaAs heterojunction bipolartransistor with electrically abrupt emitter-base junction

It is shown that the use of an electrically abrupt emitter-base junction considerably reduces the 1/f noise of self-aligned AlGaAs/GaAs heterojunction bipolar transistor (HBT). Although this device does not have depleted AlGaAs ledge passivation layer, the low-frequency noise spectra show a very low 1/f noise corner frequency of less than 10 kHz, which is much lower than previously reported value of about 100 kHz from conventional passivated or unpassivated AlGaAs/GaAs HBT's. Except for a residual generation-recombination (g-r) noise component, the noise power is comparable to that of Si BJT. It is also found that the low-frequency noise power of the AlGaAs/GaAs HBT is proportional to the extrinsic GaAs base surface recombination current square. Unlike the other HBT's reported, the noise sources associated with interface state and emitter-base (E-B) space charge region recombination are not significant for our device