Collection of charge from alpha-particle tracks in silicon devices

Experimentally and by computer simulation, we have investigated the collection process of alpha-particle-generated charge in silicon devices. We studied the total charge collected and the transient characteristics of collection for various structures. Analytic results indicate that a strong drift field extends far beyond the original depletion layer, and funnels a large number of carriers into the struck node. This field-funneling component of charge collection is a strong function of substrate resistivity and bias voltage. It is relatively independent of the area of the struck device. The collection is less efficient for a small capacitance node. The funneling also occurred with a time delay when an alpha particle missed the field region by a short distance. Devices on an n-type substrate were also studied. They exhibit a similar funneling effect as the p-type substrate. The agreement between measurement and simulation is excellent. The impact on future VLSI design is discussed.     

高阻衬底上具有n+浮空层的横向Super Junction MOSFETs

提出了一种具有n+浮空层的横向super junction结构,此结构通过磷或砷离子注入在高阻衬底上形成n+浮空层来消除传统横向super junction结构中的衬底辅助耗尽效应.这种效应来源于p型的衬底辅助耗尽了super junction区的n型层,使p与n之间的电荷不能平衡.n+层的REBULF效应通过使漏端电场减小,体电场重新分布而使新结构中的衬底承担了更多的电压.结果表明这种结构具有高的击穿电压、低的导通电阻和漂移区中电荷平衡的特点.     

高阻衬底上具有n＋浮空层的横向Super Junction MOSFETs

提出了一种具有n^＋浮空层的横向superjunction结构，此结构通过磷或砷离子注入在高阻衬底上形成n^＋浮空层来消除传统横向superjunction结构中的衬底辅助耗尽效应．这种效应来源于P型的衬底辅助耗尽了superjunction区的n型层，使P与n之间的电荷不能平衡，n^＋层的REBULF效应通过使漏端电场减小，体电场重新分布而使新结构中的衬底承担了更多的电压，结果表明这种结构具有高的击穿电压、低的导通电阻和漂移区中电荷平衡的特点。     

A field-funneling effect on the collection of alpha-particle-generated carriers in silicon devices

We studied the transient characteristics of charge collection from alpha-particle tracks in silicon devices. We have run computer calculations using the finite element method, in parallel with experimental work. When an alpha particle penetrates a pn-junction, the generated carriers drastically distort the junction field. After the alpha particle penetration, the field, which was originally limited to the depletion region, extends far down into the bulk silicon along the length of the alpha-particle track and funnels a large number of carriers into the struck junction. After a few nanoseconds, the field recovers to its position in the normal depletion layer, and, if the track is long enough, a residue of carriers is left to be transported by diffusion. The extent of this field funneling is a function of substrate concentration, bias voltage, and the alpha-particle energy.     

Thin-film silicon-on-sapphire deep depletion MOS transistors

This paper describes thin-film MOS transistors in which the entire silicon film forms the conducting channel, not just the surface inversion layer. Single crystal silicon which is epitaxially deposited on sapphire to a thickness of 0.5 to 2.0 microns forms the channel of the field-effect transistor. The oxidations for the channel oxide were done in both steam and dry oxygen ambients resulting in very little oxide charge (0-2 × 10¹¹cm^-2) on both [111] and [100] silicon orientations. No orientation dependence was observed. The absence of an active substrate leads to device characteristics that are significantly different from MOS transistors made on thick silicon. Analysis of the output characteristics and the C-V curve of these devices enables one to study the characteristics of the silicon film and its two surfaces. It is shown that the silicon-sapphire interface region has similar characteristics to the silicon-silicon dioxide interface region in its tendency to support donor sites after heating in hydrogen. To facilitate analysis of the C-V curve, two interesting relations are derived: specifically, the slope of the curve is related to the doping density of the silicon, and the 0.95 level on the normalized curve is shown to be offset approximately one volt from flat-band potential regardless of oxide thickness or doping density, provided these parameters set the normalized flat-band capacitance significantly below 0.95. The use of thin high resistivity p-type films allows one to fabricate p-type enhancement transistors which exhibit a low threshold voltage due to the fact that the silicon surface does not have to be inverted before the channel conducts. Finally, partial-gate deep depletion transistors are examined and it is shown that a substantial increase in drain breakdown voltage may be obtained with thiss geometry.     

n-channel ion-implanted enhancement/depletion FET circuit and fabrication technology

n-channel enhancement/depletion technology and circuits are described. The threshold voltage adjustment to form the enhancement- and depletion-mode devices are achieved by ion implantation. This allows optimization of the performance and circuit density. The calculated and experimentally observed speed-power product is 10 pJ/pF with a single +5-V power supply. Inversion of the field region on the high resistivity p-type substrate is completely eliminated by the use of an implanted field shield.     

具有栅介质电场屏蔽作用的新型GaN纵向槽栅MOSFET器件设计

基于氮化镓(GaN)等宽禁带(WBG)半导体的金氧半场效应晶体管(MOSFET)器件在关态耐压下,栅介质中存在与宽禁带半导体临界击穿电场相当的大电场,致使栅介质在长期可靠性方面受到挑战。为了避免在GaN器件中使用尚不成熟的p型离子注入技术,提出了一种基于选择区域外延技术制备的新型GaN纵向槽栅MOSFET,可通过降低关态栅介质电场来提高栅介质可靠性。提出了关态下的耗尽区结电容空间电荷竞争模型,定性解释了栅介质电场p型屏蔽结构的结构参数对栅介质电场的影响规律及机理,并通过权衡器件性能与可靠性的关系,得到击穿电压为1 200 V、栅介质电场仅0.8 MV/cm的具有栅介质长期可靠性的新型GaN纵向槽栅MOSFET。     

High-voltage accumulation-layer UMOSFET's in 4H-SiC

A novel silicon carbide UMOSFET structure is reported. This device incorporates two new features: a self-aligned p-type implantation in the bottom of the trench that reduces the electric field in the trench oxide, and an n-type epilayer under the p-base to promote lateral current spreading into the drift region. This UMOS structure is capable of supporting the full blocking voltage of the pn junction while keeping the electric field in the gate oxide below 4 MV/cm. An accumulation channel is formed on the sidewalls of the trench by epigrowth, and the gate oxide is produced by a polysilicon oxidation process, resulting in a uniform oxide thickness over both the sidewalls and bottom of the trench. The fabricated 4H-SiC devices have a blocking voltage of 1400 V (10 μm drift region), a specific on-resistance of 15.7 mΩ-cm ² at room temperature, and a gate oxide field of 3 MV/cm     

Recombination lifetime in oxygen-precipitated silicon

The recombination lifetime degrades when interstitial oxygen precipitates in Czochralski-grown silicon. We have observed a more severe degradation in p-type than in n-type material. Based on recombination lifetime, deep-level transient spectroscopy, Fourier-transform infra-red transmission, and transmission electron microscopy measurements, we attribute the degradation mainly to interface states at the precipitate-silicon interface acting as recombination centers. Positive charge in the oxygen precipitates (OP's), causing an electron-attractive space-charge region (scr) around the precipitate in p-Si and a hole-repulsive accumulation layer in n-Si, is proposed to explain the lifetime differences between n-type and p-type silicon.     

一种带P型埋层的4H-SiC PiN二极管

碳化硅(SiC)PiN二极管是应用在高压大功率整流领域中的一种重要的功率二极管。受SiC外延材料的载流子寿命限制以及常规SiC PiN二极管较低的阳极注入效率的影响,SiC PiN二极管的正向导通性能较差,这极大限制了其在高压大电流领域的应用。文章提出了一种带P型埋层的4H-SiC PiN二极管,较常规SiC PiN二极管增强了阳极区的少子注入效率,降低了器件的导通电阻,增大了正向电流。仿真结果表明,当正向偏压为5 V时,引入P型埋层的SiC PiN二极管的正向电流密度比常规SiC PiN二极管提升了52.8%。     

Suppression of boron penetration in BF/sub 2/-implanted p-type gate MOSFET by trapping of fluorines in amorphous gate

This paper reports the use of amorphous/polysilicon gate electrode in BF/sub 2/-implanted poly-gated P-MOSFETs to suppress the boron penetration. SIMS analysis clearly illustrates that fluorine prefers to accumulate in the layer of amorphous silicon. The retardation of boron diffusion is therefore achieved by the trapping of fluorine in the amorphous layer of stacked amorphous/polysilicon (SAP) p-type gate due to a lower diffusion rate of fluorine in the amorphous silicon layer. Polysilicon depletion effect did not become more severe by introducing the amorphous silicon. In addition, gate oxide reliability is not degraded by using this gate structure. Results show that the structure is a promising gate electrode for future dual-poly gate CMOS technology development.<>     

Integration of 5-V CMOS and High-Voltage Devices for Display Driver Applications

Reduced surface field lateral double-diffused MOS transistors for the driving circuits of plasma display panel and field emission display in the 120 V region have been integrated for the first time into a low-voltage 1.2 μm analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers and also the cost of fabrication. The lateral double-diffused MOS transistor with a drift length of 6.0 μm and a breakdown voltage greater than 150 V was self-isolated to the low voltage CMOS ICs. The measured specific onresistance of the lateral double-diffused MOS is 4.8 mΩ·cm² at a gate voltage of 5 V.     

Simulation of near-surface proton-stimulated diffusion of boron in silicon

A quantitative model for near-surface redistribution of doping impurity in silicon in the course of proton-stimulated diffusion is developed for the first time. According to the model, the near-surface peak of the impurity concentration is caused by migration of neutral impurity—self-interstitial pairs to the surface with subsequent decomposition of these pairs and accumulation of the impurity at the silicon surface within a thin layer (referred to as δ-doped layer). The depletion and enhancement regions that are found deeper than the near-surface concentration peak are caused by expulsion of ionized impurity by an electric field from the near-surface region of the field penetration. The field appears due to the charge formed in the natural-oxide film at the silicon surface as a result of irradiation with protons. The diffusion-kinetic equations for the impurity, self-interstitials, vacancies, and impurity—self-interstitial pairs were solved numerically simultaneously with the Poisson equation. It is shown that the results of calculations are in quantitative agreement with experimental data on the proton-stimulated diffusion of boron impurity in the near-surface region of silicon.     

Influence of silicon doping density on vacuum field emission triode at high frequency range

Silicon FEA will affect the high frequency application of field emission tubes when it works at the microwave frequency range. This article shows that the electron emitting will be influenced by the majority carrier response time in semiconductor silicon. The surface capacitance and delay time of n-type and p-type silicon are calculated by using semiconductor theory. The result shows that the semiconductor conductivity will determine the maximum work frequency of device. The maximum work frequency (no considering other effects such as C_gc, g_m etc.) will be decreased from about 200 GHz to 2 GHz when the resistivity of p-type silicon is increased from 0.1 Ω · cm to 10 Ω cm.     

ZnO纳米棒的图形化生长及其场发射特性

介绍了用氢离子注入技术和阳极腐蚀方法在硼掺杂p-(100)型硅晶片上制备图形化的纳米硅(SiNC)薄膜工艺，并在这种图形化衬底上成功生长了图形化的ZnO纳米棒. 场发射测试表明制备的ZnO纳米棒具有良好的场发射性能，即具有较低的开启电场和阈值电场，较高的发射点密度.     

Parametric description of the effect of electron irradiation onrecombination lifetime in silicon layers: an experimental approach

The aim of this paper is to perform an experimental investigation on the effects of electron beam irradiation on the recombination lifetime of both p-type and n-type silicon layers in order to provide a set of parameters useful to model the recombination effects in semiconductor computer simulation package. To this goal, the authors propose to use a proper three-terminal test structure in order to extract these parameters directly from lifetime measurements along the silicon layers at different temperatures and at different injection levels by using the same silicon samples before and after the electron irradiation process in order to highlight the effects of the irradiation itself on the lifetime. The experimental results indicate that the electron irradiation is more effective for controlling the high-injection lifetime in p-type silicon than in an n-type one. The effect of the irradiation on lifetime can be basically taken into account by means of one energy level placed at 0.27 eV below the conduction band edge for both n-type and p-type material, with σ _p≅10 σ_n     

Inner-stripe AlGaAs/GaAs laser diode by single-step molecular beam epitaxy

A novel fabrication technique for a real refractive-index-guide inner-stripe laser by a single-step crystal growth is reported. The injected current is confined in the p-type silicon-doped GaAs region on the V-shaped groove with (111)A slopes by the crystal-orientation-dependent amphoteric nature of the silicon impurity in GaAs.     

Famos—A new semiconductor charge storage device

A new non-volatile charge storage device is described. The floating gate avalanche injection MOS (FAMOS) structure is a p-channel silicon gate field effect transistor in which no electric contact is made to the silicon gate. It combines the floating gate concept with avalanche injection of electrons from the surface depletion region of a p-n junction to yield reproducible charging characteristics with long term storage retention.     

PC1D方法对铝背场钝化技术的分析

降低单晶硅原材料成本,采用更薄的硅片作为太阳电池的原料是晶体硅太阳电池产业发展的趋势之一。对薄片化的太阳电池,铝背场的背表面钝化工艺显得愈加重要。采用PC1D太阳电池软件模拟的方法,对以商业用p型硅为衬底的单晶硅125×125太阳电池的铝背场的背表面钝化技术进行了模拟,分析得出,对一定厚度的电池片来说,尤其是当少数载流...     

P型硅纳米板压阻特性的理论研究

考虑量子尺寸效应与自旋轨道耦合作用,从含有应变的6×6 Luttinger-Kohn哈密顿量出发,采用有限差分方法建立了p型硅纳米板的能带结构模型.基于硅纳米板压阻特性与其能带结构的相关性,采用改进的压阻理论定量分析了厚度、杂质浓度与温度对其压阻系数的影响.研究结果表明:量子尺寸效应强烈改变了硅纳米板的能带结构,是其压阻系数增大的主要因素,而自旋轨道耦合作用仅对含较高应变的硅纳米板的能带结构有较大影响;硅纳米板的压阻系数具有尺寸效应,随厚度减小而增大,随杂质浓度增加或温度升高而减小.在高简并条件下,硅纳米板的压阻系数与温度无关,完全由杂质浓度的大小控制;在非简并条件下,情况刚好相反.最后,利用施加应力前后空穴等能面形状的变化定性分析了硅纳米板压阻特性的起源.