嵌入式存储器内建自测试的一种新型应用

当今,嵌入式存储器在SoC芯片面积中所占的比例越来越大,成为SoC芯片发展的一个显著特点。由于本身单元密度很高,嵌入式存储器比芯片上面的其它元件更容易造成硅片缺陷,成为影响芯片成品率的一个重要因素。本文对采用MARCH-C算法的嵌入式存储器内建自测试进行了改进,实现了对嵌入式存储器故障的检测和定位,能够准确判断故障地址和故障类型,使嵌入式存储器故障修复更加快捷、准确,同时达到故障覆盖率高、测试时间短的目的。     

一种高速增益单元存储器的内建自测试方案

介绍了一种用于测试高速增益单元嵌入式动态随机存储器的内建自测试方案。该方案包括了指令集设计和体系结构设计。四级指令流水线的引入使全速测试成为可能。该设计方案可以通过执行不同的测试指令,对待测存储器执行多种类型的测试,从而达到较高的故障覆盖率。该内建自测试模块被集成在了一个存储容量为8kb的增益单元嵌入式动态随机存储器芯片中,并在中芯国际0.13μm标准逻辑工艺下进行了流片验证。芯片测试结果表明,该内建自测试方案可以在多种测试模式下对待测存储器执行全速测试,提高了测试速度,降低了对自动测试设备的性能要求,提高了测试的效率。     

LSC87中嵌入式ROM内建自测试实现

LSC87芯片是与Intel8086配套使用的数值协处理器，体系结构复杂，有较大容量的嵌入式ROM存储器，考虑到与Intel8087的兼容性和管脚的限制，必须选择合适的可测性设计来提高芯片的可测性。文章研究了LSC87芯片中嵌入式ROM存储器电路的设计实现，然后提出了芯片中嵌入式ROM电路的内建自测试，着重介绍了内建自测试的设计与实现，并分析了采用内建自测试的误判概率，研究结果表明，文章进行的嵌入式ROM内建自测试仅仅增加了很少的芯片面积开销，获得了满意的故障覆盖率，大大提高了整个芯片的可测性。     

一款雷达信号处理SOC芯片的存储器内建自测试设计

内建自测试(BIST)为嵌入式存储器提供了一种有效的测试方法.详细介绍了存储器故障类型及内建自测试常用的March算法和ROM算法.在一款雷达信号处理SOC芯片中BIST被采用作为芯片内嵌RAM和ROM的可测试性设计的解决方案.利用BIST原理成功地为芯片内部5块RAM和2块ROM设计了自测试电路,并在芯片的实际测试过程中成功完成对存储器的测试并证明内嵌存储器不存在故障.     

嵌入式存储器的内建自测试算法及测试验证

嵌入式存储器的广泛应用使得内建自测试(BIST,Built-In Self-Test)在当前SoC设计中具有重要的作用,本文着重分析比较了几种BIST测试算法,并对嵌入式BIST的体系结构进行了剖析,最后深入研究了MARCH C-算法的实际应用,使用UMC.18SRAM和2PRAM仿真模型对存储器的BIST测试进行了验证,并成功将其应用于一款USB音视频芯片。     

嵌入式存储器内建自测试的原理及实现

随着集成电路设计规模的不断增大 ,在芯片中特别是在系统芯片 SOC( system on a chip)中嵌入大量存储器的设计方法正变得越来越重要。文中详细分析了嵌入式存储器内建自测试的实现原理 ,并给出了存储器内建自测试的一种典型实现。     

SoC中嵌入式SRAM的BIST测试方法研究

随着集成电路设计规模的不断增大,在系统芯片SoC(System on a Chip)中嵌入大量的SRAM存储器的设计方法变得越来越重要。文中介绍了SRAM的典型故障类型和几种常用的测试方法,同时详细分析了嵌入式SRAM存储器内建自测试的实现原理以及几种改进的March算法,另外,以16k×32bitSRAM为例,给出了SRAM内建自测试的一种典型实现,并在Altera-EP1S25上实现。     

一种节约面积的可编程存储器内建自测试设计方法

随着深亚微米技术不断的发展,在SoC设计中存储器需求越来越大,芯片的量产需要有效率而又具有相对的低成本的测试方法.可编程存储器内建自测试方法基于客制化的控制器,提供了一定程度可靠的弹性以及所需合理的硬件成本.我们在本文提出了一个P-MBIST设计的硬件分享架构,经由分享共用的地址产生器与控制器,P-MBIST电路的面积开销能够大幅减小,利用加入的两级流水线能够达到更高的测试速度.最后,所提出的P-MBIST电路能够由使用者自定义的配置文档而自动生成.     

嵌入式存储器的内建自修复设计

目前，关于嵌入式存储器的内建自测试（MBIST）技术已经日趋成熟。基于这种背景．研究了一种高效的内建自修复（MBISR）方法，试验表明它具有低面积开销和高修复率等优点，保证了嵌入式存储器不仅可测．而且可修复。极大地提高了芯片的成品率。     

GPS基带芯片中存储器的可测性设计

GPS基带芯片中嵌入的存储器采用存储器内建自测试(Memory Built-in-Self-Test,MBIST)技术进行可测性设计,并利用一种改进型算法对存储器内建自测试电路的控制逻辑进行设计,结果表明整个芯片的测试覆盖率和测试效率均得到显著提高,电路性能达到用户要求,设计一次成功.     

Symmetry Measure for Memory Test and Its Application in BIST Optimization

Programmable Built-in Self-Test (BIST) has been widely used for testing embedded memories. The main disadvantage of having programmability on BIST circuits is the size of Test Algorithm Register (TAR) that becomes very crucial in case of complex test algorithms. To optimize Programmable BIST hardware symmetric March tests are usually used in BIST engines. On the other hand, the used definitions do not reflect completely the existing symmetry in test algorithms and they also do not reflect the fact that the level of symmetry in a given test algorithm can be measured. A new method of symmetry measurement for memory test algorithms and a corresponding metric are introduced. A dependency between symmetry measure and BIST optimization range is analyzed. Optimization experiments that have been done for a number of well-known test algorithms show that the BIST hardware gain could reach 48%. However, the time overhead is negligible in comparison with the hardware gain. The experiments also show that starting from some point a monotone dependency between symmetry measure and BIST hardware area exists.     

Programmable built-in self-testing of embedded RAM clusters in system-on-chip architectures

Multiport memories are widely used as embedded cores in all communication system-on-chip devices. Due to their high complexity and very low accessibility, built-in self-test (BIST) is the most common solution implemented to test the different memories embedded in the system. This article presents a programmable BIST architecture based on a single microprogrammable BIST processor and a set of memory wrappers designed to simplify the test of a system containing a large number of distributed multiport memories of different sizes (number of bits, number of words), access protocols (asynchronous, synchronous), and timing.     

Combining Scan Test and Built-in Self Test

For digital chips containing functional logic and embedded memories, these are usually tested separately: Scan test is used for testing functional logic; Memory Built-in Self Test (MBIST) is run for embedded memories. A new approach is proposed to exercise scan test and MBIST in parallel in order to reduce production test time and improve stress tests. It requires only small additional logic and allows to simultaneously run both test modes. In general, the approach can be used to control simultaneously scan test and any Built-in Self Test (BIST) providing a simple pass/fail result.     

Effective march algorithms for testing single-order addressed memories

Today's commonly used macro generators provide for read/write memories of type SRAM, Register File, Multi-Port RAM, Single-Order Addressed Memory (e.g. FIFO), CAM (Content Addressable Memory), etc. In addition to automatically generating the required momory, the appropriate test, which may be applied externally or internally as a BIST, has to be determined.Current literature provides tests for most memory types; however, tests for single-order addressed (SOA) memories, whereby the address can only change in one direction (e.g. from address 0 ton-1) have not been published yet. SOA memories are used in FIFOs and in applications where the BIST area overhead and/or speed penalty for normal (dual) order addressing are not acceptable.This article illustrates the testing problems and presents a family of march algorithms optimized for testing SOA memories.     

Spotlight on memory: an optically biased, single-ended, three transistor, fully static RAM cell

A single-ended static memory scheme combining advantages of both a one-transistor dynamic RAM (DRAM) cell and a six-transistor static RAM (SRAM) cell is proposed in this article. For the first time, optical bias is introduced, converting the classical complementary metal-oxide semiconductor (CMOS) RAM to an optoelectronic device. The cell structure is highly scalable and cost effective. Various approaches and schemes were applied to combine advantages of static and dynamic RAM memories, striving to shorten access times, lower power dissipation, and decrease cell area. This is particularly true for system-on-a-chip (SoC) and embedded memories. Here, the novel approach towards the same goal is proposed and simulated, introducing standard CMOS technology. A single-ended, three-transistor, fully static RAM cell is demonstrated.     

Testing and Reliability Techniques for High-Bandwidth Embedded RAMs

Application-specific integrated circuits (ASICs) and high-performance processors such as Itanium and Compaq Alpha use a total of almost 75% of chip real estate for accommodating various types of embedded (or on-chip) memories. Although most of these embedded memories are single-port static (and in relatively few cases, dynamic) RAMs today, the high demand for bandwidth in digital television, fast signal processing, and high-speed networking applications will also fuel the need for on-chip multiport memories in the foreseeable future. The reliability of a complex VLSI chip will depend largely on the reliability of these embedded memory blocks. With device dimensions moving rapidly toward the ultimate physical limits of device scaling, which is in the regime of feature sizes of 50 nm or so, a host of complex failure modes is expected to occur in memory circuits. This tutorial underlines the need for appropriate testing and reliability techniques for the present to the next generation of embedded RAMs. Topics covered include: reliability and quality testing, fault modeling, advanced built-in self-test (BIST), built-in self-diagnosis (BISD), and built-in self-repair (BISR) techniques for high-bandwidth embedded RAMs.     

SoC and SiP, the Yin and Yang of the Tao for the New Electronic Era

“More than Moore” is becoming the password for these coming years. New steps to overcome technology limitations to diffuse, on the same die, different chips to have a complete system have been developed. This approach is called system in package (SiP), a way to have in a package dies of logic, analog, memory, passive components, etc., assembled to obtain a miniaturized board. SiP performances and limitations are here analyzed to understand advantages versus system on chip (SoC). This paper is a discussion about the main items that can lead to the choice of the right approach—SiP or SoC—before a system design start. Three persons attend to our virtual meeting: an SoC technology development manager, expert in microcontroller embedded memories and technology integration; an SiP analog radio-frequency design senior expert; and a moderator that designed embedded memories and now SiP, all involved to understand how to reach a tradeoff among these two approaches. Like for the Yin and Yang, symbol of the equilibrium for the Taoist philosophy, the two opposites divide the circle of the life, with a piece of each in the other.      

Fully Programmable Memory BIST for Commodity DRAMs

To accomplish a high‐speed test on low‐speed automatic test equipment (ATE), a new instruction‐based fully programmable memory built‐in self‐test (BIST) is proposed. The proposed memory BIST generates a high‐speed internal clock signal by multiplying an external low‐speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on‐the‐fly to perform complicated and hard‐to‐implement functions, such as loop operations and refresh‐interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.