LSC87中嵌入式ROM内建自测试实现

LSC87芯片是与Intel8086配套使用的数值协处理器，体系结构复杂，有较大容量的嵌入式ROM存储器，考虑到与Intel8087的兼容性和管脚的限制，必须选择合适的可测性设计来提高芯片的可测性。文章研究了LSC87芯片中嵌入式ROM存储器电路的设计实现，然后提出了芯片中嵌入式ROM电路的内建自测试，着重介绍了内建自测试的设计与实现，并分析了采用内建自测试的误判概率，研究结果表明，文章进行的嵌入式ROM内建自测试仅仅增加了很少的芯片面积开销，获得了满意的故障覆盖率，大大提高了整个芯片的可测性。     

在嵌入式系统中实现从RAM快速引导技术

本文以ARM7TDMI为例,对嵌入式系统从ROM和RAM引导的特点及技术实现进行了比较,对异常和中断概念给出了详细的辨析,介绍了如何实现嵌入式系统从RAM快速引导技术。     

软件开发工具ROM TOOLS的设计与实现

本文主要介绍了软件开发工具ROM TOOLS的设计与实现,首先提出了在嵌入式计算机中,用C语言编写的程序固化在ROM中遇到的问题,然后介绍了解决这些问题的方法,即ROM TOOLS的设计思想和方法,同时也介绍了ROM TOOLS的功能特点,最后给出了一个主要模块的框图。     

一种高速MaskROM的设计研究

文章分析讨论了掩模只读存储器的工作原理和结构,并结合实际工作,详细论述了一个高速的576k位MaskROM的设计与实现.针对字线负载大、速度慢的问题,从选择合适的译码方案和减少字线上RC负载两个方面,提高字线的响应速度,从而使MaskROM的读取时间有较大提高.该款MaskROM采用0.5μm CMOS工艺,电源电压5...     

基于ARM和DSP的视频会议终端设计与实现

从控制部分设计、数据处理部分设计以及两部分联合工作这3个方面介绍了一个视频会议终端的设计和实现。并给出了一个嵌入式系统的基本架构和数据处理器在嵌入式系统中的应用，对嵌入式系统的开发和应用有一定的积极作用。     

TMS320C6701 DSP自动加载研究

在嵌入式系统中,经常要求上电后系统能自动把程序从DSP外部的ROM加载到片内RAM执行.给出一种基于TMS320C6701 DSP的ROM加载方案,通过配置CCS中DSP/BIOS模块的参数实现DSP程序中代码和数据段的先后分开加载,比传统的由手动编写连接命令文件(.CMD)实现自动加载更为方便.在此基础上,设计并实现了用CCS直接对FLASH芯片进行在线烧写.实验证明,该DSP加载方案稳定可靠,且易于实现.     

基于NiosⅡ处理器的SVPWMIPCore设计

为降低FPGA实现3电平SVPWM算法的复杂性,减小SVPWM模块所占用的资源,文中利用正弦函数和余弦函数的关系,采用小容量ROM提出了一种新的SVPWM控制算法。利用Verilog HDL实现了算法的硬件设计,并封装成IP核以方便设计复用,在Altera公司的DE2开发板上进行了设计验证,体现了SOPC嵌入式系统的灵...     

在MPC555中实现从RAM的快速引导

介绍了PowerPC系列微处理器的异常和中断。同时以MPC555为例对嵌入式系统从ROM和RAM中的引导特点及技术实现方法进行了比较 ,给出了MPC555从RAM快速引导的实现方法     

Matrix宣称研制出全球最小的1Gb内存

多层反熔丝一次性可程序ROM供货商Matrix Semiconductor公司宣布，研制出全球最小的1Gb内存。这款内存芯片面积为31mm^2，整合了该公司所称的延伸其三维半导体设计领导地位的两种技术，即所谓的[混合缩放（hybrid scaling）]及分段字线（segmented wordline）结构。     

嵌入式实时通讯控制器设计与实现

目前系统间通讯问题已经成为制约嵌入式系统性能提高的瓶颈。基于目前嵌入式系统对实时性和系统开销的要求，文章提出了一种嵌入式实时通讯控制器设计，用FPGA实现了同步串行通讯，集成了中断和DMA控制器及双端口存储器，实现了可配置的通讯控制和数据存储功能，并已在某通信产品样机中应用。     

DDS中几种关键的ROM压缩方法

直接数字频率合成器(direct digital frequency synthesis，DDS)采用只读存储器(read only memory ROM)来完成相位到幅度的映射，由于DDS的频谱纯度与ROM表的大小成正比，而增大ROM，又会使系统功率消耗增大，稳定性降低。因此，为了既能满足信号的性能指标又能减少系统的开销，很多人开始寻求更好的ROM压缩方法。介绍了几种关键的ROM压缩方法并对其性能进行了比较。     

采用Flat_Cell技术的ROM设计和分析

Flat_Cell ROM具有高密度和高性能的优点。本文介绍了Flat_Cell结构和采用Flat_Cell技术的ROM设计方法。包括Flat_Cell的工艺技术、Flat_Cell基本电路结构和ROM放大器电路。     

基于硬件描述语言的MP3解码器仿真平台的搭建以及IP Core的重用

开发基于硬件描述语言的MP3解码器，首要的问题是要搭建一个能被很好地掌握控制的仿真平台。仿真平台包括仿真输入平台和仿真输出平台。在仿真输入平台中，构造了2个模块，一个是用来存储MP3音频文件的ROM模块，另一个是控制器模块，其功能是把ROM中的数据以串行数据流的方式送到解码器模块中去。其中，在构造ROM模块时，采用了IP Core重用。     

Crosstalk-insensitive via-programming ROMs using content-aware design framework

Various code patterns of a via-programming read only memory (ROM) cause significant fluctuations in coupling noise between bitlines (BLs). This crosstalk between BLs leads to read failure in high-speed via-programmable ROMs and limits the coverage of applicable code patterns. This work presents a content-aware design framework (CADF) for via-programming ROMs to overcome the crosstalk induced read failure. The CADF ROMs employ a content-aware structure and correspondent code-structure programming algorithm to reduce the amount of coupling noise source while maintaining nonminimal BL load for crosstalk reduction. A 256-Kb conventional ROM and a 256-Kb CADF ROM were fabricated using a 0.25-/spl mu/m logic CMOS process. The measured results ascertain that the read induced read failure is suppressed significantly by CADF. The CADF ROM also reduced 86.2% and 94.5% in power consumption and standby current compared to the conventional ROM, respectively.     

Analysis and Reduction of Supply Noise Fluctuations Induced by Embedded Via-Programming ROM

Various input addresses and accessed code-patterns of a via-programming read only memory (ROM) cause substantial fluctuations in peak current and supply noise across cycles. This work analyzes the fluctuations in the supply noise that are associated with the pattern-dependent current profile of embedded via-programming ROM on a QFN package with various decoupling capacitances. A pattern-insensitive (PI) technique is developed for via-programming ROM to reduce both fluctuations of peak current and cycle current across various input addresses and accessed code-patterns. The PI technique involves the arranging of the data patterns of a ROM-code and the adjustment of the structures of row decoders and peripheral circuits. Experiments based on the designed test-setup on fabricated 0.25 $mu$ m 256 kb ROM macros demonstrate the fluctuation in peak current of conventional ROM and its reduction by the PI technique. The fluctuations of measured peak and cycle currents of PI-ROM are only 0.7% and 13.1% of those of conventional ROM. The PI-ROM also has a 94.5% lower standby current than conventional ROM.      

An 80 ns 1 Mbit MASK ROM with a new memory cell

A high-speed 1-Mb MASK ROM incorporating a new through-hole programmed memory cell, named THOLE CELL, and a full CMOS static sense amplifier is described. The ROM has been fabricated using a double-polysilicon p-well CMOS technology. As a result of achieving a compact ROM cell that is as small as 5.2-/spl times/6.4 /spl mu/m/SUP 2/, even with relatively conservative 2.0 /spl mu/m design rules, a small die size of 7.08/spl times/7.7 mm/SUP 2/ is realized. The ROM organization is 128K/spl times/8 bit and has a typical access time of 80 ns. A typical active current of 8 mA is achieved, in spite of the fully static system. This ROM offers high speed and low power characteristics, while achieving small die size and short turnaround time.     

A four-state ROM using multilevel process technology

A four-state ROM is described which reduces conventional two-state ROM matrix size by 50%. The four states are encoded in the matrix by varying device thresholds using multiple ion implants. This is called multilevel technology. The detection of matrix device type is determined by the length of time required for a linearly ramped word line to rise from 0 V to the point where the matrix device is turned on. Peripheral circuitry has been devised to measure this time period and output the device type as a two-bit binary code. A 128K ROM which incorporates the new multilevel matrix cell has been fabricated in 6-/spl mu/m metal gate technology. Die size of the ROM is 208/spl times/213 mils/SUP 2/.     

Efficient rank-ordered mean (ROM) techniques for the recovery ofisolated losses in highly corrupted images

This paper proposes two efficient rank-ordered mean (ROM)-based techniques to conceal isolated losses in any image. The first technique is an iterative ROM-based technique while the second one is a modified version of ROM filtering. Both techniques have better performances than the SD-ROM technique especially for high loss percentages     

液晶显示器的汉字显示方法

研究了图形液晶模块的汉字显示方法，以8051单片机为基础，介绍了液晶模块与单片机的典型接口电路，描述了通过外扩的EEPROM存储汉字字模数据，将其作为外部数据存储器进行寻址，通过C51程序详细介绍了使用方法。对于程序存储器和数据存储器分开寻址的单片机，该方式能起到节省程序存储器，扩大程序容量的作用。     

A 256K ROM fabricated using n-well CMOS process technology

A 256K bit CMOS ROM with a speed-power product of 0.085 pJ/bit has been developed. The excellent speed-power product and the high packing density have been achieved by using n-well CMOS technology and a serial-parallel ROM cell structure. The concept and characteristics of a serial-parallel ROM cell structure are discussed and compared to conventional ROM cell structures. The serial-parallel ROM cell structure gives more flexibility for ROM matrix design. The chip size and memory cell size of the 256K CMOS ROM are 5.98/spl times/6.00 mm and 7.0/spl times/7.0 /spl mu/m, respectively. Access time is 370 ns. The power supply currents in active and quiescent modes are 12 mA and less than 0.1 /spl mu/A at +5 V, respectively.