A Compact, ESD-Protected, SiGe BiCMOS LNA for Ultra-Wideband Applications

Two 3.65-mW, ESD-protected, BiCMOS ultra-wideband low-noise amplifiers (LNAs) for operation up to 10 GHz are presented. These common-base LNAs achieve significant savings in die area over more widely used cascoded common-emitter LNAs because they do not use an LC input matching network. A design with a shunt peaked load achieves a high S₂₁ (17-19 dB) and low noise figure (NF) (4-5 dB) across the band. A resistively loaded design exhibits a lower S₂₁ (15-16 dB) and higher NF (4.5-6 dB), but also utilizes 20% less silicon area. Both LNAs achieve a 1.5 kV ESD protection level and an acceptable S₁₁ (<-10 dB) across the band. Current source noise reduction is critical in common base topologies. Therefore, detailed noise analyses of MOS- and HBT-based current sources are provided     

A Low-Power Linear SiGe BiCMOS Low-Noise Amplifier for Millimeter-Wave Active Imaging

This letter presents a low-power linear and wideband two-stage millimeter-wave low-noise amplifier (LNA) fabricated in a low-cost 0.18 $mu{rm m}$ SiGe BiCMOS technology. Design techniques utilized to optimize the gain and NF and to achieve high linearity and wideband at W-band are addressed. The LNA achieves a peak power gain of 14.5 dB at 77 GHz with a 3 dB bandwidth of 14.5 GHz from 69 to 83.5 GHz. The measured NF is 6.9 dB at 77 GHz and is lower than 8 dB from 64 to 81 GHz. Both input and output return losses are better than 11 dB and 17 dB at 77 GHz, respectively. The measured input 1 dB compression point is $-$11.4 dBm at 77 GHz with low power consumption of only 37 mW.      

宽带平衡器的优化设计与实现

天线系统一般包括天线及馈电两部分，系统的宽频带特性不仅取决于天线性能，而且还与馈电系统及两者之间有效耦合、匹配情况有关。其中，平衡器是馈电系统的重要组成部分。本文简述了天线馈电中引入平衡器的作用，同时针对平衡器设计中通常存在带宽较窄、功率容量低的特点，提出一种宽频带平衡器的设计方法，并在理论和实际应用中同时加以验证。     

Design of a Noise-Canceling CMOS Wideband Receiver Front-End with Inherent Active Balun

This paper presents the design of an ESD-protected noise-canceling CMOS wideband receiver front-end for cognitive and ultra-wideband (UWB) radio-based wireless communications. Designed in a 0.13-μm CMOS technology, the RF front-end integrates a broadband low-noise amplifier (LNA) and a quadrature down-conversion mixer. While having ESD and package parasitics absorbed into a wideband input matching network, the LNA exploits a combination of a common-gate (CG) stage and a common-source (CS) stage to cancel the noise of the CG-stage and to provide a well balanced differential output for driving the double-balance mixer, which has a merged quadrature topology. A variable-gain method is developed for the LNA to achieve a large factor of gain switch without degrading the input impedance match and the balun function. Drawing 24 mA from 1.5 V, simulations show that the proposed front-end has a 3-dB bandwidth of around 10 GHz spanning from 1.8 GHz up to 11.8 GHz with a maximum voltage conversion gain of 30 dB and a noise figure of 4.3–6.7 dB over the entire band.     

一种W波段SiGe BiCMOS平衡式功率放大器

基于0.13 μm SiGe BiCMOS工艺,设计了一种W波段平衡式功率放大器。采用了由两个单级放大器和两个3 dB差分正交耦合器组成的全差分结构。采用变压器匹配网络,实现了良好的输入与输出匹配性能。利用三维电磁场仿真软件进行了电磁仿真。仿真结果表明,在90~100 GHz频段内,输入与输出的匹配良好,输入反射系数S₁₁小于-17 dB,输出反射系数S₂₂小于-14 dB。在94 GHz频率处,小信号增益为6.1 dB,输出1 dB压缩点功率为10.2 dBm。芯片尺寸为1.22 mm × 1.42 mm。该功率放大器适用于通信、雷达、成像等领域。     

应用于TD-LTE的SiGe BiCMOS功率 放大器的设计

针对准第四代无线通信技术TD-LTE中2.570~2.620 GHz频段的应用,设计了一款基于IBM SiGe BiCMOS7WL工艺的射频功率放大器。该功率放大器工作于AB类,采用单端结构,由两级共发射极电路级联构成,带有基极镇流电阻,除两个谐振电感采用片外元件外,其他全部元件均片上集成,芯片面积为(1.004×0.736)mm2。测试结果表明,在3.3 V电源电压下,电路总消耗电流为109 mA,放大器的功率增益为16 dB,输出1 dB增益压缩点为15 dBm。该驱动放大器具有良好的输入匹配,工作稳定。     

Compact Wideband Bandpass Filters With Wide Upper Stopband

In this letter, a T-shaped microstrip feeding arrangement is proposed to design wideband bandpass filter (BPF) using shorted slot-line resonators. This feed line produces frequency selective external coupling which is utilized to suppress unwanted harmonics. Up to sixth order harmonics are suppressed. Other advantages are low passband group delay variation, ease of fabrication, low insertion loss (IL), and compact size. A fabricated BPF of fractional bandwidth 56.3% at midband frequency 2.3 GHz has a maximum IL of 1.2 dB in its passband and 30-dB upper stopband extends over 11.53 GHz     

用于有源相控阵的X 波段SiGe BiCMOS 功放设计

设计了一款应用于有源相控阵雷达T/R 组件的X 波段功率放大器,放大器采用单端两级放大的共源共栅结构,包括输入与输出匹配网络,偏置电路采用自适应线性化技术,实现高增益和高线性的输出。基于IBM 0.18 μm SiGe BiCMOS 7WL 工艺流片,测试结果表明,在3.3 V 电源电压下,在8.5 GHz 时增益为21.8 dB,1 dB 压缩点输出功率为10.4 dBm,输入输出匹配良好,芯片面积为1.4 mm×0.8 mm。芯片面积较小,实现了与整个T/R 芯片的集成。     

A 10-GHz SiGe BiCMOS phase-locked-loop frequency synthesizer

A SiGe BiCMOS phase-locked-loop (ILL) circuit is presented. A maximum operational frequency of 10 GHz and a current consumption of 7.6 mA, i.e., 17 mW, is demonstrated. For a 9-mW low-power version, a maximum frequency of 4.7 GHz is determined. In a GSM direct conversion application, an in-band phase noise of -79 dBc/Hz at 2 kHz and a spurious suppression of -75 dBc at 400 kHz was measured at 3.4 GHz, which corresponds to a PLL phase noise floor of -214 dBc/Hz. For low-power applications, the PLL can be operated at supply voltages as low as 2.2 V and at RF input powers as low as -20 dBm while having a large output voltage range of 0.2 V to (V_cc-0.3 V). This demonstrates the speed and power advantage of the SiGe BiCMOS over Si BiCMOS and CMOS technologies for wireless communications     

一种2.4 GHz全集成SiGe BiCMOS功率放大器

针对2.4 GHz 802.11 b/g无线局域网(WLAN)的应用,该文设计了一种单片全集成的射频功率放大器(PA)。由于在自适应偏置电路中采用异质结晶体管(HBT)和电容构成的简单结构提高PA的线性度,因此不增加PA的直流功耗、插损和芯片面积。在基极偏置的DC通路中采用电阻负反馈实现温度稳定功能,有效避免热崩溃的同时不引起射频损耗。采用了GRACE 0.18mSiGe BiCMOS 工艺流片,芯片面积为1.56 mm2,实现了包括所有偏置电路和匹配电路的片上全集成。测试结果表明,在2.4-2.5 GHz工作频段,PA的小信号S21增益达23 dB,输入回波损耗S11小于-15 dB。PA的 1 dB 输出压缩点的线性输出功率为19.6 dBm,功率附加效率为20%,功率增益为22 dB。     

A 2.5-GHz eight-phase VCO in SiGe BiCMOS technology

We present a 2.5-GHz voltage-controlled oscillator (VCO) with eight equally distributed phases derived from a 10-GHz LC VCO. Stochastic and static phase errors were obtained by spectrum analyzer measurements in conjunction with an on-chip single-sideband mixer. From the measured phase noise spectrum, we predict an absolute rms jitter contribution of 130 fs in a 2-MHz bandwidth phase-locked loop. A static phase error of less than 0.7/spl deg/ was deduced from the sideband suppression. The eight-phase VCO is tunable from 2.35 to 2.85 GHz and draws 16 mA from a 2.0-V supply. Possible applications include clock and data recovery of a 10-Gb/s signal in a fiber-optic receiver as well as high-precision image rejection receivers and I/Q direct up-converters for radio-frequency applications.     

A SiGe BiCMOS Eight-Channel Multidithering Sub-Microsecond Adaptive Controller

A SiGe BiCMOS mixed-signal adaptive controller-on-chip is presented that implements gradient descent of a supplied analog control objective. Eight analog variables controlling the external plant are perturbed in parallel using sinusoidal dithers, and their gradient components are estimated by parallel synchronous detection of the dithers in the control objective. Translinear all-NPN bipolar circuits achieve linear tuning of frequency and amplitude in the oscillators and synchronous detectors, covering a 4-kHz–600-MHz range in dither frequencies with $-$ 30-dB/octave suppression of intermodulation products. Experimental results demonstrate adaptive optimization of a three-variable nonlinear plant within 1 ${rm mu}hbox{s}$ for dithers in the 100–200-MHz frequency range. The chip measures 3 mm $times$ 3 mm in 0.5-${rm mu}hbox{m}$ SiGe and consumes 110 mW at 3.3-V supply.      

A CDMA Dual-Band Zero-IF Receiver With Integrated LNAs and VCOs in an Advanced SiGe BiCMOS Process

This paper describes one of the first dual PCS- and CEL-band CDMA receivers that includes LNAs and VCOs on a single die. The PCS-band LNA achieves a noise figure (NF) of 1.5dB and IP3 of +7.5 dBm at 16-dB gain. The PCS demodulating mixer achieves an NF of 5 dB, IP3 of +5 dBm and uncalibrated IP2 of +60 dBm. The PCS VCO is capable of -134 dBc/Hz phase noise at 3.9 GHz and 1.25-MHz offset. A copper BiCMOS process was chosen for both performance and cost benefits, compared with lower geometry CMOS     

一种5位10 GHz SiGe BiCMOS比较器

SiGe BiCMOS提供了性能极其优异的异质结晶体管(HBT),其ft超过70 GHz,β>120,并具有高线性、低噪声等特点,非常适合高频领域的应用。基于SiGe BiCMOS工艺,提出了一种高性能全差分超高速比较器。该电路由宽带宽前置放大器和改进的主从式锁存器组成,采用3.3 V单电压源,比较时钟超过10 GHz,差模信号电压输入量程为0.8 V,输出差模电压0.4 V,输入失调电压约2.5 mV;工作时钟10 GHz时,用于闪烁式A/D转换器可以达到5位的精度。     

Wideband Planar Folded Dipole Antenna With Self-balanced Impedance Property

A planar folded dipole antenna that exhibits wideband characteristics is proposed. The antenna has simple planar construction without a ground plane and is easy to be assembled. Parameter values are adjusted in order to obtain wideband properties and compactness by using an electromagnetic simulator based on the method of moments. An experimental result centered at 1.7 GHz for 50 impedance matching shows that the antenna has bandwidth over 55% . The gains of the antenna are almost constant (2 dBi) in this frequency band and the radiation patterns are very similar to those of a normal dipole antenna. It is also shown that the antenna has a self-balanced impedance property in this frequency band.     

A 36–80 GHz High Gain Millimeter-Wave Double-Balanced Active Frequency Doubler in SiGe BiCMOS

This letter presents a high conversion gain double-balanced active frequency doubler operating from 36 to 80 GHz. The circuit was fabricated in a 200 GHz ${rm f}_{rm T}$ and ${rm f}_{max}$ 0.18 $mu$m SiGe BiCMOS process. The frequency doubler achieves a peak conversion gain of 10.2 dB at 66 GHz. The maximum output power is 1.7 dBm at 66 GHz and ${-}3.9$ dBm at 80 GHz. The maximum fundamental suppression of 36 dB is observed at 60 GHz and is better than 20 dB from 36 to 80 GHz. The frequency doubler draws 41.6 mA from a nominal 3.3 V supply. The chip area of the active frequency doubler is 640 $mu$m $,times,$424 $mu$m (0.272 mm $^{2}$) including the pads. To the best of authors' knowledge, this active frequency doubler has demonstrated the highest operating frequency with highest conversion gain and output power among all other silicon-based active frequency doublers reported to date.      

Highly Linear Ku-Band SiGe PIN Diode Phase Shifter in Standard SiGe BiCMOS Process

This letter presents a fully integrated highly linear 4-bit SiGe PIN diode phase shifter MMIC for Ku-band phase-array application in the standard SiGe BiCMOS process. High-performance customized SiGe PIN diode switches are employed for high linearity and low insertion loss. The use of differential inductors in the hybrid switched filters makes this phase shifter compact in size. Measurements show 20 dB ${pm}5$ dB input/output return loss, less than ${pm} 1.8^{circ}$ phase variation, and maximum 37 dBm input-referred IP3 over the 14.5–15.5 GHz frequency range, while this phase shifter draws an average current of 3.5 mA from a 3.3 V power supply. To the authors' best knowledge, this 4-bit phase shifter MMIC achieves the highest linearity at Ku-band in the standard SiGe BiCMOS process without utilizing any post-fabrication process for low loss transmission lines.      

Compact, Wideband Bandstop Filters With Sharp Rejection Characteristic

A compact unit of parallel coupled transmission line is presented for design of a compact, sharp-rejection, wideband bandstop filter (BSF). The rejection depth and bandwidth can be easily controlled by the coupled-line parameters. A lossless transmission line model is used for filter analysis. Design equations and graphs are presented in order to facilitate the design procedure. Theoretical prediction is verified in microstrip line by fabricating a prototype single section coupled-line BSF.     

一种基于锗硅双极CMOS工艺的多频段移动电视调谐器芯片

本文给出了一种应用于多频段移动电视调谐器的射频芯片的设计和测试结果。射频调协器由宽带射频前端电路,模拟基带电路,全集成的小数频率综合器和I2C数字接口电路组成。为了满足移动电视标准苛刻的临道抑制指标,同时兼顾低功耗、低成本的要求,本设计采用了带局部自动增益控制的直接下变频接收机方案。为进一步提高临道抑制的性能,基带频道选择滤波器采用了8阶椭圆有源RC的结构,具有阻带衰减高和过渡带极陡的特点。射频调协器芯片采用0.35 μm锗硅双极CMOS工艺制成,硅片面积为5.5 mm2。芯片采用3.0V单电源供电,消耗50mA电流。在CMMB应用中,系统灵敏度达到-97 dBm,临道抑制优于40 dB。