Graphical properties of easily localizable sensor networks

The sensor network localization problem is one of determining the Euclidean positions of all sensors in a network given knowledge of the Euclidean positions of some, and knowledge of a number of inter-sensor distances. This paper identifies graphical properties which can ensure unique localizability, and further sets of properties which can ensure not only unique localizability but also provide guarantees on the associated computational complexity, which can even be linear in the number of sensors on occasions. Sensor networks with minimal connectedness properties in which sensor transmit powers can be increased to increase the sensing radius lend themselves to the acquiring of the needed graphical properties. Results are presented for networks in both two and three dimensions. B. D. O. Anderson supported by National ICT Australia, which is funded by the Australian Government’s Department of Communications, Information Technology and the Arts and the Australian Research Council through the Backing Australia’s Ability initiative and the ICT Centre of Excellence Program. A. S. Morse supported by US Army Research Office and US National Science Foundation. W. Whiteley supported in part by grants from NSERC (Canada) and NIH (USA). Y. R. Yang supported in part by US National Science Foundation. Brian Anderson is a Distinguished Professor at the Research School of Information Sciences and Engineering, The Australian National University, Australia. Professor Anderson took his undergraduate degrees in Mathematics and Electrical Engineering at Sydney University, and his doctoral degree in Electrical Engineering at Stanford University. He worked in industry in the United States and at Stanford University before serving as Professor of Electrical Engineering at the University of Newcastle, Australia from 1967 through 1981. At that time, he took up a post as Professor and Head of the Department of Systems Engineering at the Australian National University in Canberra, where he was Director of the Research School of Information Sciences and Engineering from 1994 to 2002. For approximately one year to May 2003, he was the inaugural CEO of the newly formed National ICT Australia, established by the Australian Government through the Department of Communications, Information Technology and the Arts and the Australian Research Council under the Information and Communication Technologies Centre of Excellence program. Professor Anderson has served as a member of a number of government bodies, including the Australian Science and Technology Council and the Prime Minister’s Science, Engineering and Innovation Council. He was a member of the Board of Cochlear Limited, the world’s major supplier of cochlear implants from its listing until 2005. He is a Fellow of the Australian Academy of Science and Academy of Technological Sciences and Engineering, the Institute of Electrical and Electronic Engineers, and an Honorary Fellow of the Institution of Engineers, Australia. In 1989, he became a Fellow of the Royal Society, London, and in 2002 a Foreign Associate of the US National Academy of Engineering. He holds honorary doctorates of the Catholic University of Louvain in Belgium, the Swiss Federal Institute of Technology, and the Universities of Sydney, Melbourne and New South Wales. He was appointed an Officer of the Order of Australia in 1993. He was President of the International Federation of Automatic Control for the triennium 1990 to 1993, and served as President of the Australian Academy of Science for four years from 1998 to 2002. Professor Anderson became the Chief Scientist of National ICT Australia in May 2003 and served in that role till September 2006. Tolga Eren received the B.S. degree in electrical engineering from Bilkent University, Ankara, Turkey, the M.S.E.E. degree in electrical engineering from the University of Massachusetts, the M.S. and the Ph.D. degrees in engineering and applied science from Yale University, New Haven, Connecticut, in 1994, 1998, 1999, and 2003, respectively. From October 2003 to July 2005, he was a postdoctoral research scientist at the Computer Science Department at Columbia University in the City of New York. Since September 2005, he has been at the department of Electrical Engineering at Kirikkale University, Turkey. His research interests are multi-agent (multi-robot, multi-vehicle) systems, sensor networks, computer vision, graph theory, and computational geometry. A. Stephen Morse was born in Mt. Vernon, New York. He received a BSEE degree from Cornell University, MS degree from the University of Arizona, and a Ph.D. degree from Purdue University. From 1967 to 1970 he was associated with the Office of Control Theory and Application OCTA at the NASA Electronics Research Center in Cambridge, Mass. Since 1970 he has been with Yale University where he is presently the Dudley Professor of Engineering and a Professor of Computer Science. His main interest is in system theory and he has done research in network synthesis, optimal control, multivariable control, adaptive control, urban transportation, vision-based control, hybrid and nonlinear systems, sensor networks, and coordination and control of large grouping of mobile autonomous agents. He is a Fellow of the IEEE, a Distinguished Lecturer of the IEEE Control System Society, and a co-recipient of the Society’s 1993 and 2005 George S. Axelby Outstanding Paper Awards. He has twice received the American Automatic Control Council’s Best Paper Award and is a co-recipient of the Automatica Theory/Methodology Prize . He is the 1999 recipient of the IEEE Technical Field Award for Control Systems. He is a member of the National Academy of Engineering and the Connecticut Academy of Science and Engineering. Walter Whiteley (B.Sc. 66, Queen’s University at Kingston, Canada) received his Ph.D. in Mathematics from MIT, Cambridge Mass in 1971. He is currently the Director of Applied Mathematics at York University, and a member of the graduate programs in Mathematics, in Computer Science, and in Education. His research focuses on the rigidity and flexibility of systems of geometric constraints (distances, angles, directions, projections, …). Recent work has included applications of this theory to location in networks, control of formations of autonomous agents, built structures in structural engineering, linkages in mechanical engineering, geometric constraints in computational geometry and CAD, and algorithms for protein flexibility in biochemistry. He is also active in geometry education and development of visual reasoning at all levels of mathematics education and in applications of mathematics. Yang Richard Yang received the B.E. degree in Computer Science and Technology from Tsinghua University, Beijing, China, in 1993, and the M.S. and Ph.D. degrees in Computer Science from the University of Texas at Austin in 1998 and 2001, respectively. Since 2001, he has been with the Department of Computer Science, Yale University, New Haven, CT, where currently he is an Associate Professor of Computer Science and Electrical Engineering. His current research interests are in computer networks, mobile computing, and sensor networks. He leads the Laboratory of Networked Systems (LANS) at Yale University.     

Biography - Wilbur L. Pritchard

Wilbur L. Pritchard (A'45-M'48-SM'52) was born in New York, N.Y., on May 31, 1923. He received the B.E.E. degree in 1943 from the College of the City of New York. From 1948 to 1951 he was gaged in part-time graduate study at the Massachusetts Institute of Technology.     

UHF RF Front-End Circuits in 0.35-μm Silicon on Insulator (SOI) CMOS

In this work, design and measurement results of UHF RF frontend circuits to be used in low-IF and subsampling receiver architectures are presented. We report on three low noise amplifiers (LNA) (i) single-ended (ii) differential (iii) high-gain differential and a double-balanced mixer all implemented in 0.35-μ m SOI (Silicon on Insulator) CMOS technology of Honeywell. These circuits are considered as candidate low-power building blocks to be used in the two fully-integrated receiver chips targeted for deep space communications. Characteristics of square spiral inductors with high quality (Q) factors (as high as 10.8) in SOI CMOS are reported. Single-ended and fully-differential LNA's provide gains of 17.5 dB and 18.74 dB at 435 MHz, respectively. Noise figure of the single-ended LNA is 2.91 dB while the differential LNA's noise figure is 3.25 dB. These results were obtained for the power dissipations of 12.5 mW and 16.5 mW from a 2.5-V supply for the single-ended and differential LNA's, respectively. High-gain low-power differential LNA provides a small-signal gain of 45.6 dB with a noise figure of 2.4 dB at 435 MHz. Total power dissipation of the high gain LNA is 28 mW from a 3.3-V supply. The double-balanced mixer provides a conversion gain of 5.5 dB with a noise figure of 13 dB at 2 MHz IF. The power dissipation of the mixer is 11.5 mW from a 2.5-V supply. The measured responses and the power dissipations of the building blocks meet the requirements of the communications system. The die areas occupied by the single-ended LNA, differential LNA, high-gain LNA and the mixer are 0.6 mm × 1.4 mm, 1 mm × 1.4 mm, 1.4 mm × 1.2 mm and 0.6 mm × 0.9 mm, respectively. Ertan Zencir received the B.Sc. and M.S. degrees in electrical and electronics engineering from Middle East Technical University, Ankara, Turkey, and Ph.D. degree in electrical engineering from Syracuse University, Syracuse, NY in 1995, 1997, and 2003, respectively. He joined the Electrical Engineering and Computer Science Department of University of Wisconsin-Milwaukee as an Assistant Professor in August 2004. 2003). His current research focuses on RFIC and transceiver design for wireless communications. Douglas Te-Hsin Huang was born in Chia-yi Taiwan. He received the B.S. degree in electrical engineering from National Taiwan Ocean University, Kee-lung, Taiwan in 1993, and the M.S. and Ph.D. degrees in electrical engineering from Syracuse University, Syracuse, New York, in 2001 and 2003, respectively. In 2004, he joined Skyworks Solutions Inc., where he is currently an RFIC Design Engineer. His research deals mainly with low-power, infrastructure, analog RFIC, and microwave integrated circuit designs. Besides microwave and semiconductor engineering, Dr. Huang has broad interest in art, music, and philosophy. Ahmet Tekin received his B.S. degree in Electrical Engineering from Bogazici University, Istanbul, Turkey in 2002 and MS degree in Electrical engineering form North Carolina A&T State University, Greensboro, NC. He is currently working towards his PhD degree at University of California, Santa Cruz, CA. He was a Research Assistant at RF Microelectronic Laboratory, North Carolina A&T State University, from 2002 to 2004. He worked on the design of low power UHF transceiver circuits for space applications. He is currently a Research Assistant at Bio-mimetic Microelectronic Systems Laboratory, University of California at Santa Cruz, working on implantable very low power UHF frequency transceiver for a body sensor network. Numan S. Dogan received the B.Sc. degree from Karadeniz Technical University, Trabzon, Turkey, in 1975, the M.Sc. degree from Polytechnic University, New York, in 1979, and the PhD degree from the University of Michigan, Ann Arbor, in 1986, all in electrical engineering. Since 1998, he has been with the Electrical and Computer Engineering Department, North Carolina A&T State University, Greensboro, North Carolina, where he is an Associate Professor. He was a Visiting Faculty Researcher at Air Force Research Laboratory (AFRL), Eglin Air Force Base, Florida, in 1998, and General Electric Corporate Research and Development Laboratory, Schenectady, New York, in 1999. His earlier research interests included microwave and millimeter-wave solid-state devices and circuits, high-temperature electronics, and silicon micromachining. His recent research interests include RF CMOS Integrated Circuits and low-power Medical Implant Communication Systems (MICS) transceivers. Currently he serves as the Chair of the IEEE Central North Carolina Section. In April 2004, he organized “a walking robot competition” for High School Students. He enjoys hiking to Alpine Lakes in the Pacific Northwest and fishing. Ercument Arvas (M'85–SM'89) received the B.S. and M.S. degrees from METU, Ankara, Turkey, in 1976 and 1979, respectively, and the Ph.D. degree from Syracuse University, Syracuse, New York, in 1983, all in Electrical Engineering. Between 1984 and fall of 1987, he was with the Electrical Engineering Department of Rochester Institute of Technology, Rochester, New York. He joined the Electrical Engineering and Computer Science Department of Syracuse University in 1987, where he is currently a Professor. His research interests include numerical electromagnetics, antennas, and microwave circuits and devices.     

Capacity and Error Probability for Maximal Ratio Combining Reception over Correlated Nakagami Fading Channels

In this paper, the capacity and error probability of maximal ratio combining (MRC) reception are considered for different modulation schemes over correlated Nakagami fading channels. Based on an equivalent scalar additive white Gaussian noise (AWGN) channel, we derive the characteristic function (CF) and the probability density function (PDF) of the signal to noise ratio for MRC reception over Nakagami fading channels. Using these CF and PDF results, closed form error probability and capacity expressions are obtained for PSK, PAM and QAM modulation. Wei Li received his Ph.D. degree in Electrical and Computer Engineering from the University of Victoria in 2004. He is now a Post-doctoral Research Fellow in the Department of Electrical and Computer Engineering at the University of Victoria. He is a Member of the IEEE. His research interests include ultra-wideband system, spread spectrum communications, diversity for wireless communications, and cellular communication systems. Hao Zhang was born in Jiangsu, China, in 1975. He received his Bachelor Degree in Telecom Engineering and Industrial Management from Shanghai Jiaotong University, China in 1994, his MBA from New York Institute of Technology, USA in 2001, and his Ph.D. in Electrical and Computer Engineering from the University of Victoria, Canada in 2004. His research interests include ultra-wideband radio systems, MIMO wireless systems, and spectrum communications. From 1994 to 1997, he was the Assistant President of ICO(China) Global Communication Company. He was the Founder and CEO of Beijing Parco Co., Ltd. from 1998 to 2000. In 2000, he joined Microsoft Canada as a Software Engineer, and was Chief Engineer at Dream Access Information Technology, Canada from 2001 to 2002. He is currently an Adjunct Assistant Professor in the Department of Electrical and Computer Engineering at the University of Victoria. T. Aaron Gulliver received the Ph.D. degree in Electrical and Computer Engineering from the University of Victoria, Victoria, BC, Canada in 1989. From 1989 to 1991 he was employed as a Defence Scientist at Defence Research Establishment Ottawa, Ottawa, ON, Canada. He has held academic positions at Carleton University, Ottawa, and the University of Canterbury, Christchurch, New Zealand. He joined the University of Victoria in 1999 and is a Professor in the Department of Electrical and Computer Engineering. He is a Senior Member of the IEEE and a member of the Association of Professional Engineers of Ontario, Canada. In 2002, he became a Fellow of the Engineering Institute of Canada. His research interests include information theory and communication theory, algebraic coding theory, cryptography, construction of optimal codes, turbo codes, spread spectrum communications, space-time coding and ultra wideband communications.     

FGMOS Current Mirror: Behaviour and Bandwidth Enhancement

This paper presents a high performance, resistively compensated low voltage current mirror using floating gate MOSFETs (FGMOS). The compensation technique desensitizes the output current and input compliance voltage with respect to the process generated variations in the threshold voltages of the mirroring transistors. Theoretical and simulation results exhibit an appreciable increase in bandwidth of the current mirror for this compensation technique. The operation of these circuits has been verified using PSpice simulations for 0.5 μ m CMOS technology at a supply voltage of ±0.75 V. A part of this paper has appeared in IEEE APCCAS 2002 and NSM 2003. S. Sharma was born on 6th July 1967 at village Bhagta, district Udhampur, J and K (India). He received MSc Physics (Electronics) degree from University of Jammu in 1991 and was awarded University Gold Medal. After qualifying NET (CSIR), he joined as Lecturer in 1995 in the department of Physics and Electronics of the same University. He is presently a Senior Lecturer and pursuing for Ph.D. degree in the area of Analog Integrated Circuits. He has eight papers published in National/International Conferences/Journals. He is a life member of IETE (India). S.S. Rajput was born on July 1, 1957, at village Bashir Pur, District Bijnor UP India. He received his B. E. in Electronics and Communication Engineering and M. E. in Solid State Electronics Engineering from University of Roorkee, Roorkee, India (Now IIT, Roorkee) in 1978 and 1981 respectively and was awarded University gold medal in 1981. He earned his Ph.D. degree from Indian Institute of Technology, Delhi in 2002 and his topic of research was “Low voltage current mode analog circuit structures and their applications”. He joined National Physical Laboratory, New Delhi, India as Scientist B in 1983, where he is presently serving as Scientist EII. He has worked for the design, development, testing and fabrication of an instrument meant for space exploration under the ISRO-NPL joint program for development of scientific instruments for the Indian Satellite SROSS-C and SROSS-C2 missions. His research interests include low voltage analog VLSI, instrument design for space applications, Digital Signal Processing, Fault tolerant design, and fault detection. He has chaired the many sessions in Indian as well as International conferences. He is Fellow member of IETE (India). He has been awarded best paper award for IETE Journal of Education for the year 2002. He has delivered many invited talks on Low Voltage Analog VLSI. Few tutorials have been presented in International Conferences on his Research Work. He has more than 30 publications in national and international journals. L.K. Mangotra was born on 14th April 1944 at Jammu, India. He received M.Sc. (Physics) from University of Kashmir in 1968 and Ph.D. (High Energy Physics) from University of Jammu in 1974. He worked as Assistant Director in Forensic Laboratory of J and K Govt. from 1974–78. He joined Physics Department, University of Jammu as Lecturer in 1978 and became Professor in 1988. He has 131 publications in International Journals and 41 papers in proceedings of International/National Conferences. He has number of visits to foreign Universities in connection with research and has been awarded various Fellowships. He is a member of various Professional/Academic/Administrative bodies. Presently, Prof. Mangotra is an Advisor to University of Jammu for Modernization of University Infrastructure and Principal Investigator for Jammu University and Coordinator of All India Universities in the International Collaborative research project “ALICE” in High Energy Physics sponsored by Department of Atomic Energy and Department of Science and Technology, Govt. of India. S.S. Jamuar was born on 27th November 1949. He received his BSc. Engineering Degree in Electronics and Communication from Bihar Institute of Technology, Sindri in 1967, M. Tech and Ph.D. in Electrical Engineering from Indian Institute of Technology, Kanpur, India in 1970 and 1977 respectively. He worked as Research Assistant, Senior Research Fellow and Senior Research Assistant from 1969 to 1975 at IIT Kanpur. During 1975–76, he was with Hindustan Aeronautics Ltd., Lucknow. Subsequently he joined the Lasers and Spectroscopy Group in the Physics Department at IIT Kanpur, where he was involved in the design of various types of Laser Systems. He joined department of Electrical Engineering of IIT Delhi in 1977, where he became Professor in 1991. He is presently Professor in the department of Electrical and Electronic Engineering Department, Faculty of Engineering, University Putra Malaysia, Malaysia. His area of research interest includes Electronic Circuit Design, Instrumentation and Communication systems. He is recipient of Meghnad Saha Memorial Award 1976 from IETE, Distinguished Alumni Award from BIT Sindri in 1999. Dr. Jamuar is senior member of IEEE and Fellow member of IETE (India). He is presently the Chair for CASS Chapter of IEEE Malaysia Section.     

Signal threshold adaptation for vertical handoff in heterogeneous wireless networks

The convergence of heterogeneous wireless access technologies has been envisioned to characterize the next generation wireless networks. In such converged systems, the seamless and efficient handoff between different access technologies (vertical handoff) is essential and remains a challenging problem. The heterogeneous co-existence of access technologies with largely different characteristics results in handoff asymmetry that differs from the traditional intra-network handoff (horizontal handoff) problem. In the case where one network is preferred, the vertical handoff decision should be carefully executed, based on the wireless channel state, network layer characteristics, as well as application requirements. In this paper, we study the performance of vertical handoff using the integration of 3G cellular and wireless local area networks as an example. In particular, we investigate the effect of an application-based signal strength threshold on an adaptive preferred-network lifetime-based handoff strategy, in terms of the signalling load, available bandwidth, and packet delay for an inter-network roaming mobile. We present an analytical framework to evaluate the converged system performance, which is validated by computer simulation. We show how the proposed analytical model can be used to provide design guidelines for the optimization of vertical handoff in the next generation integrated wireless networks. This article is the extended version of a paper presented in IFIP Networking 2005 Ahmed H. Zahran is a Ph.D. candidate at the Department of Electrical and Computer Engineering, University of Toronto. He received both his M.Sc. and B.Sc. in Electrical Engineering from Electronics and Electrical Communication Department in the Faculty of Engineering, Cairo University in 2002 and 2000 respectively, where he was holding teaching and research positions. Since September 2003, he has been working as a research assistant in the Department of Electrical and Computer Engineering, University of Toronto under the supervision of Professor Ben Liang. His research interest is wireless communication and networking with an emphasis on the design and analysis of networking protocols and algorithms. Ben Liang received honors simultaneous B.Sc. (valedictorian) and M.Sc. degrees in Electrical Engineering from Polytechnic University in Brooklyn, New York, in 1997 and the PhD degree in Electrical Engineering with Computer Science minor from Cornell University in Ithaca, New York, in 2001. In the 2001–2002 academic year, he was a visiting lecturer and post-doctoral research associate at Cornell University. He joined the Department of Electrical and Computer Engineering at the University of Toronto as an Assistant Professor in 2002. His current research interests are in the areas of mobile networking and wireless multimedia systems. He is a member of Tau Beta Pi, IEEE, and ACM and serves on the organization and technical program committees of a number of major conferences each year. Aladdin Saleh earned his Ph.D. degree in Electrical Engineering from London University, England. Since March 1998, Dr. Saleh has been working in the Wireless Technology Department of Bell Canada, the largest service provider of wireless, wire-line, and Internet in Canada. He worked as a senior application architect in the wireless data group working on several projects among them the wireless application protocol (WAP) and the location-based services. Later, he led the work on several key projects in the broadband wireless network access planning group including planning of the IEEE 802.16/ Wimax, the IEEE 802.11/ WiFi, and the integration of these technologies with the 3G cellular network including Mobile IP (MIP) deployment. Dr. Saleh also holds the position of Adjunct Full Professor at the Department of Electrical and Computer Engineering of Waterloo University, Canada since January 2004. He is currently conducting several joint research projects with the University of Waterloo and the University of Toronto on IEEE 802.16-Wimax, MIMO technology, interworking of IEEE 802.11 WLAN and 3G cellular networks, and next generation wireless networks. Prior to joining Bell Canada, Dr. Saleh worked as a faculty member at different universities and was Dean and Chairman of Department for several years. Dr. Saleh is a Fellow of IEE and a Senior Member of IEEE.     

VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance

This paper presents the architectural design of a multicomputer interconnection network based on the use of optical technology. The performance of the system is evaluated on a set of signal processing applications. The interconnect uses Vertical Cavity Surface Emitting Lasers (VCSELs) and flexible fiber image guides to implement a physical ring topology that is logically configured as a multiring. Processors in the multicomputer are nodes on the ring and extremely high communication bandwidth is possible. Using the Laser Channel Allocation (LCA) algorithm and the Deficit Round Robin (DRR) media access protocol, the bandwidth available in the optical interconnect can be reconfigured to make efficient use of the interconnect resources. A discrete-event simulation model of the interconnect is used to examine performance issues such as throughput, latency, fairness, and the impact of reconfigurability.Roger D. Chamberlain completed the degrees BSCS and BSEE in 1983, MSCS in 1985, and DSc (computer science) in 1989 all from Washington University in St. Louis, Missouri. He is currently an Associate Professor of Computer Science and Engineering at Washington University, where he is Director of the Computer Engineering Program. Dr. Chamberlain teaches and conducts research in the areas of computer architecture, parallel computing, embedded systems, and digital design.Mark A. Franklin received his BA, BSEE and MSEE from Columbia University, and his Ph.D. in EE from Carnegie-Mellon University. He is currently a Professor in the Department of Computer Science and Engineering at Washington University in St. Louis, Missouri, and holds the Hugo F. and Ina Champ Urbauer Chair in Engineering. He founded and is former Director of the Computer and Communications Research Center.Dr. Franklin is a Fellow of the IEEE and a member of the ACM. He has been Chair of the IEEE TCCA (Technical Committee on Computer Architecture), and Vice-Chair of the ACM SIGARCH (Special Interest Group on Computer Architecture). His research areas include computer and systems architecture, ASIC and embedded processor design, parallel and distributed systems, and systems performance evaluation.Praveen Krishnamurthy received the Bachelor of Engineering degree from University of Madras (India) in 2000 and the MS degree in Computer Engineering from Washington University in St. Louis, Missouri, in 2002. He is currently a doctoral student at Washington University in St. Louis.Abhijit Mahajan received his B.E (Electronics) degree from University of Mumbai in 1998. He received is MSEE from Washington University in 2000. He is presently working with Broadcom Corporation in India. His main area of work is signal integrity and systems engineering.     

A Comparative Evaluation of Designs for Reliable Memory Systems

This paper addresses the design of storage systems for operation under critical environmental conditions. For these applications, these systems should have low latency time in access, high performance in throughput and high storage capabilities; therefore, they must be assembled using highly reliable components, while allowing flexibility in design. Commercial Off The Shelf (COTS) components have often been used. A COTS-based architecture is analyzed in this paper; the proposed architecture uses design-level techniques (such as error detection/correction codes and scrubbing) to make commercially available Dynamic Random Access Memory (DRAM) chips tolerant to faults. This paper provides a complete and novel analysis of engineering alternatives which arise in the design of a highly reliable memory system based on Reed Solomon coding. A comparative analysis of methods for permanent fault detection is provided; moreover using a Markovian characterization, different functional arrangements (based on code and scrubbing frequency) are investigated and evaluated.Gian Carlo Cardarilli received the Laurea (summa cum laude) in 1981 from the University of Rome La Sapienza. He works for the University of Rome Tor Vergata since 1984. At present he is full professor of Digital Electronics and Electronics for Communication Systems at the University of Rome Tor Vergata. During the years 1992–1994 he worked for the University of L Aquila. During the years 1987/1988 he worked for the Circuits and Systems team at EPFL of Lausanne (Switzerland). Professor Cardarilli interests is in the area of VLSI architectures for Signal Processing and IC design. In this field he published over 140 papers in international journals and conferences. He also participated to the work group of JESSI-SMI for the support to the medium and small industries. For this structure he consulted different SMIs, designing a number ASICs, in order to introduce the microelectronics technology in the industry’s products. He has also regular cooperation with companies like Alenia Aerospazio, Rome, Italy, STM, Agrate Brianza, Italy, Micron, Avezzano, Italy, Ericsson Lab, Rome, Italy and with a lot of SMEs. Scientific interests of Professor Cardarilli concern the design of special architectures for signal processing. In particular, he works in the field of computer arithmetic and its application to the design of fast signal digital processor. He also developed mixed-signal neural network architectures implementing them in silicon technology. Recently, he also proposed different new solutions for the implementation of fault-tolerant architectures.Fabrizio Lombardi graduated in 1977 from the University of Essex (UK) with a B.Sc. (Hons.) in Electronic Engineering. In 1977 he joined the Microwave Research Unit at University College London, where he received the Master in Microwaves and Modern Optics (1978), the Diploma in Microwave Engineering (1978) and the Ph.D. from the University of London in 1982.He is currently the holder of the International Test Conference (ITC) Endowed Professorship at Northeastern University, Boston. At the same Institution during the period 1998–2004 he served as Chair of the Department of Electrical and Computer Engineering. Prior to Northeastern University he was a faculty member at Texas Tech University, the University of Colorado-Boulder and Texas A&M University.Dr. Lombardi has received many professional awards: the Visiting Fellowship at the British Columbia Advanced System Institute, University of Victoria, Canada (1988), twice the Texas Experimental Engineering Station Research Fellowship (1991–1992, 1997–1998) the Halliburton Professorship (1995), the Outstanding Engineering Research award at Northeastern University (2004) and an International Research award from the Ministry of Science and Education of Japan (1993–1999). Dr. Lombardi was the recipient of the 1985/86 Research Initiation award from the IEEE/Engineering Foundation and a Silver Quill award from Motorola-Austin (1996).Dr. Lombardi was an Associate Editor (1996–2000) of IEEE Transactions on Computers and a Distinguished Visitor of the IEEE-CS (1990–1993 and 2001–2004). Since 2000, he has been the Associate Editor-In-Chief of IEEE Transactions on Computers and an Associate Editor of the IEEE Design and Test Magazine. Since 2004 he serves as the Chair of the Committee on “Nanotechnology Devices and Systems” of the Test Technology Technical Council of the IEEE.Dr. Lombardi has been involved in organizing many international symposia, conferences and workshops sponsored by professional organizations as well as guest editor of Special Issues in archival journals and magazines such as the IEEE Transactions on Computers, IEEE Transactions on Instrumentation and Measurement, the IEEE Micro Magazine and the IEEE Design & Test Magazine. He is the Founding General Chair of the IEEE Symposium on Network Computing and Applications.His research interests are testing and design of digital systems, quantum and nano computing, ATE systems, configurable/network computing, defect tolerance and CAD VLSI. He has extensively published in these areas and edited six books.Marco Ottavi is currently postdoctoral research associate at the ECE Department of Northeastern University in Boston. He received the Laurea degree in Electronic Engineering from University of Rome “La Sapienza” in 1999 and the Ph.D. in Microelectronics and Telecommunications from University of Rome “Tor Vergata” in 2004. In 2000 he was with ULISSE Consortium, Rome as designer of digital systems for space applications. In 2003 he was visiting research assistant at ECE Department of Northeastern University. His research interests include yield and reliability modeling, fault-tolerant architectures, on-line testing and design of nano scale circuits and systems.Salvatore Pontarelli is currently postdoctoral research associate at the University of Rome, Tor Vergata. He received the Laurea degree in Electronic Engineering from the University of Bologna in 1999 and the Ph.D. in Microelectronics and Telecommunications Engineering from the University of Rome Tor Vergata in 2003. His research mainly focuses on fault tolerance, on-line testing and reconfigurable digital architectures.Adelio Salsano was born in Rome on December 26, 1941 and is currently full professor of Microelectronics at the University of Rome, Tor Vergata where he teaches the courses of Microelectronics and Electronic Programmable Systems. His present research work focuses on the techniques for the design of VLSI circuits, considering both the CAD problems and the architectures for ASIC design. In particular, of relevant interest are the research activities on fault tolerant/fail safe systems for critical environments as space, automotive etc.; on low power systems considering the circuit and architectural points of view; and on fuzzy and neural systems for pattern recognition. An international patent and more than 90 papers on international journals or presented in international meetings are the results of his research activity. At present he is the President of a national consortium named U.L.I.S.S.E., between ten universities, three polytechnics and several of the biggest national industries, as STMicroelectronics, ESAOTE, FINMECCANICA. He is responsible for contracts with the ASI, Italian Space Agency, for the evaluation and use in space environment of COTS circuits and for the definition of new suitable architectures for space applications. Professor Salsano is also involved in professional activities in the field of information technology and is also consultant of many public authorities for specific problems. In particular, he is consultant of the Departments of the Research and of the Industry, of IMI and of other authorities for the evaluation of industrial public and private research projects. Professor Salsano was a member of the consulting Committee for Engineering Sciences of the CNR (National Research Council) from 1981 to 1994 and participated in the design of public research programs in the fields of Telematics, Telemedicine, Office Automation, Telecommunication and, recently, Microelectronics and Bioelectronics.     

On the Use of Multiple Hops in Next Generation Wireless Systems

Traditional cellular networks provide a centralized wireless networking paradigm within the wireless domain with the help of fixed infrastructure nodes such as Base Stations (BSs). On the other hand, Ad hoc wireless networks provide a fully distributed wireless networking scheme with no dependency on fixed infrastructure nodes. Recent studies show that the use of multihop wireless relaying in the presence of infrastructure based nodes improves system capacity of wireless networks. In this paper, we consider three recent wireless network architectures that combine the multihop relaying with infrastructure support – namely Integrated Cellular and Ad hoc Relaying (iCAR) system, Hybrid Wireless Network (HWN) architecture, and Multihop Cellular Networks (MCNs), for a detailed qualitative and quantitative performance evaluation. MCNs use multihop relaying by the Mobile Stations (MSs) controlled by the BS. iCAR uses fixed Ad hoc Relay Stations (ARSs) placed at the boundaries to relay excess traffic from a hot cell to cooler neighbor cells. HWN dynamically switches its mode of operation between a centralized Cellular mode and a distributed Ad hoc mode based on the throughput achieved. An interesting observation derived from these studies is that, none of these architectures is superior to the rest, rather each one performs better in certain conditions. MCN is found to be performing better than the other two architectures in terms of throughput, under normal traffic conditions. At very high node densities, the variable power control employed in HWN architecture is found to be having a superior impact on the throughput. The mobility of relay stations significantly influences the call dropping probability and control overhead of the system and hence at high mobility iCAR which uses fixed ARSs is found to be performing better. This work was supported by Infosys Technologies Ltd., Bangalore, India and the Department of Science and Technology, New Delhi, India. B. S. Manoj received his Ph.D degree in Computer Science and Engineering from the Indian Institute of Technology, Madras, India, in July 2004. He has worked as a Senior Engineer with Banyan Networks Pvt. Ltd., Chennai, India from 1998 to 2000 where his primary responsibility included design and development of protocols for real-time traffic support in data networks. He had been an Infosys doctoral student in the Department of Computer Science and Engineering at the Indian Institute of Technology-Madras, India. He is a recipient of the Indian Science Congress Association Young Scientist Award for the Year 2003. Since the beginning of 2005, he has been a post doctoral researcher in the Department of Electrical and Computer Engineering, University of California, San Diego. His current research interests include ad hoc wireless networks, next generation wireless architectures, and wireless sensor networks. K. Jayanth Kumar obtained his B.Tech degree in Computer Science and Engineering in 2002 from the Indian Institute of Technology, Madras, India. He is currently working towards the Ph.D degree in the department of Computer Science at the University of California, Berkeley. Christo Frank D obtained his B.Tech degree in Computer Science and Engineering in 2002 from the Indian Institute of Technology, Madras, India. He is currently working towards the Ph.D. degree in the department of Computer Science at the University of Illinois at Urbana-Champaign. His current research interests include wireless networks, distributed systems, and operating systems. C. Siva Ram Murthy received the B.Tech. degree in Electronics and Communications Engineering from Regional Engineering College (now National Institute of Technology), Warangal, India, in 1982, the M.Tech. degree in Computer Engineering from the Indian Institute of Technology (IIT), Kharagpur, India, in 1984, and the Ph.D. degree in Computer Science from the Indian Institute of Science, Bangalore, India, in 1988. He joined the Department of Computer Science and Engineering, IIT, Madras, as a Lecturer in September 1988, and became an Assistant Professor in August 1989 and an Associate Professor in May 1995. He has been a Professor with the same department since September 2000. He has held visiting positions at the German National Research Centre for Information Technology (GMD), Bonn, Germany, the University of Stuttgart, Germany, the University of Freiburg, Germany, the Swiss Federal Institute of Technology (EPFL), Switzerland, and the University of Washington, Seattle, USA. He has to his credit over 120 research papers in international journals and over 100 international conference publications. He is the co-author of the textbooks Parallel Computers: Architecture and Programming, (Prentice-Hall of India, New Delhi, India), New Parallel Algorithms for Direct Solution of Linear Equations, (John Wiley & Sons, Inc., New York, USA), Resource Management in Real-time Systems and Networks, (MIT Press, Cambridge, Massachusetts, USA), WDM Optical Networks: Concepts, Design, and Algorithms, (Prentice Hall, Upper Saddle River, New Jersey, USA), and Ad Hoc Wireless Networks: Architectures and Protocols, (Prentice Hall, Upper Saddle River, New Jersey, USA). His research interests include parallel and distributed computing, real-time systems, lightwave networks, and wireless networks. Dr.Murthy is a recipient of the Sheshgiri Kaikini Medal for the Best Ph.D. Thesis from the Indian Institute of Science, the Indian National Science Academy (INSA) Medal for Young Scientists, and Dr. Vikram Sarabhai Research Award for his scientific contributions and achievements in the fields of Electronics, Informatics, Telematics & Automation. He is a co-recipient of Best Paper Awards from the 1st Inter Research Institute Student Seminar (IRISS) in Computer Science, the 5th IEEE International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS), and the 6th and 11th International Conference on High Performance Computing (HiPC). He is a Fellow of the Indian National Academy of Engineering.     

Pipeline of Successive Approximation Converters with Optimum Power Merit Factor

In this paper, we present a low power 12 bit 5 MSPS, successive approximation converter architecture using pipeline technique. The converter consumes 4 mW at the Nyquist rate input with 1.8 V power supply. By combination of pipeline and successive architecture, the entire circuit, simulated at the transistor level in a 0.18 μ CMOS process, achieves a FoM (Figure of Merit) of 0.19 pJ/conversion. Jinghua Li was born in 1973. He received the MSEE and BSEE Degree from College of Electronics and information, Shanghai Jiaotong University and Harbin Engineering University in 1997 and 1994 respectively. He is currently pursuing Ph.D degree in Department of Electrical Engineering, Texas A&M University, College Station, TX, USA. In 1997, he joined Bell Laboratory (China), Lucent Technologies as a member of technical staff. He worked on single-chip HDTV decoder IC and Sonet/SDH SoC for various projects in Murray Hill, NJ, USA and Shanghai China. He also finished projects on hardware implementation of Video conference/Phone based on H.263 standard as his master thesis. Since 2000, he has been a research assistant in Analog Mixed Signal center, TAMU. Most currently his research interests are focused on low power analog to digital conversion IC design, CMOS implementation of 10 G/2.5 G clock data recovery IC for high speed serial communications. Franco Maloberti received the Laurea Degree in Physics (Summa cum Laude) from the University of Parma, Parma Italy, in 1968 and the Dr. Honoris Causa degree in electronics from the Instituto Nacional de Astrofisica, Optica y Electronica (Inaoe), Puebla, Mexico in 1996. In 1993 he was a Visiting Professor at ETH-PEL, Zurich. He was Professor of Microelectronics and Head of the Micro Integrated Systems Group University of Pavia, Pavia, Italy and the TI/J.Kilby Analog Engineering Chair Professor at the Texas A&M University. He is currently the Distinguished Microelectronic Chair Professor at University of Texas at Dallas and part-time Professor at the University of Pavia, Italy. His professional expertise is in the design, analysis and characterization of integrated circuits and analogue digital applications, mainly in the areas of switched capacitor circuits, data converters, interfaces for telecommunication and sensor systems, and CAD for analogue and mixed A-D design. He has written more than 250 published papers, three books and holds 15 patents. He was in 1992 recipient of the XII Pedriali Prize for his technical and scientific contributions to national industrial production. He was co-recipient of the 1996 Institute of Electrical Engineers (U.K.) Fleming Premium for the paper “CMOS Triode Transistor Transconductor for high-frequency continuous time filters.” He has been responsible at both technical and management levels for many research programs including ten ESPRIT projects and has served the European Commission as ESPRIT Projects' Evaluator, Reviewer and as European Union expert in many European Initiatives. He served the Academy of Finland on the assessment of electronic research in Academic institutions and on the research programs' evaluations. Dr. Maloberti was Vice-President, Region 8, of the IEEE Circuit and Systems Society from 1995 to 1997 and an Associate Editor of IEEE-Transaction on Circuit and System-II. He received the 1999 IEEE CAS Society Meritorious Service Award, the 2000 CAS Society Golden Jubilee Medal, and the IEEE Millenium Medal. He is the President of the IEEE Sensor Council and member of the Board of Governors of the IEEE CAS Society. He is a member of the Italian Electrothecnical and Electronic Society (AEI), the Editorial Board of Analog Integrated Circuits and Signal Processing, and Fellow of IEEE.     

On Node Lifetime Problem for Energy-Constrained Wireless Sensor Networks

A fundamental problem in wireless sensor networks is to maximize network lifetime under given energy constraints. In this paper, we study the network lifetime problem by considering not only maximizing the time until the first node fails, but also maximizing the lifetimes for all the nodes in the network, which we define as the Lexicographic Max-Min (LMM) node lifetime problem. The main contributions of this paper are two-fold. First, we develop a polynomial-time algorithm to derive the LMM-optimal node lifetime vector, which effectively circumvents the computational complexity problem associated with an existing state-of-the-art approach, which is exponential. The main ideas in our approach include: (1) a link-based problem formulation, which significantly reduces the problem size in comparison with a flow-based formulation, and (2) an intelligent exploitation of parametric analysis technique, which in most cases determines the minimum set of nodes that use up their energy at each stage using very simple computations. Second, we present a simple (also polynomial-time) algorithm to calculate the flow routing schedule such that the LMM-optimal node lifetime vector can be achieved. Our results in this paper advance the state-of-the-art algorithmic design for network-wide node lifetime problem and facilitate future studies of the network lifetime problem in energy-constrained wireless sensor networks. Y. Thomas Hou obtained his B.E. degree from the City College of New York in 1991, the M.S. degree from Columbia University in 1993, and the Ph.D. degree from Polytechnic University, Brooklyn, New York, in 1998, all in Electrical Engineering. From 1997 to 2002, Dr. Hou was a research scientist and project leader at Fujitsu Laboratories of America, IP Networking Research Department, Sunnyvale, California(Silicon Valley). Since Fall 2002, he has been an Assistant Professor at Virginia Tech, the Bradley Department of Electrical and Computer Engineering, Blacksburg, Virginia. Dr. Hou's research interests are in the algorithmic design and optimization for network systems. His current research focuses on wireless sensor networks and multimedia over wireless ad hoc networks. In recent years, he has worked on scalable architectures, protocols, and implementations for differentiated services Internet; service overlay networking; multimedia streaming over the Internet; and network bandwidth allocation policies and distributed flow control algorithms. He has published extensively in the above areas and is a co-recipient of the 2002 IEEE International Conference on Network Protocols (ICNP) Best Paper Award and the 2001 IEEE Transactions on Circuits and Systems for Video Technology (CSVT) Best Paper Award. He is a member of ACM and a senior member of IEEE. Yi Shi received his B.S. degree from University of Science and Technology of China, Hefei, China, in 1998, a M.S. degree from Institute of Software, Chinese Academy of Science, Beijing, China, in 2001, and a second M.S. degree from Virginia Tech, Blacksburg, VA, in 2003, all in computer science. He is currently working toward his Ph.D. degree in electrical and computer engineering at Virginia Tech. While in undergraduate, he was a recipient of Meritorious Award in International Mathematical Contest in Modeling and 1997 and 1998, respectively. Yi's current research focuses on algorithms and optimization for wireless sensor networks and wireless ad hoc networks. His work has appeared in highly selective international conferences (e.g., ACM MobiCom and MobiHoc). Hanif D. Sherali is the W. Thomas Rice Endowed Chaired Professor of Engineering in the Industrial and Systems Engineering Department at Virginia Polytechnic Institute and State University. His area of research interest is in discrete and continuous optimization, with applications to location, transportation, and engineering design problems. He has published about 200 papers in Operations Research journals, has co-authored four books in this area, and serves on the editorial board of eight journals. He is a member of the National Academy of Engineering.     

Energy-aware on-demand routing protocols for wireless ad hoc networks

Energy use is a crucial design concern in wireless ad hoc networks since wireless terminals are typically battery-operated. The design objectives of energy-aware routing are two folds: Selecting energy-efficient paths and minimizing the protocol overhead incurred for acquiring such paths. To achieve these goals simultaneously, we present the design of several on-demand energy-aware routing protocols. The key idea behind our design is to adaptively select the subset of nodes that are required to involve in a route-searching process in order to acquire a high residual-energy path and/or the degree to which nodes are required to participate in the process of searching for a low-power path in networks wherein nodes have transmission power adjusting capability. Analytical and simulation results are given to demonstrate the high performance of the designed protocols in energy-efficient utilization as well as in reducing the protocol overhead incurred in acquiring energy-efficient routes. Baoxian Zhang received his B.S., M.S., and Ph.D. degrees in Electrical Engineering from Northern Jiaotong University, Beijing, China in 1994, 1997, and 2000, respectively. From January 2001 to August 2002, he was working with Department of Electrical and Computer Engineering at Queen’s University in Kingston as a postdoctoral fellow. He is currently a research scientist with the School of Information Technology and Engineering (SITE) of University of Ottawa in Ottawa, Ontario, Canada. He has published over 40 refereed technical papers in international journals and conference proceedings. His research interests include routing algorithm and protocol design, QoS management, wireless ad hoc and sensor networks, survivable optical networks, multicast communications, and performance evaluation. He is a member of the IEEE. Hussein Mouftah joined the School of Information Technology and Engineering (SITE) of the University of Ottawa in September 2002 as a Canada Research Chair (Tier 1) Professor in Optical Networks. He has been with the Department of Electrical and Computer Engineering at Queen’s University (1979-2002), where he was prior to his departure a Full Professor and the Department Associate Head. He has three years of industrial experience mainly at Bell Northern Research of Ottawa, now Nortel Networks (1977-79). He has spent three sabbatical years also at Nortel Networks (1986-87, 1993-94, and 2000-01), always conducting research in the area of broadband packet switching networks, mobile wireless networks and quality of service over the optical Internet. He served as Editor-in-Chief of the IEEE Communications Magazine (1995-97) and IEEE Communications Society Director of Magazines (1998-99) and Chair of the Awards Committee (2002-2003). He is a Distinguished Speaker of the IEEE Communications Society since 2000. Dr. Mouftah is the author or coauthor of five books, 22 book chapters and more than 700 technical papers and 8 patents in this area. He is the recipient of the 1989 Engineering Medal for Research and Development of the Association of Professional Engineers of Ontario (PEO), and the Ontario Distinguished Researcher Award of the Ontario Innovation Trust. He is the joint holder of the Best Paper Award for a paper presented at SPECTS’2002, and the Outstanding Paper Award for papers presented at the IEEE HPSR’2002 and the IEEE ISMVL’1985. Also he is the joint holder of a Honorable Mention for the Frederick W. Ellersick Price Paper Award for Best Paper in the IEEE Communications Magazine in 1993. He is the recipient of the IEEE Canada (Region 7) Outstanding Service Award (1995). Also he is the recipient of the 2004 IEEE Communications Society Edwin Howard Armstrong Achievement Award, and the 2004 George S. Glinski Award for Excellence in Research of the Faculty of Engineering, University of Ottawa. Dr. Mouftah is a Fellow of the IEEE (1990) and Fellow of the Canadian Academy of Engineering (2003).     

An Efficient Architecture for a Lifted 2D Biorthogonal DWT

This paper presents a new algorithm for a 2D non-separable lifted bi-orthogonal wavelet transform. The algorithm is derived by factoring complementary pairs of wavelet transform 2D filters. The results are efficient architectures for real time signal processing, which do not require transpose memory for the 2D processing of data. The proposed architecture exploits in place implementation, inherit from the algorithm, and can take advantage of both vertical and horizontal parallelism in the direct implementation. The processing in our architecture is scheduled by carefully pipelining the lifted steps, which allows for up to four times faster processing than the direct implementation. The proposed architecture operates at high speed, consumes low power and has reduced computational complexity as compared to previously published filter and lifted based bi-orthogonal wavelet architectures.M. Alam (Student) is currently M.Sc. student in the Department of Electrical and Computer Engineering at University of Calgary. His research interest includes VLSI signal processing. He is recipient of iCORE International Graduate Scholarship.Wael Badawy (Ph.D. 00, M.Sc 98, 97; B.Sc. 94) is an associate professor in the Department of Electrical and Computer Engineering. He holds an adjunct professor in the Department of Mechanical Engineering, University of Alberta.Dr. Badawys research interests are in the areas of: Microelectronics, VLSI architectures for video applications with low-bit rate applications, digital video processing, low power design methodologies, and VLSI prototyping. His research involves designing new models, techniques, algorithms, architectures and low power prototype for novel system and consumer products. Dr. Badawy authored and co-authored more than 100 peer reviewed Journal and Conference papers and about 30 technical reports. He is the Guest Editor for the special issue on System on Chip for Real-Time Applications in the Canadian Journal on Electrical and Computer Engineering, the Technical Chair for the 2002 International Workshop on SoC for real-time applications, and a technical reviewer in several IEEE journals and conferences. He is currently a member of the IEEE-CAS Technical Committee on Communication. Dr. Badawy was honored with the 2002 Petro Canada Young Innovator Award, 2001 Micralyne Microsystems Design Award and the 1998 Upsilon Pi Epsilon Honor Society and IEEE Computer Society Award for Academic Excellence in Computer Disciplines. He is currently the Chairman of the Canadian Advisor Committee (CAC) and Head of the Canadian Delegation on ISO/IEC/JTC1/SC6 Telecommunications and Information Exchange Between Systems. Member, The Canadian Advisory Committee for the Standards Council of Canada-Subcommittee 29: Coding of Audio, Picture Multimedia and Hypermedia Information, and Canadian Delegate, The ISO/IEC MPEG standard committee. He is a voting Member on the VSI Alliance. He is also the Chair of the IEEE-Southern Alberta Society-Computer Chapter.Vassil S. Dimitrov was born in Plovdiv, Bulgaria, in 1964. He received his Ph.D. degree in mathematics in 1995 from the Mathematical Institute of the Bulgarian Academy of Sciences. Since then, he has spent two years as a postdocral fellow at the VLSI Research Group, University of Windsor, Canada, one year as a research scientist at the Reliable Software Technology Corporation, Virginia, USA, one year as a chief research scientist at the Signal Processing and Computer Technology Laboratory, Helsinki University of Technology, Finland, and one year as an Associate Professor at the University of Windsor, Canada. Since July 2001 he has held the position of Associate Professor at the Department of Electrical and Computer Engineering, University of Calgary, Canada. His main interests are in the area of number theoretic algorithms, computational complexity, cryptography, optimization theory, fast algorithms for digital signal processing and related topics. Dr. Dimitrov is a member of the New York Academy of Sciences.Graham Jullien (Fellow IEEE) was educated in the United Kingdom, receiving degrees, in Electrical Engineering, from the Universities of Loughborough, Birmingham and Aston (Ph.D., 1969). He was a student engineer and data processing engineer at English Electric Computers, UK, from 1961 to 1966, and a visiting senior research engineer at the Central Research Laboratories of EMI Ltd., UK, from 1975 to 1976. From 1969 until 2000 he was with the Department of Electrical and Computer Engineering at the University of Windsor, Ontario, Canada, where he held the rank of University Professor and was the Director of the VLSI Research Group. Since January 2001, he has been with the Department of Electrical and Computer Engineering at the University of Calgary, where he holds the iCORE Research Chair in Advanced Technology Information Processing Systems. He is a member of the Board of Directors of the Canadian Microelectronics Corporation (CMC) and is a member of the Steering Committee and Board of Directors of the Micronet Network of Centres of Excellence. He has published widely in the fields of Digital Signal Processing, Computer Arithmetic, Neural Networks and VLSI Systems, and teaches courses in related areas. He has served on the technical committees of many international conferences; he currently serves on the Editorial Board of the Journal of VLSI Signal Processing; and is a past Associate Editor of the IEEE Transactions on Computers. He hosted and was program co-chair of the 11th IEEE Symposium on Computer Arithmetic, was program chair for the 8th Great Lakes Symposium on VLSI, and was the technical program chair for the 1999 Asilomar Conference on Signals, Systems and Computers. He is general chair for the 2003 Asilomar Conference and general co-chair of the International Workshop on System-on-Chip for Real-Time Systems, Calgary, Alberta 2003.     

Algorithm design for a class of base station location problems in sensor networks

Base station placement has significant impact on sensor network performance. Despite its significance, results on this problem remain limited, particularly theoretical results that can provide performance guarantee. This paper proposes a set of procedure to design (1− ε) approximation algorithms for base station placement problems under any desired small error bound ε > 0. It offers a general framework to transform infinite search space to a finite-element search space with performance guarantee. We apply this procedure to solve two practical problems. In the first problem where the objective is to maximize network lifetime, an approximation algorithm designed through this procedure offers 1/ε² complexity reduction when compared to a state-of-the-art algorithm. This represents the best known result to this problem. In the second problem, we apply the design procedure to address base station placement problem when the optimization objective is to maximize network capacity. Our (1− ε) approximation algorithm is the first theoretical result on this problem. Yi Shi received his B.S. degree from University of Science and Technology of China, Hefei, China, in 1998, a M.S. degree from Institute of Software, Chinese Academy of Science, Beijing, China, in 2001, and a second M.S. degree from Virginia Tech, Blacksburg, VA, in 2003, all in computer science. He is currently working toward his Ph.D. degree in electrical and computer engineering at Virginia Tech. While in undergraduate, he was a recipient of Meritorious Award in International Mathematical Contest in Modeling and 1997 and 1998, respectively. His current research focuses on algorithms and optimizations for wireless sensor networks, wireless ad hoc networks, UWB-based networks, and SDR-based networks. His work has appeared in journals and highly selective international conferences (ACM Mobicom, ACM Mobihoc, and IEEE Infocom). Y. Thomas Hou received the B.E. degree from the City College of New York in 1991, the M.S. degree from Columbia University in 1993, and the Ph.D. degree from Polytechnic University, Brooklyn, New York, in 1998, all in Electrical Engineering. Since Fall 2002, he has been an Assistant Professor at Virginia Tech, the Bradley Department of Electrical and Computer Engineering, Blacksburg, VA. His current research interests are radio resource (spectrum) management and networking for software-defined radio wireless networks, optimization and algorithm design for wireless ad hoc and sensor networks, and video communications over dynamic ad hoc networks. From 1997 to 2002, Dr. Hou was a Researcher at Fujitsu Laboratories of America, Sunnyvale, CA, where he worked on scalable architectures, protocols, and implementations for differentiated services Internet, service overlay networking, video streaming, and network bandwidth allocation policies and distributed flow control algorithms. Prof. Hou is a recipient of an Office of Naval Research (ONR) Young Investigator Award (2003) and a National Science Foundation (NSF) CAREER Award (2004). He is a Co-Chair of Technical Program Committee of the Second International Conference on Cognitive Radio Oriented Wireless Networks and Communications (CROWNCOM 2007), Orlando, FL, August 1–3, 2007. He also was the Chair of the First IEEE Workshop on Networking Technologies for Software Defined Radio Networks, September 25, 2006, Reston, VA. Prof. Hou holds two U.S. patents and has three more pending. Alon Efrat earned his Bachelor in Applied Mathematics from the Technion (Israel’s Institute of Technology) in 1991, his Master in Computer Science from the Technion in 1993, and his Ph.D in Computer Science from Tel-Aviv University in 1998. During 1998–2000 he was a Post Doctorate Research Associate at the Computer Science Department of Stanford University, and at IBM Almaden Research Center. Since 2000, he is an assistant professor at the Computer Science Department of the University of Arizona. His main research areas are Computational Geometry, and its applications to sensor networks and medical imaging.     

A CMOS Image Processing Sensor for the Detection of Image Features

A compact CMOS vision sensor for the detection of higher level image features, such as corners, junctions (T-, X-, Y-type) and linestops, is presented. The on-chip detection of these features significantly reduces the data amount and hence facilitates the subsequent processing of pattern recognition. The sensor performs a series of template matching operations in an analog/digital mixed mode for various kinds of image filtering operations including thinning, orientation decomposition, error correction, set operations, and others. The analog operations are done in the current domain. A design procedure, based on the formulation of the transistor mismatch, is applied to fulfill both accuracy and speed requirements. The architecture resembles a CNN-UM that can be programmed by a 30-bit word. The results of an experimental 16 × 16 pixel chip demonstrate that the sensor is able to detect features at high speed due to the pixel-parallel operation. Over 270 individual processing operations are performed in about 54 μsec. Masatoshi Nishimura was born in 1962 in Japan. He received his B.S. degree in mathematical engineering and information physics from the University of Tokyo in 1984. In 2001 he received his Ph.D. in Electrical Engineering from the University of Pennsylvania. His Ph.D. research focused on biologically inspired algorithms for the feature detection in visual images. Except for the three years he spent at University of Pennsylvania, he has been working for Sankyo since 1984, where he has been involved in the research and development of medical instruments including a microchip for capillary electrophoresis. He is currently working in the field of bioinformatics. Jan Van der Spiegel received his Masters and Ph.D. degrees in Electrical Engineering from the University of Leuven, Belgium, in 1974 and 1979, respectively. He joined the University of Pennsylvania in 1981 where he is currently a Professor of Electrical and Systems Engineering and the director of the Center for Sensor Technologies. He was the chairman of the Department of Electrical Engineering from 1998 to 2002 and the interim chairman of the Electrical and Systems Engineering department at the University of Pennsylvania from 2002 to 2004. His research interests are in mixed-mode VLSI design, biologically based sensors and sensory information processing systems, micro-sensor technology, and analog-to-digital converters. He is the author of over 150 journal and conference papers and holds 4 patents. He is a Fellow of the IEEE (2002) and the recipient of the IEEE Third Millennium Medal, the UPS Foundation Distinguished Education Chair and the Bicentennial Class of 1940 Term Chair. He received the Christian and Mary Lindback Foundation, and the S. Reid Warren Award for Distinguished Teaching. He was also Editor of Sensors and Actuators A for North and South America from 1983 to 2004.     

Simplified Modeling of a Multipole Amplifier Using All-Pass Network Functions

This paper presents a system model for the representation of amplifiers that cannot be accurately characterized by a classical two pole transfer function. The effects of higher order poles are modeled by an all-pass function added to the conventional two pole model. The accuracy of the model is demonstrated by comparing the results for a typical CMOS amplifier to those obtained from device level simulations using SPICE. This model can be easily implemented in a standard simulator and is shown to achieve fast simulation time. This model is expected to have application in system level modelling of mixed-signal circuits using conventional SPICE simulators.Yihong Dai received his B.S. and M.Eng. degrees in Electrical Engineering from Shanghai JiaoTong University, Shanghai, China in 1993 and 1996, respectively. From 1996 to 1998, he enjoyed his industrial experiences in Shanghai with semiconductor companies like Shanghai Nortel Semiconductor and Motorola Electronics (China) Shanghai Branch. Since 1998, he has been a research assistant at the Analog and Mixed-signal Laboratory of the Electrical Engineering Department of Brigham Young University working toward his Ph.D. During the summer of 1999, he was with AMI semiconductor Utah Research and Design Center where he developed a threshold voltage based CMOS voltage reference architecture. In the summer of 2001, he was with Ultra Design where he designed a reference amplifier for high speed digital-to-analog converters. His research interest includes voltage reference, reference amplifier and high speed data converters in both CMOS and GaAs processes.Donald T. Comer received the B.S, M.S., and Ph.D. degrees from San Jose State University, the University of California (Berkeley), and the University of Santa Clara, respectively, all in electrical engineering. He began teaching at San Jose State University in 1961 and mixed his teaching and industrial work until he left San Jose State University in 1979. He has worked for California Technical Industries, IBM Corp., Mobility Systems, Precision Monolithics, Storage Technology Corp., and Analog Devices during his career. He founded the AMI Utah Research and Design Center in 1998 that specializes in MOS design. In 2002, Dr. Comer founded Ultra Design, a design center that specializes in high-frequency heterojunction circuit designs. He holds fifteen patents and has published over 50 articles dealing with solid-state and integrated circuits. He has published five textbooks in the field of large-signal and integrated circuits. He formerly held the Quentin Berg Chair at Penn State Harrisburg from 1990 to 1995. He is now a professor of electrical and computer engineering at Brigham Young University where he held the Endowed Chair of Engineering from 1995 to 1998.David J. Comer received the B.S., M.S., and Ph.D. degrees from San Jose State University, the University of California (Berkeley), and Washington State University, respectively, all in electrical engineering. He has worked for IBM Corp., Pacific Electromagnetics, Lawrence Livermore Laboratories, and Intel Corporation. He began his teaching career at the University of Idaho and has taught at the University of Calgary and California State University, Chico. He is presently a professor of electrical and computer engineering at Brigham Young University. He served as Chairman of the Division (Dean) of Engineering at CSU, Chico and as Department Chair at BYU.While at CSU, Chico, Dr. Comer served on the statewide Engineering Liaison Committee and served as Chair of the Council of California State University Deans of Engineering.Dr. Comer has published twelve textbooks and over 60 articles in the field of circuit design. He has contributed sections to the Encyclopedia of Physical Science and Technology and holds seven patents. He was given the Professional Achievement Award at CSU, Chico and was named the Outstanding Teacher of Engineering at BYU. He has also held the College of Engineering Research Chair at Brigham Young University.Darren Korth received the B.S. and M.S. degrees in electrical engineering at Brigham Young University, Provo, Utah in 1999. He is currently pursuing a Ph.D. in electrical engineering. He served as an instructor for the Department of Electrical and Computer Engineering at Brigham Young University from 2000 to 2002. From 2001 to 2003, he also worked as a senior design engineer at UltraDesign, LLC, Provo, Utah where he researched high-speed data converter circuits. He is currently with AMI Semiconductor in their RF CMOS group.     

Effective Capacity-Based Quality of Service Measures for Wireless Networks

An important objective of next-generation wireless networks is to provide quality of service (QoS) guarantees. This requires a simple and efficient wireless channel model that can easily translate into connection-level QoS measures such as data rate, delay and delay-violation probability. To achieve this, in Wu and Negi (IEEE Trans. on Wireless Communications 2(4) (2003) 630–643), we developed a link-layer channel model termed effective capacity, for the setting of a single hop, constant-bit-rate arrivals, fluid traffic, and wireless channels with negligible propagation delay. In this paper, we apply the effective capacity technique to deriving QoS measures for more general situations, namely, (1) networks with multiple wireless links, (2) variable-bit-rate sources, (3) packetized traffic, and (4) wireless channels with non-negligible propagation delay. Dapeng Wu received B.E. in Electrical Engineering from Huazhong University of Science and Technology, Wuhan, China, in 1990, M.E. in Electrical Engineering from Beijing University of Posts and Telecommunications, Beijing, China, in 1997, and Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University, Pittsburgh, PA, in 2003. From July 1997 to December 1999, he conducted graduate research at Polytechnic University, Brooklyn, New York. During the summers of 1998, 1999 and 2000, he conducted research at Fujitsu Laboratories of America, Sunnyvale, California, on architectures and traffic management algorithms in the Internet and wireless networks for multimedia applications. Since August 2003, he has been with Electrical and Computer Engineering Department at University of Florida, Gainesville, FL, as an Assistant Professor. His research interests are in the areas of networking, communications, multimedia, signal processing, and information and network security. He received the IEEE Circuits and Systems for Video Technology (CSVT) Transactions Best Paper Award for Year 2001. Currently, he is an Associate Editor for the IEEE Transactions on Vehicular Technology and Associate Editor for International Journal of Ad Hoc and Ubiquitous Computing. He served as Program Chair for IEEE/ACM First International Workshop on Broadband Wireless Services and Applications (BroadWISE 2004); and as TPC member of over 20 conferences such as IEEE INFOCOM'05, IEEE ICC'05, IEEE WCNC'05, and IEEE Globecom'04. He is Vice Chair of Mobile and wireless multimedia Interest Group (MobIG), Technical Committee on Multimedia Communications, IEEE Communications Society. He is a member of the Award Committee, Technical Committee on Multimedia Communications, IEEE Communications Society. He is also Director of Communications, IEEE Gainesville Section. Rohit Negi received the B.Tech. degree in Electrical Engineering from the Indian Institute of Technology, Bombay, India in 1995. He received the M.S. and Ph.D. degrees from Stanford University, CA, USA, in 1996 and 2000 respectively, both in Electrical Engineering. He has received the President of India Gold medal in 1995. Since 2000, he has been with the Electrical and Computer Engineering department at Carnegie Mellon University, Pittsburgh, PA, USA, where he is an Assistant Professor. His research interests include signal processing, coding for communications systems, information theory, networking, cross-layer optimization and sensor networks.     

A Location-Aware Routing Protocol for the Bluetooth Scatternet

Bluetooth is a most promising technology for the wireless personal area networks and its specification describes how to build a piconet. Though the construction of scatternet from the piconets is left out in the specification, some of the existing solutions discuss the scatternet formation issues and routing schemes. Routing in a scatternet, that has more number of hops and relay nodes increases the difficulties of scheduling and consumes the bandwidth and power resources and thereby impacts on the performance of the entire network. In this paper, a novel routing protocol (LARP) for the Bluetooth scatternet is proposed, which reduces the hop counts between the source and the destination and reconstructs the routes dynamically using the location information of the Bluetooth devices. Besides, a hybrid location-aware routing protocol (HLARP) is proposed to construct the shortest routes among the devices with or without having the location information and degenerate the routing schemes without having any location information. Experimental results show that our protocols are efficient enough to construct the shortest routing paths and to minimize the transmission delay, bandwidth and power consumption as compared to the other protocols that we have considered. Chih-Yung Chang received the Ph.D. degree in Computer Science and Information Engineering from National Central University, Taiwan, in 1995. He joined the faculty of the Department of Computer and Information Science at Aletheia University, Taiwan, as an Assistant Professor in 1997. He was the Chair of the Department of Computer and Information Science, Aletheia University, from August 2000 to July 2002. He is currently an Associate Professor of Department of Computer Science and Information Engineering at Tamkang University, Taiwan. Dr. Chang served as an Associate Guest Editor of Journal of Internet Technology (JIT, 2004), Journal of Mobile Multimedia (JMM, 2005), and a member of Editorial Board of Tamsui Oxford Journal of Mathematical Sciences (2001--2005). He was an Area Chair of IEEE AINA'2005, Vice Chair of IEEE WisCom 2005 and EUC 2005, Track Chair (Learning Technology in Education Track) of IEEE ITRE'2005, Program Co-Chair of MNSA'2005, Workshop Co-Chair of INA'2005, MSEAT'2003, MSEAT'2004, Publication Chair of MSEAT'2005, and the Program Committee Member of USW'2005, WASN'2005, and the 11th Mobile Computing Workshop. Dr. Chang is a member of the IEEE Computer Society, Communication Society and IEICE society. His current research interests include wireless sensor networks, mobile learning, Bluetooth radio systems, Ad Hoc wireless networks, and mobile computing. Prasan Kumar Sahoo got his Master degree in Mathematics from Utkal University, India. He did his M.Tech. degree in Computer Science from Indian Institute of Technology (IIT), Kharagpur, India and received his Ph.D in Mathematics from Utkal University, India in April, 2002. He joined in the Software Research Center, National Central University, Taiwan and currently working as an Assistant Professor, in the department of Information Management, Vanung University, Taiwan, since 2003. He was the Program Committee Member of MSEAT'2004, MSEAT'2005, WASA'2006, and IEEE AHUC'2006. His research interests include the coverage problems, modeling and performance analysis of wireless sensor network and Bluetooth technology. Shih-Chieh Lee received the B.S. degree in Computer Science and Information Engineering from Tamkang University, Taiwan, in 1997. Since 2003 he has been a Ph.D. Students in Department of Computer Science and Information Engineering, Tamkang University. His research interests are wireless sensor networks, Ad Hoc wireless networks, and mobile/wireless computing.     

Performance Simulation of a Microwave Micro-Electromechanical System Shunt Switch Using Chatoyant

In this paper we demonstrate the capabilities of our mixed-signal, multi-domain system level simulation tool, Chatoyant, to model and simulate an RF MEMS shunt switch. We verify our mechanical simulations and analysis by comparison to results from commercial simulation packages, ANSYS and CoventorWare. We show that our modeling accuracy and simulation speed are comparable to these commercial tools for specific analysis. We conclude by showing the unique capabilities of a system tool based on a modular hierarchal approach that allows one to model not only the individual components of the system but also the subtle interactions resulting in specific system behaviors.Michael Bails received his B.A. in Economics from the University of Vermont in 1995 and a B.S. in Electrical Engineering from the University of Pittsburgh in 2002 (cum laude). He worked as an undergraduate researcher in optical MEMS for Benchmark Photonics, a Pittsburgh-based start-up company from 2001 to 2002. Mr. Bails is currently pursuing his M.S. in the Department of Electrical and Computer Engineering at the University of Pittsburgh, where he is a recipient of the Rath Fellowship. His interests are in MEMS modeling with an emphasis on statistical process variations. Mr. Bails is a student member of IEEE.José A. Martínez is an Electrical Engineering Ph.D. student at the University of Pittsburgh. He received his MS from the University of Pittsburgh (2000) in Electrical Engineering. He received the BS (magna cum laude) in Electrical Engineering from the Universidad de Oriente (UDO), Venezuela, in 1993. Mr. Martínez was granted the José Feliz Rivas’ medal for high academic achievement by the Venezuelan government (1993), and scholarships by the Venezuelan Fundayacucho Society (1993) and CONICIT-UDO (1994) institution. Since 1997 he has been working in the Optoelectronic computing group at the University of Pittsburgh. His research interests include behavioral simulation, reduction order techniques, modeling of MEMs and OMEMs, CAD, VLSI and computer architecture. Mr. Martínez is a member of IEEE/LEOS, and OSA.Steven P. Levitan is the John A. Jurenko Professor of Computer Engineering in the Department of Electrical and Computer Engineering. He received the B.S. degree from Case Western Reserve University in 1972. From 1972 to 1977 he worked for Xylogic Systems designing hardware for computerized text processing systems. He received his M.S. and Ph.D. in Computer Science from the University of Massachusetts, Amherst. During that time he also worked for Digital Equipment Corporation, and Viewlogic Systems, as a consultant in HDL simulation and synthesis. He was an Assistant Professor from 1984 to 1986 in the Electrical and Computer Engineering Department at the University of Massachusetts. In 1987, Dr. Levitan joined the Electrical Engineering faculty at the University of Pittsburgh where he holds a joint appointment in the Department of Computer Science. He is Past Chair of the ACM Special Interest Group on Design Automation (SIGDA). He was awarded the ACM/SIGDA Distinguished Service Award for over a decade of service to ACM/SIGDA and the EDA Industry in 2002. He is on the technical advisory board for The Technology Collaborative. He is a senior member of the IEEE/Computer Society and a member of the Optical Society of America, the Association for Computing Machinery, and the International Society for Optical Engineering. He is a member of the ACM/IEEE Design Automation Conference Executive Committee.Jason Boles received the B.S. degree in computer engineering from the University of Pittsburgh, Pittsburgh, PA, in 2001, where he is currently pursuing the M.S. degree in electrical engineering. His research interests include hardware acceleration techniques for simulation, system level modeling, computer-aided design (CAD), as well as systems-on-chip design and verification. Mr. Boles is a student member of IEEE.Ilya V. Avdeev is currently with ANSYS, Inc (Canonsburg, PA). He received his B.S. and M.S. degrees both in mechanical engineering from St. Petersburg State Polytechnical University (Russia) in 1997 and 1999 respectively. He received his Ph.D. in mechanical engineering from the University of Pittsburgh in 2003. His dissertation was on modeling strongly-coupled MEMS. He has been an inaugural John Swanson Doctoral Fellow and was awarded numerous scholarships and personal grants during his undergraduate and graduate studies. His research interests include mathematical modeling of coupled-field effects, new finite element techniques and methods, design and simulation of MEMS/NEMS, and acoustics. He is a member of ASME and IEEE.Michael R. Lovell is the Associate Dean for Research and an Associate Professor of Industrial and Mechanical Engineering in the School of Engineering at the University of Pittsburgh. Dr. Lovell received his PhD in Mechanical Engineering in 1994 from the University of Pittsburgh. He joined the Mechanical Engineering Department at Pittsburgh in January of 2000 after three years of service as an Assistant Professor at the University of Kentucky and four years of service as a senior development engineer at ANSYS Inc. Professor Lovell is a W. K. Whiteford Endowed Faculty Fellow, has served as the Executive Director of the Swanson Center for Product Innovation since May of 2000, and has been the Director of the Swanson Institute for Technical Excellence since September of 2002. Among his accomplishments, Professor Lovell is a recipient of the NSF CAREER award (1997), the SME Outstanding Young Manufacturing Engineer Award (1999), and won the FAG Outstanding International Publication on Bearings (1998). Dr. Lovell’s primary research interests are in the areas of tribology, advanced computation, and micro and nano systems.Donald M. Chiarulli, Professor of Computer Science. Dr. Chiarulli received his BS degree (Physics, 1976) from Louisiana State University, MSc (Computer Science, 1979) from Virginia Polytechnic Institute, and PhD (Computer Science, 1986) from Louisiana State University. He was an Instructor/Research Associate at LSU from 1979 to 1986, and has been at the University of Pittsburgh since 1986. Dr. Chiarulli’s research interests are in photonic and optoelectronic computing systems architecture. Dr Chiarulli’s research has been recognized with Best Paper Awards at the International Conference on Neural Networks (ICNN-98) and the Design Automation Conference (DAC-00). He is also the co-inventor on three patents relating to computing systems and optoelectronics. He has served on the technical program committees of numerous conferences for both research and education issues. Dr. Chiarulli serves on the editorial board of the Journal of Parallel and Distributed Systems and is a member of the IEEE. SPIE, and OSA.