Component-Efficient Multiphase Switched-Capacitor DC–DC Converter With Configurable Conversion Ratios for LCD Driver Applications

A CMOS 3/4-phase switched capacitor dc-dc converter with configurable conversion ratios of $4times/5times/6times/7times$ is proposed for liquid crystal display driver applications. The 3/4-phase driving scheme requires only 3 off-chip flying capacitors and 5 package pins. The converter core, input voltage monitor, 3/4-phase clock generator and bandgap voltage reference were integrated using a 0.35- $mu$m high-voltage CMOS process. The input voltage ranges from 2.5 to 5 V, and the output voltage is higher than 15 V with a load current of 500 $mu$A. Measurement results confirmed the validity and performance of the driving scheme.      

Dual-Mode Multiple-Band Digital Controller for High-Frequency DC–DC Converter

An integrated digital controller design for dc-dc converter is proposed in this paper. The proposal presents a multiple- band dual-stage (MBDS) delay line A/D converter (ADC) for wide dynamic range of operation with reduced ripple, chip area, and power consumption. This proposal also introduces a novel folding logic for digital error calculation and dual-mode error control PID for improving transient response. A complete closed-loop experimental prototype is demonstrated on a field-programmable-gate- array-based setup. The feasibility and functionality of the proposed digital controller is verified with a closed-loop synchronous buck converter prototype that switches at 1 MHz and regulates over a wide output voltage range of 1.6-3.3 V. The proposed MBDS delay line ADC is fabricated with discrete logic gates and flip-flops. The integrated digital controller is also implemented using standard cell-based design methodology in 0.5-mum CMOS technology. The design reduces 33 % on-chip area compared to an equivalent of 64 tap delay line ADC. The complete digital controller chip takes less than 0.7 mm² of silicon area and consumes an average current of 92 muA at 1-MHz switching frequency. The voltage-mode digital loop achieves tracking time of less than 10 mus for 1-V step change of the reference voltage and settling time of 20 mus. Post layout simulation and experimental results are demonstrated.     

A Novel High-Frequency Transformer-Linked Soft-Switching Half-Bridge DC–DC Converter With Constant-Frequency Asymmetrical PWM Scheme

This paper presents a novel soft-switching half-bridge dc–dc converter with high-frequency link. The newly proposed soft-switching dc–dc converter consists of a single-ended half-bridge inverter controlled by an asymmetrical pulsewidth-modulation scheme and a center-tapped diode rectifier. In order to attain the wide range of soft commutation under constant switching frequency, the single active edge-resonant snubber cell composed of a lossless inductor and a switched capacitor is employed for the half-bridge inverter leg, providing and assisting zero-current-switching operations in the switching power devices. The practical effectiveness of the proposed soft-switching dc–dc converter is demonstrated by the experimental results from an 800 W–55 kHz prototype. In addition, the feasibility of the dc–dc converter topology is proved from the viewpoints of the high efficiency and high power density.      

Step-Up/Step-Down DC–DC ZVS PWM Converter With Active Clamping

This paper presents a regenerative step-up/step-down DC-DC zero-voltage-switching pulsewidth-modulation converter with active clamping. The switch losses are reduced due to the implementation of a simple active snubber circuit that provides soft commutation in all the switches of the converter. The theoretical analysis, basic equations, design methodology, and experimental results are shown in this paper. A control methodology to assure the output voltage regulation is also proposed. The main advantages of the proposed power converter are the small number of components, simplicity of the controller, robustness, small weight and size, and high efficiency.     

Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation

A dual-branch 1.8 V to 3.3 V regulated switched-capacitor voltage doubler with an embedded low dropout regulator is presented. For the power stage, the power switches are individually controlled by their phase signals using a phase-delayed gate drive scheme, and are turned on and off in proper sequence to eliminate both short-circuit and reversion currents during phase transitions. For the regulator, the two branches operate in an interleaving fashion to achieve continuous output regulation with small output ripple voltage. Dual-loop feedback capacitor multiplier is adopted for loop compensation and a P-switch super source follower with high current sinking capability is inserted to drive switching capacitive load, and push the pole at the gate of the output power transistor to high frequency for better stability. The regulated doubler has been fabricated in a 0.35 $mu{hbox {m}}$ CMOS process. It operates at a switching frequency of 500 kHz with an output capacitor of 2 $muhbox{F}$ , and the maximum output voltage ripple is only 10 mV for a load current that ranges from 10 mA to 180 mA. The load regulation is 0.0043%/mA, and the load transient is 7.5 $mu{hbox {s}}$ for a load change of 160 mA to 10 mA, and 25 $mu{hbox {s}}$ for a load change of 10 mA to 160 mA.      

An Integrated Switching DC–DC Converter With Dual-Mode Pulse-Train/PWM Control

This brief presents an integrated switching converter with a dual-mode control scheme. A pulse-train (PT) control employing a combination of four pulse control patterns is proposed to achieve optimal regulation performance under various operation scenarios. Meanwhile, a high-frequency pulsewidth modulation (PWM) control is adopted to ensure low output ripples and avoid digital limit cycling in steady state. The converter was fabricated with a 0.35- $muhbox{m}$ digital CMOS n-well process. The entire die area, including the on-chip pads and power devices, is 1.31 $hbox{mm}^{2}$ . Experimental results show that, in the steady state, the output voltage is well regulated at 1.5 V with $pm$12.5-mV ripples in the PWM mode. The measured maximum efficiency is 91%, and the efficiency stays above 70% within the entire 500-mW power range. In transient measurements, with a 100% load step change from 50 to 100 mA, the output voltage of the converter settles within 345 ns due to the fast response of the PT control, with a maximum voltage variation of 164 mV. The converter functions well when the input supply voltage frequently varies between 2.2 and 3.3 V, with a line regulation of 29.1 mV/V.      

A Three-Phase Current-Fed Push–Pull DC–DC Converter

In this paper, a new three-phase current-fed push–pull dc–dc converter is proposed. This converter uses a high-frequency three-phase transformer that provides galvanic isolation between the power source and the load. The three active switches are connected to the same reference, which simplifies the gate drive circuitry. Reduction of the input current ripple and the output voltage ripple is achieved by means of an inductor and a capacitor, whose volumes are smaller than in equivalent single-phase topologies. The three-phase dc–dc conversion also helps in loss distribution, allowing the use of lower cost switches. These characteristics make this converter suitable for applications where low-voltage power sources are used and the associated currents are high, such as in fuel cells, photovoltaic arrays, and batteries. The theoretical analysis, a simplified design example, and the experimental results for a 1-kW prototype will be presented for two operation regions. The prototype was designed for a switching frequency of 40 kHz, an input voltage of 120 V, and an output voltage of 400 V.      

Optimal PWM Control of Switched-Capacitor DC–DC Power Converters via Model Transformation and Enhancing Control Techniques

This paper presents an efficient and effective method for an optimal pulsewidth-modulated (PWM) control of switched-capacitor dc-dc power converters. Optimal switching instants are determined based on minimizing the output ripple magnitude, the output leakage voltage and the sensitivity of the output load voltage with respect to both the input voltage and the load resistance. This optimal PWM control strategy has several advantages over conventional PWM control strategies: 1) it does not involve a linearization, so a large-signal analysis is performed; and 2) it guarantees the optimality. The problem is solved via both the model transformation and the optimal enhancing control techniques. A practical example of the PWM control of a switched-capacitor dc-dc power converter is presented.     

Digital Predictive Feed-Forward Controller for a DC–DC Converter in Plasma Display Panel

This paper describes a new digital control method to enhance the dynamic performance of a dc-dc converter used in plasma display panel (PDP). A simple digital PID compensator with duty ratio feed-forward control is proposed to minimize the output voltage variation while the load current is continuously changing. The duty ratio feed-forward is calculated using noise-free load current information which is predicted by the available video data of the PDP. No separate current sensing circuit is required. A small signal z-domain feed-forward model is derived for the performance analysis and controller design. The proposed control method is experimentally verified on an asymmetrical half bridge dc-dc converter which supplies power to a 42 in PDP.     

Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters

A few simple switching structures, formed by either two capacitors and two-three diodes (C-switching), or two inductors and two-three diodes (L-switching) are proposed. These structures can be of two types: ldquostep-downrdquo and ldquostep-up.rdquo These blocks are inserted in classical converters: buck, boost, buck-boost, Cuk, Zeta, Sepic. The ldquostep-downrdquo C- or L-switching structures can be combined with the buck, buck-boost, Cuk, Zeta, Sepic converters in order to get a step-down function. When the active switch of the converter is on, the inductors in the L-switching blocks are charged in series or the capacitors in the C-switching blocks are discharged in parallel. When the active switch is off, the inductors in the L-switching blocks are discharged in parallel or the capacitors in the C-switching blocks are charged in series. The ldquostep-uprdquo C- or L-switching structures are combined with the boost, buck-boost, Cuk, Zeta, Sepic converters, to get a step-up function. The steady-state analysis of the new hybrid converters allows for determing their DC line-to-output voltage ratio. The gain formula shows that the hybrid converters are able to reduce/increase the line voltage more times than the original, classical converters. The proposed hybrid converters contain the same number of elements as the quadratic converters. Their performances (DC gain, voltage and current stresses on the active switch and diodes, currents through the inductors) are compared to those of the available quadratic converters. The superiority of the new, hybrid converters is mainly based on less energy in the magnetic field, leading to saving in the size and cost of the inductors, and less current stresses in the switching elements, leading to smaller conduction losses. Experimental results confirm the theoretical analysis.     

A Synchronous Multioutput Step-Up/Down DC–DC Converter With Return Current Control

This brief presents a new return-current control method for a multioutput step-up/down dc–dc converter. Compared with prior multioutput dc–dc converters, the presently described converter can generate outputs higher or lower than the input voltage with simple control-loop compensation while guaranteeing stability in a wide load range. Using a 0.5-$muhbox{m}$ bipolar CMOS (BiCMOS) process, a converter having five outputs has been implemented for an LG active-matrix organic light-emitting diode (AM-OLED) display panel. The implemented converter operates at 1-MHz switching frequency with 4.7- $muhbox{H}$ inductor and 10- $muhbox{F}$ capacitor. Experimental results show that the proposed control method can generate tightly regulated stepped-up or -down outputs stably under a wide load variation. The conversion efficiency is higher than 80% at a typical AM-OLED panel grey level.      

A Single-Inductor Switching DC–DC Converter With Five Outputs and Ordered Power-Distributive Control

An integrated five-output single-inductor multiple-output dc-dc converter with ordered power-distributive control (OPDC) in a 0.5 mum Bi-CMOS process is presented. The converter has four main positive boost outputs programmable from +5 V to +12 V and one dependent negative output ranged from -12 V to -5 V. A maximum efficiency of 80.8% is achieved at a total output power of 450 mW, with a switching frequency of 700 kHz. The performance of the converter as a commercial product is successfully verified with a new control method and proposed circuits, including a full-waveform inductor-current sensing circuit, a variation-free frequency generator, and an in-rush-current-free soft-start method. With simplicity, flexibility, and reliability, the design enables shorter time-to-market in future extensions with more outputs and different operation requirements.     

A Bidirectional DC–DC Converter for an Energy Storage System With Galvanic Isolation

This paper addresses a bidirectional dc-dc converter suitable for an energy storage system with an additional function of galvanic isolation. An energy storage device such as an electric double layer capacitor is directly connected to a dc side of the dc-dc converter without any chopper circuit. Nevertheless, the dc-dc converter can continue operating when the voltage across the energy storage device drops along with its discharge. Theoretical calculation and experimental measurement reveal that power loss and peak current impose limitations on a permissible dc-voltage range. This information may be useful in design of the dc-dc converter. Experimental results verify proper charging and discharging operation obtained from a 200-V, 2.6-kJ laboratory model of the energy storage system. Moreover, the dc-dc converter can charge the capacitor bank from zero to the rated voltage without any external precharging circuit.     

A Switching-Capacitor PWM DC–DC Converter and Its Variations

This paper proposes a novel switching-capacitor pulsewidth modulation (PWM) converter. The converter is a combination of a switching-capacitor converter and a PWM converter, and it has the following advantages: 1) zero-voltage switching of all the MOSFETs; 2) with an autotransformer self-driven method, there is no need to adjust the synchronous rectifier control timing, and this reduces body diode conduction loss; 3) its efficiency is not sensitive to the leakage inductor, so a discrete transformer can be used, and it is suitable for both voltage regulator module (VRM) and voltage regulator down (VRD) application; and 4) a single-phase option makes it more flexible, and it can achieve higher efficiency in the whole load range with a phase-shedding control strategy. A 700-kHz 1.2-V/35-A POL prototype and a four-phase 700-kHz 1.2-V/130-A-output VRM prototype were built to verify the analysis.      

Reaching High Power Density in Multikilowatt DC–DC Converters With Galvanic Isolation

In this paper, the possibility of reaching high power densities in multikilowatt dc-dc converters with galvanic isolation is demonstrated and the main design issues are discussed. The issues related to converter topology, transformer design, and thermal management are addressed, and new conceptual solutions are proposed. Implementing zero-voltage-switching quasi-zero-current-switching topology, optimized transformer design with leakage layer, and thermal management based on conduction enhanced by heat pipes at critical places resulted in very high power density and efficiency. The power density reached by the converter prototype is 11.13 kW/L with water cooling and 6.6 kW/L with air cooling. In the same time, the measured efficiency exceeded 97% in a broad load range. The new design concepts are demonstrated on a 50-kW converter prototype that was successfully tested at full-load conditions.     

Digital Peak Current Control for Switching DC–DC Converters With Asymmetrical Dual-Edge Modulation

An asymmetrical dual-edge modulation (ADM) method applied to digital peak current (DPC)-controlled switching dc–dc converters is proposed in this brief. Steady-state and transient performance comparison of DPC-controlled buck converters with ADM and conventional symmetrical dual-edge modulation (SDM) is presented and verified by experimental results. Comparison studies show that the steady-state and transient performances of DPC with ADM are better than those of DPC with SDM.      

A Fully Integrated 660 MHz Low-Swing Energy-Recycling DC–DC Converter

A fully integrated 0.18  $mu$ m DC–DC buck converter using a low-swing “stacked driver” configuration is reported in this paper. A high switching frequency of 660 MHz reduces filter components to fit on chip, but this suffers from high switching losses. These losses are reduced using: 1) low-swing drivers; 2) supply stacking; and 3) introducing a charge transfer path to deliver excess charge from the positive metal-oxide semiconductor drive chain to the load, thereby recycling the charge. The working prototype circuit converts 2.2 to 0.75–1.0 V at 40–55 mA. Design and simulation of an improved circuit is also included that further improves the efficiency by enhancing the charge recycling path, providing automated zero voltage switching (ZVS) operation, and synchronizing the half-swing gating signals.      

A Full-Bridge DC–DC Converter WithZero-Voltage-Switching Overthe Entire Conversion Range

A new topology of full-bridge dc–dc converter is proposed featuring zero-voltage-switching (ZVS) of active switches over the entire conversion range. In contrast to conventional techniques, the stored energy in the auxiliary inductor of the proposed converter is minimal under full-load condition and it progressively increases as the load current decreases. Therefore, the ZVS operation over the entire conversion range is achieved without significantly increasing full-load conduction loss making the converter particularly suitable in applications where the output is required to be adjustable over a wide range and load resistance is fixed (e.g., an electromagnet power supply). The principle of operation is described and the considerations in the design of converter are discussed. Performance of the proposed converter is verified with experimental results on a 500-W, 100-kHz prototype.      

A High-Efficiency DC–DC Converter Using 2 nH Integrated Inductors

Historically, buck converters have relied on high-Q inductors on the order of 1 to 100 muH to achieve a high efficiency. Unfortunately, on-chip inductors are physically large and have poor series resistances, which result in low-efficiency converters. To mitigate this problem, on-chip magnetic coupling is exploited in the proposed stacked interleaved topology to enable the use of small (2 nH) on-chip inductors in a high-efficiency buck converter. The dramatic decrease in the inductance value is made possible by the unique bridge timing of the stacked design that causes magnetic coupling to boost the converter's efficiency by reducing the current ripple in each inductor. The magnetic coupling is realized by stacking the two inductors on top of one another, which not only lowers the required inductance, but also reduces the chip area consumed by the two inductors. The measured conversion efficiency for the prototype circuit, implemented in a 130-nm CMOS technology, shows more than a 15% efficiency improvement over a linear converter for low output voltages rising to a peak efficiency of 77.9 % for a 0.9 V output. These efficiencies are comparable to converters implemented with higher Q inductors, validating that the proposed techniques enable high-efficiency converters to be realized with small on-chip inductors.     

Two-Parameter Discontinuity-Induced Bifurcation Curves in a ZAD-Strategy-Controlled DC–DC Buck Converter

The dynamics of a zero-average dynamic strategy controlled dc–dc Buck converter, modelled by a set of differential equations with discontinuous right-hand side is studied. Period-doubling and corner-collision bifurcations are found to occur close to each other under small parameter variations. Closer examination of the parameter space leads to the discovery of a novel bifurcation. This type of bifurcation has not been reported so far in the literature and it corresponds to a corner-collision bifurcation of a nonhyperbolic cycle. The bifurcation boundaries are computed analytically in this paper and the system dynamics are unfolded close to the novel bifurcation point.This paper was completed during a research period of all the authors at the CRM in Barcelona in March 2007.