Optimum crystallographic orientation of submicrometer CMOS devices operated at low temperatures

The dependence of submicrometer-channel CMOS performance on surface orientation is measured for LDD devices at both 300 and 77 K. Special emphasis is placed on determining the optimum crystalline plane for CMOS operating at low temperatures (CRYO-CMOS). A comparison of transistor parameters is experimentally made between     

Fully symmetric cooled CMOS on (110) plane

A cooled CMOS device using dual-polysilicon gates, (110) Si substrates, lightly doped drains with doping concentrations of 10¹⁴ cm^-2, and no channel implant is described. It is found that the peak mobility of a p⁺ polysilicon gate pMOS transistor on a (110) plane is 1.6 times larger than that on a (100) plane at 77 K. This pMOS transistor si very promising for use at 77 K because of its steeper subthreshold slope and higher hole mobility. The design has realized fully symmetrical cooled CMOS devices with 0.8-μm gates in which saturation currents and transductances of both n and pMOS transistors have been almost equalized. This fully symmetric cooled CMOS increases the ring oscillator speed by a factor of 1.2 and allows flexible CMOS circuit design that allows effective use of NOR gates     

Design and performance of 0.1-μm CMOS devices usinglow-impurity-channel transistors (LICT's)

0.1-μm CMOS devices using low-impurity-channel transistors (LICTs) with dual-polysilicon gates have been fabricated by nondoped epitaxial growth technology, high-pressure oxidation of field oxide, and electron-beam lithography. These devices, with gate lengths of 0.135 μm, achieved normal transistor operation at both 300 and 77 K using 1.5-V supply voltage. Maximum transconductances are 203 mS/mm for nMOS transistors and 124 mS/mm for pMOS transistors at 300 K. Low-impurity channels grown on highly doped wells provide low threshold voltages of about 0.35 V for nMOS transistors and about -0.15 V for pMOS transistors at 77 K, and preserve good turn-offs with subthreshold swings of 25 mV/decade at 77 K. LICTs suppress short-channel effects more effectively, compared with conventional devices with nearly uniform dopings     

Performance and physical mechanisms in SIMOX MOS transistorsoperated at very low temperature

The performance and the physical properties of SIMOX (separation by implantation of oxygen) MOS transistors are studied from room to liquid helium temperatures with particular emphasis on the behavior of carrier mobility, threshold voltage, subthreshold swing, leakage current, and kink effect. Various SIMOX substrates, such as partially depleted films annealed at low or high temperature and ultrathin films (100 nm), are analyzed and compared. Enhancement- and depletion-mode devices with different doping levels, channel lengths, and geometries are considered. The front and back channels are activated independently in order to assess the electrical quality of both interfaces. Comparison with bulk Si transistors reveals a number of interesting features of SIMOX devices, which are explained using comprehensive models. The advantages of low-temperature operation of SIMOX transistors are related to the decrease in subthreshold swing and leakage, increase in mobility, and reasonable shift of the threshold voltage. The performance of ultra-thin-film devices is excellent over the whole range or temperatures, whereas partially depleted transistors exhibit optimum performance at 77 K     

Enhanced transconductance in deep submicrometer MOSFET

It is shown that the enhanced transconductance observed in deep submicrometer MOSFETs at 77 and 300 K can be modeled using an extended drift-diffusion approximation with mobility parameters taken from measurements on MOSFETs of the 4-Mb DRAM generation. For the terminal characteristics of these devices, velocity overshoot is of little importance for devices with channel lengths larger than 60 nm     

Cut off frequency and transit time analysis of lightly doped drain (LDD) MOSFETs

Analytical model for the transconductance, cut off frequency, transit time and fringing capacitance of LDD MOSFETs is presented with a simple approach. The analysis is carried out considering the LDD device as a conventional MOSFET with a series resistance [Z.-H. Liu et al., Threshold voltage model for submicrometer MOSFETs. IEEE Trans Electron Devices 1993; ED-40: 86–94] and a simple closed form expressions for cut off frequency and transit time is obtained. The total gate capacitance, i.e. the geometric and fringing capacitance, is calculated for both LDD and non-LDD devices and lower fringing capacitance is reported in LDD devices. Lower cut-off frequencies and higher transit time are reported in LDD devices for the same channel length.     

On the profile design and optimization of epitaxial Si- andSiGe-base bipolar technology for 77 K applications. I. Transistor DCdesign considerations

The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for comparison. All four epitaxial-base profiles yield transistors with DC properties suitable for high-speed logic applications in the 77-K environment. The differences between the low-temperature DC characteristics of Si and SiGe transistors are highlighted both theoretically and experimentally. A performance tradeoff associated with the use of an intrinsic spacer layer to reduce parasitic leakage at low temperatures and the consequent base resistance degradation due to enhanced carrier freeze-out is identified. Evidence that a collector-base heterojunction barrier effect severely degrades the current drive and transconductance of SiGe-base transistors operating at low temperatures is provided     

Impact ionization MOS (I-MOS)-Part II: experimental results

Part I of this paper dealt with the fundamental understanding of device physics and circuit design in a novel transistor, based on the field-effect control of impact-ionization (I-MOS). This paper focuses on experimental results obtained on various silicon-based prototypes of the I-MOS. The fabricated p-channel I-MOS devices showed extremely abrupt transitions from the OFF state to the ON state with a subthreshold slope of less than 10 mV/dec at 300 K. These first experimental prototypes of the I-MOS also showed significant hot carrier effects resulting in threshold voltage shifts and degradation of subthreshold slope with repeated measurements. Hot carrier damage was seen to be much worse in nMOS devices than in pMOS devices. Monte Carlo simulations revealed that the hot carrier damage was caused by holes (electrons) underneath the gate in pMOS (nMOS) devices and, thus, consequently explained the difference in hot carrier effects in p-channel versus n-channel I-MOS transistors. Recessed channel devices were also explored to understand the effects of surfaces on the enhancement in the breakdown voltage in I-MOS devices. In order to reduce the breakdown voltage needed for device operation, simple p-i-n devices were fabricated in germanium. These devices showed much lower values of breakdown voltage and excellent matches to MEDICI simulations.     

A simple analytical model for the electrical characteristics of depletion-mode MOSFET's with application to low-temperature operation

A simple analytical model for depletion-mode MOSFET's is developed based on the gradual channel approximation and taking into account carrier freeze-out onto impurity sites implanted for threshold voltage modification. Theory is found to be in reasonable agreement with experimental results for n-channel depletion-mode MOSFET's at room temperature and at 77 K. It is shown that the common methods used for enhancement-mode devices to determine carrier channel mobility and threshold voltage, respectively, from the slope and voltage intercept of the current-gate voltage characteristics are invalid for depletion-mode devices. By comparison of enhancement and depletion devices on the same chip, it is shown that the processes associated with ion implantation had no effect on electron channel mobility at room temperature and caused at most a 25-percent reduction at 77 K. The model also is applicable to buried p-channel devices as used in CMOS technologies.     

A new LDD transistor with inverse-T gate structure

A new submicrometer inverse-T lightly doped drain (ITLDD) transistor structure for alleviating hot-electron effects is demonstrated. A thin extension of the polysilicon gate under the oxide sidewall spacer is formed, giving the gate cross section the appearance of an inverted letter T. Due to the unique self-aligned n+ T-to-gate feature facilitated by the conducting polysilicon extension, the "spacer-induced degradation" existing in a conventional LDD transistor is eliminated in ITLDD devices. This allows the use of low n- LDD doses for optimum channel electric field reduction and minimum post-implant drive-in for future VLSI compatibility. Submicrometer ITLDD transistors with good transconductance and hot-electron reliability have been achieved. The new ITLDD transistor offers a promising device structure for future VLSI applications.     

A total resistance slope-based effective channel mobilityextraction method for deep submicrometer CMOS technology

A simple yet effective total resistance slope-based method for extracting the effective channel mobility in deep submicrometer CMOS technology is developed. Using the slope of the measured total resistance versus mask length, the series resistance is removed from the measured total resistance, and mobility is extracted without involving the effective channel length. The new method facilitates mobility extraction in situations where the effective channel length is difficult to extract, such as in lightly-doped-drain (LDD) devices or at low temperatures. The new method also allows the series resistance to be any function of the gate bias, making the mobility extraction in LDD devices easier and more accurate     

Hot-carrier reliability in double-implanted lightly doped drain devices for advanced DRAMs

Hot-electron degradation in short-channel (0.50 mu m and 0.83 mu m) double-implanted lightly doped drain (DI-LDD) devices was characterised using DC stress tests. Compared to lightly doped drain (LDD) devices of the same effective channel length L/sub eff/, the measurements indicate that channel hot-electron injection is more prevalent in devices with the p/sup +/-pocket implant due to a higher peak channel electric field. Degradation is more severe in both the drain current and transconductance. However, an improvement in short-channel effects was seen in DI-LDD devices over LDD devices. For the same L/sub eff/, the punch-through voltage was higher and the subthreshold swing lower for the DI-LDD devices.<>     

DC performance of deep submicrometer Schottky-gated n-channel Si:SiGe HFETs at low temperatures

N-type Schottky-gated Si:SiGe heterostructure field-effect transistors with physical gate lengths between 70 and 450nm are characterized over a wide temperature range (T=10 K...300 K) for low electric fields. The room-temperature maximum low-field transconductance increases 61% to 440 mS/mm at T=10 K for the 70-nm device. The minimum subthreshold slope is 14...19 mV/dec at T=10 K. The off-state currents I/sub OFF/ are limited by parallel conduction at high temperatures and by the gate leakage current at low temperatures. Substrate leakage currents are found to be due to generation of carriers within the drain/substrate depletion layer and only make a minor contribution to I/sub OFF/. Operation of the devices at the lowest temperature is found to result in the occurrence of the floating-body kink effect, as a consequence of substrate freeze-out and subsequent self-biasing by impact ionization currents. Low temperature characteristics exhibit a nonlinear low-field drain current dependence on the drain voltage, due to the presence of parasitic Schottky source/drain contacts. An extraction method for access resistance consistent with this phenomenon is presented.     

重掺多晶氧化法LDD-CMOS高性能电路的优化设计与研制

对重掺多晶氧化法(HDPO)应用于LDD IC中的工艺条件进行了优化,并实现了HDPO-LDD电路.研究了HDPO-LDD器件的性能和热载流子效应,同时对器件进行计算机模拟,对HDPO-LDD进行优化设计,获得了优化参数.综合优化设计的工艺条件和参数,成功地应用于亚微米NMOSFET,1μm沟道长的CMOS CD4007电路,2μm沟道长的CMOS 21级环振和2.5μm沟道长的LSI CMOS IC,性能优良,高速,稳定,可靠.     

New understanding of LDD NMOS hot-carrier degradation and device lifetime at cryogenic temperatures

This work shows that the worst-case gate voltage stress condition for LDD nMOSFETs is a strong function of the channel length, drain voltage, and operating temperature. A new cross-over behavior of the worst-case gate voltage condition is reported at low temperatures. New understanding of the hot-carrier mechanisms at low temperatures is also discussed. Low temperature effects such as freeze-out are shown to have important contributions to the hot-carrier behavior at low temperatures. A trend is identified for the first time which suggests important consequences for the hot-carrier reliability of deep sub-micron channel length MOSFETs under normal operating temperatures.     

Optimization of LDD devices for cryogenic operation

The optimization of lightly doped drain (LDD) devices to maximize hot-carrier device lifetime at cryogenic temperature is studied. The hot-carrier-induced device degradation behavior and mechanisms of the various LDD and conventional devices are investigated. Carefully designed LDD devices can have better device reliability at low temperature compared to the conventional devices. However, the device lifetime is very short at low temperature for all the devices, and the difference in device lifetime between LDD and control devices is not appreciably large. The degradation behavior of both LDD and non-LDD devices at 77 K does not follow the simple behavior modeled by substrate current. For a given device, the maximum degradation is not observed at the bias condition for maximum substrate current. The optimum LDD design depends on the specific stressing bias conditions at 77 K     

Impact of the gate-drain overlapped device (GOLD) for deepsubmicrometer VLSI

The gate-drain overlapped device (GOLD) structure is proposed to achieve high reliability and high performance in deep submicrometer MOSFETs. The GOLD device concept is different from that of drain-engineering methods such as the double-diffused drain (DDD) and lightly doped drain (LDD). GOLD eliminates the tradeoff between transconductance and breakdown voltage (hot-carrier, drain sustaining). The overlap effect of the GOLD devices is discussed using simulation and experiment. GOLD has a gate structure using a native oxide film (5-10 A) to obtain an overlapped fine structure. The process is also compatible with conventional LDD processes and is suitable for 0.3-0.5-μm-design-rule devices at 5-V operation, and 3-V operation     

Performance and reliability evaluation of high dielectric LDDspacer on deep sub-micrometer LDD MOSFET

High dielectric LDD spacer has been proposed to achieve both reliability and performance improvement on the scaled LDD MOSFET's. However, the sidewall polyoxide and spacer bottom oxide required for process reliability issue will adversely limit the DC performance improvement gained by using high dielectric LDD spacer. AC performance is evaluated by the transconductance cutoff frequency determined by the transconductance, G_M and total gate capacitance, C_GG . For deep-submicron MOSFET's, the dominance of gate to source/drain overlap capacitance in C_GG has significant impact on the AC performance. The increase of C_GG due to the enhanced fringe field from high dielectric LDD spacer significantly dominates over the increase of transconductance, and then deteriorates the AC performance. As the reliability issue is concerned, the key doping profile, N^- source/drain lateral diffusion profile was obtained from the two dimensional process simulator SUPREM-IV corresponding to wide range of LDD N^- doses. The optimized N ^- dose designed for hot carrier reliability issue (under V _GS-V_T=0.5 V_DS operation) is located around 2×10¹³ cm^-2 for both conventional LDD (denoted as OLDD in this paper) and high dielectric LDD (HLDD) devices. However, the improvement achieved by using HLDD instead of OLDD devices is then turned out to be insignificant under this optimized N^- dose condition     

Design optimization of high-performance low-temperature 0.18 μmMOSFETs with low-impurity-density channels at supply voltage below 1 V

A 0.18 μm nMOS structure with a vertically nonuniform low-impurity-density channel (LIDC) at 77 K has been studied at supply voltage below 1 volt. An abrupt Gaussian profile is used in the channel. The investigation is based on two-dimensional (2-D) energy transport simulation with appropriate models to account for quantum and low-temperature freeze-out effects. The study focuses on achieving high driving capability and low off-current at low supply voltage and on minimizing short-channel effects. Some guidelines are proposed for improving device performance and suppressing short-channel effects of the LIDC MOS devices. It is shown that at 77 K the optimized nonuniform LIDC 0.18 μm nMOS structure with an abrupt impurity channel profile at supply voltage as low as 0.9 V is able to provide a saturation drain current comparable to that of a room-temperature LIDC 0.1 μm nMOS device at 1.5 V. Furthermore, the 77 K LIDC 0.18 μm nMOS consumes considerably lower dynamic and standby power than the room-temperature 0.1 μm nMOS. These results suggest that the LIDC MOS structure with an abrupt channel profile is very suitable for low-power and high-speed ULSI applications at low temperature