低开销片上网络容错传输机制

随着工艺的不断进步,片上网络可靠性问题越发严峻。为了平衡性能和功耗,研究者们提出了许多针对链路比特错误的传输机制,提出了一种基于纠错编码和重传方案的传输机制,在此机制中,路由器只提供对包头进行检验的检错器,并重用网络接口中的译码器对整个数据包进行纠错。通过使用轻量级的检错电路减少了硬件和功耗开销,并且保证时延开销与端到端和点到点的纠错方案相同。     

片上网络容错路由算法研究

随着集成电路制造工艺的不断发展,集成在芯片上晶体管的数量也随之增多,已超过几十亿晶体管的规模,因此芯片上可以集成越来越多的IP核。随着芯片中IP核数量的增多,基于总线结构的片上系统(System-on-Chip,So C)已不能满足数据的通信要求,为了解决这个问题,片上网络(Network-on-Chip,No C)作为一种全新的互联结构被提出来。其核心是把网络设计的思想移植到芯片设计中,将片上资源互连起来,并将计算与通信分离。片上网络具有很好的空间可扩展性,采用的全局异步一局部同步的通信机制使并行通信效率更高。NOC带来了一种全新的片上通信方式,它的引入有利于提升可重用设计、解决通信瓶颈和全局同步等难题。本文在研究片上网络结构的基础上,针对片上网络多播通信的特点提出了一种多播容错路由算法。     

片上网络容错技术研究

片上网络是一种全新的片上计算机体系结构,对片上网络的研究主要包括拓扑结构、路由算法、服务质量、交换机制、拥塞控制、能耗和容错等突出问题,其中对容错方法的研究一直是研究的重点。在软件改进和硬件改进方面,容错方法可以分为路由算法容错和路由器结构容错两类。分析当前已有容错方法的适用情况、实现原理和实现方法,并且分析其延迟、吞吐率、功耗等性能及其优缺点,对容错方法的现状进行剖析并且为容错方法的下一步研究提供研究方向。     

面向3维片上网络的轻量级细粒度容错机制

片上网络(networks-on-chip, NoC)是3维集成电路的主要通信技术之一.其中,路由器是3维片上网络的重要组成部件.现有的面向3维片上网络中路由器的容错技术,通常采取路由器整体冗余技术或者直接舍弃失效路由器的方法,这导致网络资源损失较为严重.提出一种面向3维片上网络的轻量级细粒度容错机制,充分利用故障路由器中仍能正常运行的有效资源,保障系统通信.提出的容错机制包括一种高可靠性路由器微体系结构设计和一种与之匹配的容错路由机制.通过实验对比和分析,相比较于已有的3维片上网络容错机制,提出的细粒度容错机制具备较高的通信性能和可靠性,同时面积和功耗开销较小.     

面向片上网络路由器FIFO故障的实时容错设计

为满足对片上网络路由器FIFO故障的实时容忍需求,设计了一种可实时检测路由器FIFO故障并对故障容忍的方法。首先建立了路由器FIFO的功能模型及故障模型,在此基础上利用测试地址在线生成法,提出了一种针对于片上网络路由器FIFO的故障实时检测算法,并提出利用FIFO重定向机制容忍FIFO故障。实验结果表明,对测试电路参数进行合理地设置,可将测试电路对路由器性能影响降到很小范围,且在故障条件下,吞吐率和延时得到较好的改善。     

一种可配置双向链路的片上网络容错偏转路由器

随着CMOS工艺进入纳米时代,工艺尺寸的不断缩小增加了集成电路对瞬态故障与永久故障的敏感性.在片上网络中提供容错支持对于提高单芯片多处理器片上数据传输的可靠性至关重要.为了处理片上网络中的瞬态故障与永久故障链路,提出一种可配置双向链路的容错偏转路由器BiFTDR.相邻BiFTDR路由器之间采用一对可配置方向的双向链路互连,根据链路的故障状态和路由器的到达包信息对双向链路的方向进行动态配置,在单向链路故障的情况下不需要绕道路由即可实现容错,并且不需要路由表从而降低了路由器的硬件实现开销.模拟结果表明,在合成通信模式下,网络中包含5条和15条永久故障链路的情况下,BiFTDR路由器的包平均延迟比一种基于强化学习的容错偏转路由器分别少10%和19%;在真实应用运行踪迹通信模式下,与无故障网络的包平均延迟相比,BiFTDR路由器的性能损失不到1%.对于瞬态故障,即使在高故障率下BiFTDR路由器的性能下降程度也较小.在65 nm工艺下对BiFTDR路由器进行综合,能达到500 MHz的时钟频率,并且具有较小的面积和功耗开销.     

基于前缀的片上网络容错源路由算法

为克服片上网络链路永久性错误带来的路由问题,提出一种基于前缀的片上网络容错源路由算法PFTSR。该算法适用于二维mesh片上网络,采用预测路径并根据反馈信息调整路径的方法进行路由探测。在仿真平台NIRGAM上进行仿真,实验结果表明,与传统片上网络容错源路由算法SRN相比,PFTSR极大降低了片上系统的功耗,并且在大多数情况下能减少探测到第一条路径的时间。     

面向片上网络容错偏转路由器设计与优化

随着集成电路工艺进入纳米时代,可靠性已成为片上网络设计的一个关键因素。本文设计实现了一种基于增强学习的片上网络容错偏转路由器,该路由器在发送包的同时采用增强学习的方法对路由表进行重配置以实现容错路由。为了提高性能,我们对路由器进行了流水线优化设计,采用2级流水线实现。在TSMC65nm工艺下综合结果表明,2级流水线路由器频率提升了近一倍达到750MHz,而面积开销仅增加了22%。在合成通信模式下的模拟结果表明,2级流水线容错偏转路由器的平均网络延迟优于无流水线路由器。     

片上网络故障模型及容错设计方法合理性分析

结合片上网络的硬件实现结构和先进工艺集成电路物理效应对片上网络存在的故障行为进行分析。进而对现的多种故障模型合理性进行了深入探讨,指出了其存在的缺陷及问题。在此基础上从故障产生的成因出发,对面向片上的容错多种设计方法进行了检讨和反思。通过本文的分析可以看出,需要在结合其自身硬件结构的基础上深入分析物理效应所引起的故障行为,才能有针对性的设计出真正高效、可靠的片上网络。     

一种片上网络的低延迟容错算法

为解决片上网络容错问题,利用端到端模式设计一种低延迟可靠传输算法。该算法利用发送端主动发送冗余数据包获得较小的延迟,将数据分成包集以提高链路利用率,进一步降低延迟。发送端只在收到接收端对当前包集的确认后才发送下一个包集的数据,由此保证高可靠性。通过不断发送数据包及端到端的反馈保证传输的正确性。NS-2仿真实验结果证明,该算法延迟低,片上通信可靠性高,可以有效处理传输过程中的瞬时错误。     

Load-Balancing Schemes for High-Throughput Distributed Fault-Tolerant Servers

Clusters of workstations, connected by a fast network, are emerging as a viable architecture for building high-throughput fault-tolerant servers. This type of architecture is more scalable and more cost-effective than a tightly coupled multiprocessor and may achieve as good a throughput. Two of the most important issues that a designer of such clustered servers must consider in order for the system to meet its fault-tolerance and throughput goals are the load-balancing scheme and the fault-tolerance scheme that the system will use. This paper explores several combinations of such fault-tolerance and load-balancing schemes and compares their impact on the maximum throughout achievable by the system, and on its survivability. In particular, we show that a fault-tolerance scheme may have an effect on the throughput of the system, while a load-balancing scheme may affect the ability of the system to override failures. We study the scalability of the different schemes under different loads and failure conditions. Our simulations take into consideration the overhead of each scheme, the network contention, and the resource loads.     

Bit-accurate energy estimation for Networks-on-Chip

Networks-on-Chip (NoCs) are recognized as the solution to address the communication bottleneck in a Multi-processor System-on-Chip (MPSoC). As NoCs represent a significant part of system consumption, MPSoC designers expect accurate power models in order to produce energy efficient systems. Nowadays, NoC simulators rely on power models that integrate link models without crosstalk modeling. In this study, we present Noxim-XT, a NoC simulator based on Noxim that embeds a link power model with crosstalk modeling. We show that the crosstalk effect has a deep impact on NoC energy consumption since our results demonstrate that classical models generate errors up to 45.5% on the whole NoC energy consumption estimation. In addition, this tool is able to run application-based traffic and we show that under application-based traffics, the energy estimation made by classical models overestimates the NoC energy consumption by up to 50%.     

Stochastic communication for application-specific Networks-on-Chip

In this paper, we have developed analytical stochastic communication technique for inter and intra-Networks-on-Chip (NoC) communication. It not only separates the computation and communication in Networks-in-Package (NiP) but also predicts the communication performance. Moreover, it will help in tracking of the lost data packets and their exact location during the communication. Further, the proposed technique helps in building the Closed Donor Controlled Based Compartmental Model, which helps in building Stochastic Model of NoC and NiP. This model helps in computing the transition probabilities, latency, and data flow from one IP to other IP in a NoC and among NoCs in NiP. From the simulation results, it is observed that the transient and steady state response of transition probabilities give state of data flow latencies among the different IPs in NoC and among the compartments of NoCs in NiP. Furthermore, the proposed technique produces low latency as compared to the latencies being produced by the existing topologies.     

用于片上网络的网络接口设计

提出一种用于由双通道路由器组成的片上网络系统的网络接口。该网络接口符合AMBA总线协议,能根据IP核的通信请求,自动选取通信方式,向IP核隐藏通信细节,充分利用双通道路由器中控制包通道与数据包通道分离的特点,方便系统编程。使用SMIC0．13gm工艺综合后,该网络接151的面积仅为0．3mm^2。     

Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip

In this paper, we propose two adaptive routing algorithms to alleviate congestion in the network. In the first algorithm, the routing decision is assisted by the number of occupied buffer slots at the corresponding input buffer of the next router and the congestion level of that router. Although this algorithm performs better than the conventional method, DyXY, in some cases the proposed algorithm leads to non-optimal decisions. Fuzzy controllers compensate for ambiguities in the data by giving a level of confidence rather than declaring the data simply true or false. To make a better routing decision, we propose an adaptive routing algorithm based on fuzzy logic for Networks-on-chip where the routing path is determined based on the current condition of the network. The proposed algorithm avoids congestion by distributing traffic over the routers that are less congested or have a spare capacity. The output of the fuzzy controller is the congestion level, so that at each router, the neighboring router with the lowest congestion value is chosen for routing a packet. To evaluate the proposed routing method, we use two multimedia applications and two synthetic traffic profiles. The experimental results show that the fuzzy-based routing scheme improves the performance over the DyXY routing algorithm by up to 25% with a negligible hardware overhead.     

多核结构片上网络性能-能耗分析及优化方法

文中探讨了片上网络在执行真实并行程序时的能耗和性能关系,并提出了一种能耗/性能优化方法.首先,文中提出了一种精确的性能-能耗模型,在性能和能耗模型中同时划分出与频率相关和与频率无关的因素,并分析其对性能和能耗的影响;其次,在性能-能耗模型中建立并行开销、片外访存开销与片上网络规模(节点数)、频率之间的关系,同时引入了并行度、通信模型等与应用相关的因素,使该模型能够同时表达软硬件特性;第三,文中提出了一种基于该性能-能耗模型的性能-能耗优化方法,通过采集程序的通信模型、访存消息数量等数据选择适当的频率和网络节点数来获得片上网络能耗最低值或处理器性能最大值.最后,文中采用8个PARSEC并行程序验证前述模型的准确性并评价性能-能耗优化方法,结果显示文中性能-能耗模型相比传统模型更加精确吻合实验测量结果,性能-能耗优化方法也有效适用于不同种类的并行程序.     

Analysis of worst-case backlog bounds for Networks-on-Chip

In networks-on-chips (NoCs), analyzing the worst-case backlog bounds of routers is very important to identify network congestions and improve network performance. In this paper, we propose a method called DiGB (DIrected-contention-Graph-based Backlog bound derivation) to analyze worst-case backlog bounds. For primitive scenarios, we propose analytical models for backlog bound derivation. For complex scenarios, we first construct a directed-contention-graph (DCG) to analyze the relationships among traffic flows. Then, we use the Breadth-First-Search strategy to traverse the DCG so that complex scenarios can be divided into primitive scenarios. Finally we compute the worst-case backlog bounds of each router. To illustrate this method, we present the derivation of closed-form formulas to compute the worst-case backlog bounds under all-to-one gather communication. The experimental results show that our method can achieve correct and tight worst-case backlog bounds.