A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors

A fine-grained reconfigurable architecture based on double gate technology is proposed and analyzed. The logic function operating on the first gate of a double-gate (DG) transistor is reconfigured by altering the charge on its second gate. Each cell in the array can act as logic or interconnect, or both, contrasting with current field-programmable gate array structures in which logic and interconnect are built and configured separately. Simulation results are presented for a fully depleted SOI DG-MOSFET implementation and contrasted with two other proposals from the literature based on directed self-assembly.     

Impact of Line-Edge Roughness on Double-Gate Schottky-Barrier Field-Effect Transistors

The impact of line-edge roughness (LER) on double-gate (DG) Schottky-barrier field-effect transistors (SBFETs) in the level of device and circuit was investigated by a statistical simulation. The LER sequence is statistically generated by a Fourier analysis of the power spectrum of the Gaussian autocorrelation function. The results show that SBFETs are more sensitive to the LER effect in the high-$V_{rm gs}$ region and less sensitive in the subthreshold region compared with DG FinFETs. The aggressive fluctuation of drive current can be attributed to the variation of tunneling barrier width. Lowering the Schottky-barrier height and increasing the silicon-body thickness can suppress the parameter fluctuations from the LER effect. The simulation also shows that a 6T SRAM cell consisting of SBFETs is more vulnerable to noise disturbance than its counterpart consisting of FinFETs, particularly for the read operation, which is due to a larger mismatch of drivability of SBFETs within the cell.      

应变硅电子迁移率解析模型

提出了一个应变硅沟道电子迁移率解析模型.模型以应变张量为对象研究应变硅沟道电子迁移率,因此与工艺相独立;适用于施加双轴应力及<100>/<110>方向单轴应力,沟道方向为<100>/<110>的器件;易于嵌入常用仿真工具中.     

应变硅NMOS晶体管沟道应变的模拟研究

建立了一种基于硅/锗硅异质结构的应变硅NMOS晶体管的有限元模型,通过模拟研究了沟道区的应变分布及其与器件参数的关系。结果表明,提高锗硅虚拟衬底中锗的摩尔组分、减小应变硅层厚度,可以增加沟道应变。此外,应变量还随器件结构长度的增加而增加。研究结果可为应变硅器件的设计、工艺优化提供参考依据。     

应变硅电子迁移率解析模型

提出了一个应变硅沟道电子迁移率解析模型.模型以应变张量为对象研究应变硅沟道电子迁移率,因此与工艺相独立;适用于施加双轴应力及<100>/<110>方向单轴应力,沟道方向为<100>/<110>的器件;易于嵌入常用仿真工具中.     

超深亚微米自对准平面双栅MOSFET假栅的制作

进入超深亚微米领域以后,传统CMOS器件遇到了器件物理、工艺技术等方面难以逾越的障碍.普遍认为,必须引入新结构和新材料来延长摩尔定律的寿命.其中,双栅CMOS被认为是新结构中的首选.在制作平面型双栅MOS器件中,采用自对准假栅结构,利用UHV外延得到有源区(S、D、G),是一种制作自对准双栅MOSFET的有效手段.文章详细研究了一种假栅制作技术.采用电子束曝光,结合胶的灰化技术,得到了线宽为50 nm的胶图形,并用RIE刻蚀五层介质的方法,得到了栅长仅为50 nm的自对准假栅结构.     

应变硅pMOS晶体管沟道应变的有限元研究

通过有限元方法,研究了一种采用SiGe源漏结构的pMOS晶体管中硅沟道的应变及其分布情况,模拟计算结果与利用会聚束电子衍射方法测量得到的数据能够较好地吻合,验证了模拟模型及方法的正确性。结果表明:提高源漏SiGe中的Ge组分、减小源漏间距、增加源漏的刻蚀深度和抬高高度,能有效增加沟道的应变量,为通过控制应变改善载流子迁移率提供了设计依据。     

双极双栅MOS晶体管静态特性解析模型的模拟与分析

提出了一种应用于VHF和UHF的新型功率电子器件－双极双栅MOS晶体管（BDGMOSFET）,该结构是在单栅MOSFET一侧引入双极型压控晶体管（BJMOSFET）,使之在正向工作时具有MOSFET和BJT的工作特性,通态电较小,同时,减少了寄生双极晶体管效应,改善了频率特性。文章对其静态特性的解析模型进行了详细研究,在该模型基础上运用通用电路模拟软件PSPICE的多瞬态分析法模拟了BDEMOSFET的直流特性,结果表明,在同等条件下,BDGMOSFET的电流密度比双栅MOSFET提高大约30％。     

Fabrication of Strained-Si/Strained-Ge Heterostructures on Insulator

Ultrathin strained-Si/strained-Ge heterostructures on insulator have been fabricated using a bond and etch-back technique. The substrate consists of a trilayer of 9 nm strained-Si/4 nm strained-Ge/3 nm strained-Si on a 400-nm-thick buried oxide. The epitaxial trilayer structure was originally grown pseudomorphic to a relaxed Si_0.5Ge_0.5 layer on a donor substrate. Raman analysis of the as-grown and final transferred layer structures indicates that there is little change in the strain in the Si and Ge layers after layer transfer. These ultrathin Si and Ge films have very high levels of strain (∼1.8% biaxial tension and 1.4% compression, respectively), and are suitable for enhanced-mobility field-effect transistor applications.     

薄膜全耗尽应变Si SOI MOSFET特性模拟与优化分析

研究了应变Si沟道引入对薄膜全耗尽SOI MOSHET器件特性的影响,并分析了器件特性改进的物理机理.与传统的SOI MOSFET结构相比,器件的驱动电流和峰值跨导都有明显提高,对n-FET分别为21%和16.3%,对p-FET为14.3%和10%.应变si沟道的引入还降低了器件的阈值电压,这有益于集成电路中供电电压的降低和电路功耗的减小.另外,本文还对新结构中的Ge含量进行了优化分析,认为当Ge含量为30%时,器件有较好的电特性,而且不会增加器件制作的工艺成本.     

Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

We demonstrate, for the first time, the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique. Our method uses the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs. Gate-all-around nand p-FETs, fabricated using these stacked NW arrays as the channel (L_gges0.35 mum), exhibit excellent device performance with high I_ON/I_OFF ratio (~10⁶), near ideal subthreshold slope (~62-75 mV/dec) and low drain induced barrier-lowering (~20 mV/V). The transconductance characteristics suggest quantum confinement of holes in the [Ge]-rich outer-surface of SiGe for p-FETs and confinement of electrons in the core Si with significantly less [Ge] for n-FETs. The presented device architecture can be a promising option to overcome the low drive current restriction of Si NW MOSFETs for a given planar estate     

Measurement of Channel Temperature in GaN High-Electron Mobility Transistors

In this paper, a simple and reliable method to estimate the channel temperature of GaN high-electron mobility transistors (HEMTs) is proposed. The technique is based on electrical measurements of performance-related figures of merit ($I_{{rm D}max}$ and $R_{rm ON}$) with a synchronized pulsed $I$ –$V$ setup. As our technique involves only electrical measurement, no special design in device geometry is required, and packaged devices can be measured. We apply this technique to different device structures and validate its sensitivity and robustness.      

Transparent Thin-Film Transistors Using ZnMgO as Dielectrics and Channel

An enhancement-mode ZnMgO transparent thin-film transistor (TFT) is fabricated, in which cubic-phase ZnMgO (C-ZnMgO) is used as gate insulator and hexagonal-phase ZnMgO (H-ZnMgO) is used as channel. The multilayers of C-ZnMgO and H-ZnMgO are grown on patterned indium-tin-oxide-coated glass in successive fashion at low temperature. Capacitor-voltage characteristics measured across the gate show that the H-ZnMgO channel is n-type. The C-ZnMgO isolating layer demonstrates low leakage current characteristics, i.e., 4 times 10^-7 A/cm², at a bias of 10 V. The transparent TFTs display a typical channel mobility of 1.5 cm² V^-1 s^-1 and an on/off ratio of 10⁴.     

基于In-Zn-Ti-O氧化物半导体材料的薄膜晶体管

在室温下制备了基于In-Zn-Ti-O氧化物半导体的薄膜晶体管,氧化物沟道层中In、Zn、Ti的摩尔比为49∶49∶2。所制备的器件场致迁移率达到9.8cm2/V.s,开关比大于105,亚阈值摆幅0.61V/dec。和未掺Ti器件的比较表明,掺Ti能使器件阈值正向变化,对场致迁移率也有提高作用。     

Low-Cost and Highly Manufacturable Strained-Si Channel Technique for Strong Hole Mobility Enhancement on 35-nm Gate Length pMOSFETs

Local strained-silicon channel pMOSFETs with minimum gate length down to 22 nm have been fabricated by integrating Ge preamorphization implantation (PAI) for source/drain (S/D) extension, which induces a uniaxial compressive stress in the channel to attain an enhanced pMOSFET performance without additional masks. A 43 % improvement of hole effective mobility has been obtained for 35-nm gate length pMOSFETs with an optimized Ge PAI condition for S/D extension at 1.1-MV cm vertical effective field, and the hole mobility improvement is nearly maintained at higher vertical field. The corresponding enhancement of a saturated drive current is 25 % at 1.3-MV ldr cm vertical field. The scaling strengthens the enhancement of the hole mobility remarkably. No negative effect on electron effective mobility is observed. An analysis by using a zero-order Laue zone diffraction on large angle convergent beam electron diffraction patterns in a transmission electron microscopy confirms that the significant residual compressive strain up to -3.0 % in the channel region is induced for 60-nm gate length strained channel pMOSFETs with the same optimized Ge PAI condition as that of 35-nm gate length pMOSFETs. The depth profiles of the residual compressive strain and shear strain in the channel region are given, respectively. The possible mechanisms are discussed.     

GaAs MESFET With a High-Mobility Self-Assembled Planar Nanowire Channel

We demonstrate the first metal–semiconductor field-effect transistor with a self-assembled planar $langlehbox{110}rangle$ GaAs nanowire channel. Well-defined dc output and transfer characteristics have been observed with a subthreshold slope of $sim$150 mV/dec, maximum $g_{m}$ of 23 mS/mm, and excellent on-current saturation. Bulklike mobility of $sim! hbox{4100} hbox{cm}^{2}/hbox{V}cdot hbox{s}$ with corresponding electron concentration of $hbox{2.3} cdot hbox{10}^{17} hbox{cm}^{-3}$ is derived by fitting the experimental data using a self-consistent long channel field effect device model.      

Si/Ge异质结双栅隧穿场效应晶体管TCAD仿真研究

Si/Ge异质结双栅隧穿场效应晶体管(DGTFET)较传统硅基DGTFET有更好的电学性能。文章基于Sentaurus TCAD仿真软件,构建了有/无Pocket两种结构的Si/Ge异质结DGTFET器件,定量研究了Pocket结构及Pocket区厚度、掺杂浓度等参数对器件开态电流、关态电流、亚阈值摆幅、截止频率和增益带宽积的影响。通过仿真实验和计算分析发现,Si/Ge异质结DGTFET的开态/关态电流、亚阈值摆幅、截止频率和增益带宽积随Pocket区掺杂浓度增大而增大,而Pocket区厚度对器件性能没有明显影响。研究结果为TFET器件的直流、频率特性优化提供了指导。     

Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness

A new method is proposed and successfully demonstrated for the fabrication of polycrystalline silicon (poly-Si) nanowire (NW) transistors with rectangular-shaped NW channels and two independent gates. The two independently controllable gates allow higher flexibility in device operation and provide a unique insight into the conduction mechanism of the NW device. Our results indicate that dramatic performance enhancement is feasible when the thickness of the NW channel is sufficiently thin, and the two conduction channels in the NW structure are operating simultaneously.      

Effect of Channel Width Shortening on the Stability of a-Si:H/nc-Si:H Bilayer Thin-Film Transistors

The static bias-stress-induced degradation of hydrogenated amorphous/nanocrystalline silicon bilayer bottom-gate thin-film transistors is investigated by monitoring the turn-on voltage (V _on) and on-state current (I _on) in the linear region of operation. Devices of constant channel length 10 mum and channel width varying from 3 to 400 mum are compared. The experimental results demonstrate that the device degradation is channel-width dependent. In wide channel devices, substantial degradation of V _on is observed, attributed to electron injection into the gate dielectric, followed by I _on reduction due to carrier scattering by the stress-induced gate insulator trapped charge. With shrinking the channel width down to 3 mum, the device stability is substantially improved due to the possible reduction of the electron thermal velocity during stress or due to the gate insulator quality uniformity over small dimensions.