High-frequency performance of subthreshold SOI MESFETs

Results from silicon-on-insulator (SOI) MESFETs designed for subthreshold operation are presented. The transistors have subthreshold slopes as low as 78 mV/dec and off-state drain currents approaching 1 pA//spl mu/m. Drain current saturation can be achieved with drain voltages of less than 0.5 V and with output impedance>100 M/spl Omega//spl middot//spl mu/m. The cutoff frequency of a 500-nm gate length device exceeds 1 GHz at currents significantly less than 1 /spl mu/A//spl mu/m. These results suggest that subthreshold SOI MESFETs might have useful applications in mixed-signal, micropower circuit design.     

An effect of the subthreshold current on scaled-down MOS dynamic RAMs

Data-output holding characteristics of MOS dynamic RAMs with 2.5 /spl mu/m design rules are studied by employing the hidden-RAS-only-refresh mode. It is verified that the noise voltage caused by internal circuit operation increases the subthreshold current and that the clamp circuitry effectively decreases the subthreshold current.     

A fully monolithic 260-/spl mu/W, 1-GHz subthreshold low noise amplifier

A micro-power complementary metal oxide semiconductor (CMOS) low-noise amplifier (LNA) is presented based on subthreshold MOS operation in the GHz range. The LNA is fabricated in an 0.18-/spl mu/m CMOS process and has a gain of 13.6 dB at 1 GHz while drawing 260 /spl mu/A from a 1-V supply. An unrestrained bias technique, that automatically increases bias currents at high input power levels, is used to raise the input P1dB to -0.2 dBm. The LNA has a measured noise figure of 4.6 dB and an IIP3 of 7.2 dBm.     

Modeling and sizing for minimum energy operation in subthreshold circuits

This paper examines energy minimization for circuits operating in the subthreshold region. Subthreshold operation is emerging as an energy-saving approach to many energy-constrained applications where processor speed is less important. In this paper, we solve equations for total energy to provide an analytical solution for the optimum V/sub DD/ and V/sub T/ to minimize energy for a given frequency in subthreshold operation. We show the dependence of the optimum V/sub DD/ for a given technology on design characteristics and operating conditions. This paper also examines the effect of sizing on energy consumption for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18-/spl mu/m test chip is used to compare normal sizing and sizing to minimize operational V/sub DD/ and to verify the energy models. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.     

Low-Voltage CMOS subthreshold log-domain filtering

This paper presents both a complete set of very low-voltage basic building blocks and a compact design methodology for log filtering in standard or even digital CMOS technologies. The new proposals are based on an alternative translinear loop principle for the MOSFET operating in its subthreshold region. Three different sets of complete basic building blocks are proposed along with all required auxiliary circuitry and a specific matrix design procedure to obtain stable and compact filter implementations. Also, all-MOS filter implementations following these circuit techniques are studied. Simulated and experimental examples are given at 1-V supply voltage for 1.2and 0.35-/spl mu/m CMOS technologies. The resulting circuit techniques are suitable to integrate very low-voltage low-power system-on-a-chip audio applications, such as hearing aids, in standard CMOS technologies.     

Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS

The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, control switching power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. With threshold voltage scaling, subthreshold leakage power is expected to become a significant portion of the total power in future CMOS systems. Therefore, it becomes crucial to predict and reduce subthreshold leakage power of such systems. In the first part of this paper, we present a subthreshold leakage power prediction model that takes into account within-die threshold voltage variation. Statistical measurements of 32-bit microprocessors in 0.18-/spl mu/m CMOS confirm that the mean error of the model is 4%. In the second part of this paper, we present the use of stacked devices to reduce system subthreshold leakage power without reducing system performance. A model to predict the scaling nature of this stack effect and verification of the model through statistical device measurements in 0.18-/spl mu/m and 0.13-/spl mu/m are presented. Measurements also demonstrate reduction in threshold voltage variation for stacked devices compared to nonstack devices. Comparison of the stack effect to the use of high threshold voltage or longer channel length devices for subthreshold leakage reduction is also discussed.     

A low-voltage low-power voltage reference based on subthreshold MOSFETs

In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-/spl mu/m CMOS technology, exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm//spl deg/C in the range -25 to +125/spl deg/C. A brief study of gate-source voltage behavior with respect to temperature in subthreshold MOSFETs is also reported.     

Study of 90-nm MOSFET subthreshold hump characteristics using newly developed MOSFET array test structure

We report 90-nm MOSFET subthreshold hump characteristics obtained for the first time by using a newly developed MOSFET array test structure. The array contains small-scale device-under-test groups with a new poly-Si gate layout pattern, which eliminates the influence of gate leakage and off leakage currents observed on measured MOSFET parameter data such as Vth, Ion, and subthreshold slope. We confirmed that subthreshold humps occur at random in an array. The rate at which humps occur is expressed as a percentage with respect to the whole array (referred to as the hump occurrence rate); the rate depends on chips from a wafer. It is also confirmed that the influence of subthreshold humps on /spl sigma/(Vth) is not negligible, and we revealed that it is important to design RF/analog circuits with an appropriate current density to reduce their influence. By extracting hump variations using a MOSFET array, it is possible to accurately estimate and reduce the standby current in logic large-scale integration (LSI) chips.     

Device optimization for digital subthreshold logic operation

Digital circuits operated in the subthreshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultralow power and medium frequency of operation. Although the implication of technology scaling on subthreshold operation is not obvious (since an obsolete technology node can deliver the same performance as a scaled technology in subthreshold), it has been shown that technology scaling helps to reduce the supply-voltage and, hence, the power consumption at iso-performance. It is possible to implement subthreshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, an Si MOSFET so optimized for performance in the super-threshold regime is not the best device to use in the subthreshold domain. We propose device designs apt for subthreshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the subthreshold region.     

Optical subthreshold current method for extracting the interface states in MOS systems

Optical subthreshold current method (OSCM) is proposed for characterizing the interface states in MOS systems using the current-voltage characteristics under a photonic excitation. An optical source with a subbandgap (E/sub ph/相似文献   

Double gate-MOSFET subthreshold circuit for ultralow power applications

In this paper, we propose MOSFETs that are suitable for subthreshold digital circuit operations. The MOSFET subthreshold circuit would use subthreshold leakage current as the operating current to achieve ultralow power consumption when speed is not of utmost importance. We derive the theoretical limit of delay and energy consumption in MOSFET subthreshold circuit, and show that devices that have an ideal subthreshold slope are optimal for subthreshold operations due to the smaller gate capacitance, as well as the higher current. The analysis suggests that a double gate (DG)-MOSFET is promising for subthreshold operations due to its near-ideal subthreshold slope. The results of our investigation into the optimal device characteristics for DG-MOSFET subthreshold operation show that devices with longer channel length (compared to minimum gate length) can be used for robust subthreshold operation without any loss of performance. In addition, it is shown that the source and drain structure of DG-MOSFET can be simplified for subthreshold operations since source and drain need not be raised to reduce the parasitic resistance.     

An analytical subthreshold current model for pocket-implanted NMOSFETs

An analytical subthreshold current model for metal oxide semiconductor field effect transistors (MOSFETs) with pocket implantation is presented. The model is developed based on considering an averaged localized pileup of channel dopants near the source and drain ends of channel to account for the pocket implantation effect and to derive the channel potential using a pseudo-two-dimensional (2-D) method. This, together with the conventional drift-diffusion theory, leads to the development of a subthreshold current model for pocket-implanted MOS devices. Model verification is carried out using data measured from a set of pocket-implanted NMOSFETs fabricated from a 0.17-/spl mu/m, DRAM process. Very good agreement is obtained between the model calculations and measurement results.     

Channel length independent subthreshold characteristics insubmicron MOSFETs

This work reports an anomalous subthreshold characteristic of the MOSFET for the first time. It is observed that the subthreshold characteristic does not change as the channel length decreases. The cause of channel length independent subthreshold characteristics is identified as the localized pileup of channel dopants near the source and drain ends of the channel. The low surface potential of this pileup region limits the subthreshold current of MOSFET. As a result, the ratio of on-current to off-current for this MOSFET increases as the channel length is reduced, which is an important parameter for low-voltage operation. It is found that a MOSFET with channel length independent subthreshold characteristic is more suitable for low-voltage operation     

A single-piece C∞-continuous MOSFET modelincluding subthreshold conduction

A simple yet powerful technique that transforms regional compact (algebraic) MOSFET models into single-piece C_∞-continuous models is introduced. The technique significantly improves MOSFET models by removing kinks and glitches at the boundaries between the subthreshold, triode, and saturation regions of operation. In addition, the technique adds subthreshold conduction modeling to models that lack such a capability. The authors show the technique by extending a simple MOSFET model, which is three piece and does not model subthreshold conduction, to become a single-piece model that includes subthreshold conduction     

high-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel

In this paper, we demonstrate for the first time a high-performance and high-reliability 80-nm gate-length dynamic threshold voltage MOSFET (DTMOS) using indium super steep retrograde channel implantation. Due to the steep indium super steep retrograde (In SSR) dopant profile in the channel depletion region, the novel In-SSR DTMOS features a low V/sub th/ in the off-state suitable for low-voltage operation and a large body effect to fully exploit the DTMOS advantage simultaneously, which is not possible with conventional DTMOS. As a result, excellent 80-nm gate length transistor characteristics with drive current as high as 348 /spl mu/A//spl mu/m (off-state current 40 nA//spl mu/m), a record-high Gm=1022 mS/mm, and a subthreshold slope of 74 mV/dec, are achieved at 0.7 V operation. Moreover, the reduced body effects that have seriously undermined conventional DTMOS operation in narrow-width devices are alleviated in the In-SSR DTMOS, due to reduced indium dopant segregation. Finally, it was found for the first time that hot-carrier reliability is also improved in DTMOS-mode operation, especially for In-SSR DTMOS.     

A true-1-V 300-/spl mu/W CMOS-subthreshold log-domain hearing-aid-on-chip

This paper presents a true very low-voltage low-power complete analog hearing-aid system-on-chip as a demonstrator of novel analog CMOS circuit techniques based on log companding processing and using MOS transistors operating in subthreshold. Low-voltage circuit implementations are given for all of the required functions including amplification and automatic gain control filtering, generation, and pulse-duration modulation. Based on these blocks, a single 1-V 300-/spl mu/A application specific integrated circuit integrating a complete hearing aid in a standard 1.2-/spl mu/m CMOS technology is presented along with exhaustive experimental data. To the authors' knowledge, the presented system is the only CMOS hearing aid with true internal operation at the battery supply voltage and with one of the lowest current consumptions reported in literature. The resulting low-voltage CMOS circuit techniques may also be applied to the design of A/D converters for digital hearing aids.     

Ultra-low-power DLMS adaptive filter for hearing aid applications

We present an ultra-low-power, delayed least mean square (DLMS) adaptive filter operating in the subthreshold region for hearing aid applications. Subthreshold operation was accomplished by using a parallel architecture with pseudo nMOS logic style. The parallel architecture enabled us to operate the system at a lower clock rate and reduced supply voltage while maintaining the same throughput. Pseudo nMOS logic operating in the subthreshold region (subpseudo nMOS) provided better power-delay product than subthreshold CMOS (sub-CMOS) logic. Simulation results show that the DLMS adaptive filter can operate at 22 kHz using a 400-mV supply voltage to achieve 91% improvement in power compared to a nonparallel, CMOS implementation. To validate the robust operation of subthreshold logics, a 0.35 /spl mu/m, 23.1 kHz, 21.4 nW, 8/spl times/8 carry save array multiplier test chip was fabricated where an adaptive body biasing scheme is used for compensating process, supply and temperature variations. The test chip showed stable operation at a supply voltage of 0.30 V, which is even lower than the threshold voltages of the pMOS (0.82 V) and nMOS (0.67 V) transistors.     

Translinear circuits in subthreshold MOS

In this paper we provide an overview of translinear circuit design using MOS transistors operating in subthreshold region. We contrast the bipolar and MOS subthreshold characteristics and extend the translinear principle to the subthreshold MOS ohmic region through a drain/source current decomposition. A front/back-gate current decomposition is adopted; this facilitates the analysis of translinear loops, including multiple input floating gate MOS transistors. Circuit examples drawn from working systems designed and fabricated in standard digital CMOS oriented process are used as vehicles to illustrate key design considerations, systematic analysis procedures, and limitations imposed by the structure and physics of MOS transistors. Finally, we present the design of an analog VLSI translinear system with over 590,000 transistors in subthreshold CMOS. This performs phototransduction, amplification, edge enhancement and local gain control at the pixel level.     

Optimized retrograde N-well for 1-/spl mu/m CMOS technology

Using experiment and simulation, transistors in a high-energy implanted N-well are designed for optimum device performance suitable for 1-/spl mu/m CMOS technology. The effect of process parameters on device performance is obtained. Superior body effect, junction capacitance, punchthrough voltage, and subthreshold slope are achieved for 1-/spl mu/m n- and p-channel transistors. With shallow P/P+ epitaxial material, this retrograde N-well approach also provides latch-up immunity for high-density CMOS.     

Bulk-drain connected load for subthreshold MOS current-mode logic

Bulk-drain connected PMOS transistors are proposed as loads for subthreshold MOS current-mode logic gates. Such loads exhibit an approximately linear dependence of the subthreshold drain-source current on the drain-source voltage, guaranteeing robust gate operation. The design and performance of an inverter gate and ring oscillator in a 0.25 mum CMOS technology are presented