A novel germanium doping method for fabrication of high-performance p-channel poly-Si/sub 1-x/Ge/sub x/ TFT by excimer laser crystallization

In this letter, a novel process for fabricating p-channel poly-Si/sub 1-x/Ge/sub x/ thin-film transistors (TFTs) with high-hole mobility was demonstrated. Germanium (Ge) atoms were incorporated into poly-Si by excimer laser irradiation of a-Si/sub 1-x/Ge/sub x//poly-Si double layer. For small size TFTs, especially when channel width/length (W/L) was less than 2 /spl mu/m/2 /spl mu/m, the hole mobility of poly-Si/sub 1-x/Ge/sub x/ TFTs was superior to that of poly-Si TFTs. It was inferred that the degree of mobility enhancement by Ge incorporation was beyond that of mobility degradation by defect trap generation when TFT size was shrunk to 2 /spl mu/m/2 /spl mu/m. The poly-Si/sub 0.91/Ge/sub 0.09/ TFT exhibited a high-hole mobility of 112 cm/sup 2//V-s, while the hole mobility of the poly-Si counterpart was 73 cm/sup 2//V-s.     

High-performance nonhydrogenated nickel-induced laterally crystallized P-channel poly-Si TFTs

High-performance nickel-induced laterally crystallized (NILC) p-channel poly-Si thin-film transistors (TFTs) have been fabricated without hydrogenation. Two different thickness of Ni seed layers are selected to make high-performance p-type TFTs. A very thin seed layer (e.g., 5 /spl Aring/) leads to marginally better performance in terms of transconductance (Gm) and threshold voltage (V/sub th/) than the case of a 60 /spl Aring/ Ni seed layer. However, the p-type poly-Si TFTs crystallized by the very thin Ni seeding result in more variation in both V/sub th/ and G/sub m/ from transistor to transistor. It is believed that differences in the number of laterally grown polycrystalline grains along the channel cause the variation seen between 5 /spl Aring/ NILC TFTs compared to 60-/spl Aring/ NILC TFTs. The 60 /spl Aring/ NILC nonhydrogenated TFTs show consistent high performance, i.e., typical electrical characteristics have a linear field-effect hole mobility of 156 cm/sup 2//V-S, subthreshold swing of 0.16 V/dec, V/sub th/ of -2.2 V, on-off ratio of >10/sup 8/, and off-current of <1/spl times/10/sup -14/ A//spl mu/m when V/sub d/ equals -0.1 V.     

Large grain poly-Si(/spl sim/rm 10/spl mu/m) TFTs prepared by excimer laser annealing through a thick SiON absorption layer

Poly-Si with large grain size of 10.4/spl times/4.4 /spl mu/m/sup 2/ was realized by excimer laser annealing (ELA) through the substrate and an 1 /spl mu/m thick silicon oxynitride (SiON) absorption layer underlying the top amorphous silicon. Thin-film transistors (TFTs) can then be made on this single poly-Si grain and show good electrical performance.     

Performance of poly-Si TFTs fabricated by SELAX

Selectively enlarging laser crystallization (SELAX) has been proposed as a new crystallization process for use in the fabrication of thin-film transistors (TFTs). This method is capable of producing a large-grained and flat film of poly-Si. The average grain size is 0.3/spl times/5 /spl mu/m, and the surface roughness of the poly-Si layer is less than 5 nm. The TFTs fabricated with this method have better performance and are more uniform than those produced with the conventional excimer laser crystallization (ELC) method. The average values of field-effect mobility are 440 cm/sup 2//Vs (n-type), and 130 cm/sup 2//Vs (p-type). The subthreshold slope for both types is 0.20 V/dec. Values for standard deviation of threshold voltage are 0.03 V (n-type) and 0.20 V (p-type). The delay time of the CMOS-inverter of SELAX TFTs is less than half that of ELC TFTs.     

High-performance poly-Si TFTs fabricated by implant-to-silicide technique

High-performance poly-Si thin-film transistors (TFTs) with fully silicided source/drain (FSD) and ultrashort shallow extension (SDE) fabricated by implant-to-silicide (ITS) technique are proposed for the first time. Using the FSD structure, the S/D parasitic resistance can be suppressed effectively. Using the ITS technique, an ultrashort and defect-free SDE can also be formed quickly at about 600/spl deg/C. Therefore, the FSD poly-Si TFTs exhibits better current-voltage characteristics than those of conventional TFTs. It should be noted that the on/off current ratios of FSD poly-Si TFT (W/L=1/4/spl mu/m) is over 3.3/spl times/10/sup 7/, and the field-effective mobility of that device is about 141.6 (cm/sup 2//Vs). Moreover, the superior short-channel characteristics of FSD poly-Si TFTs are also observed. It is therefore believed that the proposed FSD poly-Si TFT is a very promising TFT device.     

Stable polycrystalline silicon TFT with MICC

We studied the bias-induced changes in the performance of the poly-Si thin-film transistor (TFT) by metal-induced crystallization of amorphous silicon through a cap layer (MICC) poly-Si. The p-channel poly-Si TFT exhibited a field-effect mobility of 101 cm/sup 2//V/spl middot/s and a minimum leakage current of <1.0/spl times/10/sup -12/ A//spl mu/m at V/sub ds/=-10 V. The MICC poly-Si TFT performance changes little by either gate or hot-carrier bias stress. The better stability appears to be due to the smooth surface of MICC poly-Si, which is /spl sim/2 nm that is much smaller than that (13 nm) of a laser-annealed poly-Si.     

Elimination of poly-Si gate depletion for sub-65-nm CMOS technologies by excimer laser annealing

Pulsed excimer laser annealing (ELA) is used to reduce the poly-Si gate depletion effect (to <0.1 nm). Low resistivity (0.58 m/spl Omega//spl middot/cm) and high active boron concentration (4/spl times/10/sup 20/ cm/sup -3/) at the gate-oxide interface are achieved while preserving the gate oxide quality and avoiding boron penetration, to meet International Technology Roadmap for Semiconductors requirements for sub-65-nm CMOS technology nodes. ELA is compatible with high-/spl kappa/ dielectric (HfO/sub 2/) and results in significantly lower gate leakage current density as compared with rapid thermal annealing (RTA).     

A novel four-mask-processed poly-Si TFT fabricated using excimer laser crystallization of an edge-thickened a-Si active island

A four-mask-processed polycrystalline silicon thin-film transistor (poly-Si TFT) is fabricated using 50-pulse KrF excimer laser to crystallize an edge-thickened amorphous silicon (a-Si) active island without any shrinkage. This method introduces a temperature gradient in the island to enlarge grains from the edge, especially when the channel width is narrow. The grain boundaries across the width of the channel suppress the leakage current and the drain-induced barrier lowering. Moreover, the proposed poly-Si TFT with a channel length of L = 2 /spl mu/m and a channel width of W = 1.2 /spl mu/m possesses a high field-effect mobility of 260 cm/sup 2//Vs and an on/off current ratio of 2.31 /spl times/ 10/sup 8/.     

An ultrathin vertical channel MOSFET for sub-100-nm applications

An ultrathin vertical channel (UTVC) MOSFET with an asymmetric gate-overlapped low-doped drain (LDD) is experimentally demonstrated. In the structure, the UTVC (15 nm) was obtained using the cost-effective solid phase epitaxy, and the boron-doped poly-Si/sub 0.5/Ge/sub 0.5/ gate was adopted to adjust the threshold voltage. The fabricated NMOSFET offers high-current drive due to the lightly doped (<1/spl times/10/sup 15/ cm/sup -3/) channel, which suppresses the electron mobility degradation. Moreover, an asymmetric gate-overlapped LDD was used to suppress the offstate leakage current and reduce the source/drain series resistance significantly as compared to the conventional symmetrical LDD. The on-current drive, offstate leakage current, subthreshold slope, and DIBL for the fabricated 50-nm devices are 325 /spl mu/A//spl mu/m, 8/spl times/10/sup -9/ /spl mu/A//spl mu/m, 87 mV/V, and 95 mV/dec, respectively.     

Implementation of fully self-aligned bottom-gate MOS transistor

This letter reports the implementation of a bottom-gate MOSFET, which possesses the following fully self-aligned structural features: 1) self-aligned source-drain to bottom-gate; 2) self-aligned thick source-drain and thin channel; and 3) self-aligned and mask-free lightly doped drain (LDD). The complete self-alignment is realized by combining a conventional ion implantation and a subsequent chemical-mechanical polishing (CMP) step. The process is applied to poly-Si films crystallized from an a-Si film deposited by LPCVD using a metal-induced unilateral crystallization technique, and is grain-enhanced further in a high temperature annealing step. Deep submicron fully self-aligned bottom-gate pMOS transistors with channel length less than 0.5 /spl mu/m are fabricated. The measured performance parameters include threshold voltage of -0.43 V, subthreshold swing of 113 mV/dec, effective hole mobility of 147 cm/sup 2//V-s, off-current of 0.17 pA//spl mu/m, and on-off current ratio of 7.1/spl times/10/sup 8/.     

Polycrystalline silicon thin-film transistors fabricated by defect reduction methods

Fabrication of n-channel polycrystalline silicon thin-film transistors (poly-Si TFTs) at a low temperature is reported. 13.56 MHz-oxygen plasma at a 100 W, 130 Pa at 250/spl deg/C for 5 min, and heat treatment at 260/spl deg/C with 1.3/spl times/10/sup 6/-Pa-H/sub 2/O vapor for 3 h were applied to reduction of the density of defect states in 25-nm-thick silicon films crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Defect reduction was numerically analyzed. Those treatments resulted in a high carrier mobility of 830 cm/sup 2//Vs and a low threshold voltage of 1.5 V at a laser crystallization energy density of 285 mJ/cm/sup 2/.     

Polycrystalline silicon films and thin-film transistors using solution-based metal-induced crystallization

Polycrystalline silicon (poly-Si) films consisting of dish-like and wadding-like domains were obtained with solution-based metal-induced crystallization (SMIC) of amorphous silicon. The Hall mobility of poly-Si was much higher in dish-like domains than in wadding-like domains. Thin-film transistors (TFTs) have been prepared using those two kinds of poly-Si films as the active layer, followed by the phosphosilicate glass (PSG) nickel gettering. The field effect mobility of dish-like domain poly-Si TFTs and wadding-like poly-Si TFTs were 70/spl sim/80 cm/sup 2//V/spl middot/s and 40/spl sim/50 cm/sup 2//V/spl middot/s, respectively. With a multi-gate structure, the leakage current of poly-Si TFTs was reduced by 1 to 2 orders of magnitude. In addition, the gate-induced drain leakage current (GIDL) and uniformity of the drain current distribution were also improved. P-type TFTs fabricated using SMIC exhibited excellent reliability.     

Fabrication of high-performance InGaAsN ridge waveguide lasers with pulsed anodic oxidation

We have demonstrated high-performance InGaAsN triple-quantum-well ridge waveguide (RWG) lasers fabricated using pulsed anodic oxidation. The lowest threshold current density of 675 A/cm/sup 2/ was obtained from a P-side-down bonded InGaAsN laser, with cavity length of 1600 /spl mu/m and contact ridge width of 10 /spl mu/m. The emission wavelength is 1295.1 nm. The transparency current density from a batch of unbonded InGaAsN RWG lasers was 397 A/cm/sup 2/ (equivalent to 132 A/cm/sup 2/ per well). High characteristic temperature of 138 K was also achieved from the bonded 10/spl times/1600-/spl mu/m/sup 2/ InGaAsN laser.     

Low-resistance ultrashallow extension formed by optimized flash lamp annealing

Flash lamp annealing (FLA) technology is proposed as a new method of activating implanted impurities. By optimizing FLA and implantation conditions, junction depth (Xj) at the concentration of 1 /spl times/ 10/sup 18/ cm/sup -3/ and the sheet resistance of 13 nm and 700 /spl Omega//sq for As and 14 nm and 770 /spl Omega//sq for BF/sub 2/ with junction leakage lower than 1 /spl times/ 10/sup -16/ A//spl mu/m/sup 2/ at 1.5 V were successfully obtained without wafer slip and warpage problems.     

10-kV, 123-m/spl Omega//spl middot/cm/sup 2/ 4H-SiC power DMOSFETs

10-kV, 123-m/spl Omega//spl middot/cm/sup 2/ power DMOSFETs in 4H-SiC are demonstrated. A 42% reduction in R/sub on,sp/, compared to a previously reported value, was achieved by using an 8 /spl times/ 10/sup 14/ cm/sup -3/ doped, 85-/spl mu/m-thick drift epilayer. An effective channel mobility of 22 cm/sup 2//Vs was measured from a test MOSFET. A specific on-resistance of 123 m/spl Omega//spl middot/cm/sup 2/ were measured with a gate bias of 18 V, which corresponds to an E/sub ox/ of 3 MV/cm. A leakage current of 197 /spl mu/A was measured at a drain bias of 10 kV from a 4H-SiC DMOSFET with an active area of 4.24 /spl times/ 10/sup -3/ cm/sup 2/. A switching time of 100 ns was measured in 4.6-kV, 1.3-A switching measurements. This shows that the 4H-SiC power DMOSFETS are ideal for high-voltage, high-speed switching applications.     

A resonant tunneling quantum-dot infrared photodetector

A novel device-resonant tunneling quantum-dot infrared photodetector-has been investigated theoretically and experimentally. In this device, the transport of dark current and photocurrent are separated by the incorporation of a double barrier resonant tunnel heterostructure with each quantum-dot layer of the device. The devices with In/sub 0.4/Ga/sub 0.6/As-GaAs quantum dots are grown by molecular beam epitaxy. We have characterized devices designed for /spl sim/6 /spl mu/m response, and the devices also exhibit a strong photoresponse peak at /spl sim/17 /spl mu/m at 300 K due to transitions from the dot excited states. The dark currents in the tunnel devices are almost two orders of magnitude smaller than those in conventional devices. Measured values of J/sub dark/ are 1.6/spl times/10/sup -8/ A/cm/sup 2/ at 80 K and 1.55 A/cm/sup 2/ at 300 K for 1-V applied bias. Measured values of peak responsivity and specific detectivity D/sup */ are 0.063 A/W and 2.4/spl times/10/sup 10/ cm/spl middot/Hz/sup 1/2//W, respectively, under a bias of 2 V, at 80 K for the 6-/spl mu/m response. For the 17-/spl mu/m response, the measured values of peak responsivity and detectivity at 300 K are 0.032 A/W and 8.6/spl times/10/sup 6/ cm/spl middot/Hz/sup 1/2//W under 1 V bias.     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

Top-gate TFTs using 13.56 MHz PECVD microcrystalline silicon

Top-gate thin-film transistors (TFTs) with microcrystalline silicon (/spl mu/c-Si) channel layers deposited using standard 13.56 MHz plasma-enhanced chemical vapor deposition were fabricated at a maximum processing temperature of 250/spl deg/C. The TFTs employ amorphous silicon nitride (a-SiN) as the gate dielectric layer. The 80-nm-thick /spl mu/c-Si channel layer showed a dark conductivity of the order of 10/sup -7/ S/cm and a crystalline volume fraction of over 80%. The /spl mu/c-Si TFTs showed a field effect mobility of 0.85 cm/sup 2//V/spl middot/s, a threshold voltage of 4.8 V, a subthreshold slope of 1 V/dec, and an ON/OFF current ratio of /spl sim/10/sup 7/. More importantly, the TFTs were very stable under gate bias stress, offering promise for organic light-emitting display (OLED) applications.     

Optical subthreshold current method for extracting the interface states in MOS systems

Optical subthreshold current method (OSCM) is proposed for characterizing the interface states in MOS systems using the current-voltage characteristics under a photonic excitation. An optical source with a subbandgap (E/sub ph/相似文献   

InAlN/GaN HEMTs: a first insight into technological optimization

High-electron mobility transistors (HEMTs) were fabricated from heterostructures consisting of undoped In/sub 0.2/Al/sub 0.8/N barrier and GaN channel layers grown by metal-organic vapor phase epitaxy on (0001) sapphire substrates. The polarization-induced two-dimensional electron gas (2DEG) density and mobility at the In/sub 0.2/Al/sub 0.8/N/GaN heterojunction were 2/spl times/10/sup 13/ cm/sup -2/ and 260 cm/sup 2/V/sup -1/s/sup -1/, respectively. A tradeoff was determined for the annealing temperature of Ti/Al/Ni/Au ohmic contacts in order to achieve a low contact resistance (/spl rho//sub C/=2.4/spl times/10/sup -5/ /spl Omega//spl middot/cm/sup 2/) without degradation of the channels sheet resistance. Schottky barrier heights were 0.63 and 0.84 eV for Ni- and Pt-based contacts, respectively. The obtained dc parameters of 1-/spl mu/m gate-length HEMT were 0.64 A/mm drain current at V/sub GS/=3 V and 122 mS/mm transconductance, respectively. An HEMT analytical model was used to identify the effects of various material and device parameters on the InAlN/GaN HEMT performance. It is concluded that the increase in the channel mobility is urgently needed in order to benefit from the high 2DEG density.