Board level reliability assessment of chip scale packages

A large program had been initiated to study the board level reliability of various types of chip scale package (CSP). The results on six different packages are reported here, which cover flex interposer CSP, rigid interposer CSP, wafer level assembly CSP, and lead frame CSP. The packages were assembled on FR4 PCBs of two different thicknesses. Temperature cycling tests from −40°C to +125°C with 15 min dwell time at the extremes were conducted to failure for all the package types. The failure criteria were established based on the pattern of electrical resistance change. The cycles to failure were analyzed using Weibull distribution function for each type of package. Selected packages were tested in the temperature/humidity chamber under 85°C/85%RH for 1000 h. Some assembled packages were tested in vibration condition as well. In all these tests, the electrical resistance of each package under testing was monitored continuously. Test samples were also cross-sectioned and analyzed under a Scanning Electronic Microscope (SEM). Different failure mechanisms were identified for various packages. It was noted that some packages failed at the solder joints while others failed inside the package, which was packaging design and process related.     

Drop impact reliability of edge-bonded lead-free chip scale packages

This paper presents the drop test reliability results for edge-bonded 0.5 mm pitch lead-free chip scale packages (CSPs) on a standard JEDEC drop reliability test board. The test boards were subjected to drop tests at several impact pulses, including a peak acceleration of 900 Gs with a pulse duration of 0.7 ms, a peak acceleration of 1500 Gs with a pulse duration of 0.5 ms, and a peak acceleration of 2900 Gs with a pulse duration of 0.3 ms. A high-speed dynamic resistance measurement system was used to monitor the failure of the solder joints. Two edge-bond materials used in this study were a UV-cured acrylic and a thermal-cured epoxy material. Tests were conducted on CSPs with edge-bond materials and CSPs without edge bonding. Statistics of the number of drops-to-failure for the 15 component locations on each test board are reported. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. Failure analysis was performed using dye-penetrant and scanning electron microscopy (SEM) methods. The most common failure mode observed is pad lift causing trace breakage. Solder crack and pad lift failure locations are characterized with the dye-penetrant method and optical microscopy.     

100 μm Pitch flip chip on foil assemblies with adhesive interconnections

In this work the reliability of flip-chip-on-flexible substrate packages with electrically conductive adhesive as first level interconnections is studied. The pitch of the interconnections ranges from 300 to 100 μm with prospects to smaller pitches. The Physics-of-Failure approach is used to determine the nature of such an interconnection and hence the factors that will influence the performance of these packages. The results indicate that moisture is a more important stress factor than temperature. In particular cyclic exposure to high and low moisture levels may lead to degradation of the electrical interconnection. As failure mechanism, reduction of the compressive force that holds the interconnection together is proposed. Further, the proper combination of materials––based on their in- and out-diffusion rates for water––determines the resistance of the packages to reflow-soldering.     

Study of short-circuiting between adjacent joints under electric field effects in fine pitch anisotropic conductive adhesive interconnects

Anisotropic conductive adhesive film (ACF) has been extensively used in the liquid crystal display (LCD) industry for decades on chip-on-glass (COG) applications. It offers the advantages in terms of fine-pitch capability and more environment compatibility. One of the very important performance requirements of using ACF in fine pitch interconnection is not to create leakage of electric current between adjacent joints as it may lead to abnormal display segments/pixels of the LCD. In this work, the possibility of short-circuiting between adjacent joints in fine pitch ACF interconnections under the effects of electric field was investigated. Insulation resistance measurements of the selected adjacent joints against electric field strength 1 V/μm for a 24 h testing duration were discussed and analyzed. The results showed a strong dependence of curing degree of the ACFs on the chance of short-circuiting between adjacent joints under field effects.     

Particle on Bump (POB) technique for ultra-fine pitch chip on glass (COG) applications by conductive particles and adhesives

Chip on glass (COG) technology is widely used in liquid crystal display (LCD) modules for connecting driver ICs to the displays especially for middle and small size panels. The most common COG technology currently used in display applications is based on anisotropic conductive films (ACF). As the increasing demand in higher resolution and cost reduction, the bump pitch of the driver ICs becomes finer and finer. With the reduction of bump pitch, the current ACF based COG technology is confronted with two issues: one is the increase of the chances of open circuit; the other is the increase of the chances of forming shorts. A new approach for ultra-fine pitch chip on glass (COG) bonding, named ”Particle on Bump (POB)”, is proposed in this paper. In this technique, conductive particles are planted on the top surface of bumps of a driver IC through Au–Sn intermetallic connection. The driver IC is then assembled on the glass substrate of a LCD panel with an insulated adhesive by thermal press. The new method ensures that electrical connections are established only between bumps and corresponding pads. The Au–Sn reflow process for particle planting and corresponding COG bonding process were investigated in detail. The results showed that reliable connections were formed between particles and bumps through an Au–Sn intermetallic layer and final COG interconnections thus formed performed well in reliability tests. It is concluded that the POB technique overcomes the shortcomings of current ACF technique and has good potential to provide a viable ultra-fine pitch flip chip on glass solution for display applications.     

A new COG technique using low temperature solder bumps for LCD driver IC packaging applications

A new chip on glass (COG) technique using flip chip solder joining technology has been developed for excellent resolution and high quality liquid crystal display (LCD) panels. The flip chip solder joining technology has several advantages over the anisotropic conductive film (ACF) bonding technology: finer pitch capability, better electrical performance, and easier reworkability. Conventional solders such as eutectic Pb-Sn and Pb-5Sn require high temperature processing which can lead to degradation of the liquid crystal or the color filter in LCD modules. Thus it is desirable to develop a low temperature process below 160/spl deg/C using solders with low melting temperatures for this application. In our case, we used eutectic 58 wt%Bi-42 wt%Sn solder for this purpose. Using the eutectic Bi-Sn solder bumps of 50-80/spl mu/m pitch sizes, an ultrafine interconnection between the IC and glass substrate was successfully made at or below 160/spl deg/C. The average contact resistance of the Bi-Sn solder joints was 19m/spl Omega/ per bump, which is much lower than the contact resistance of conventional ACF bonding technologies. The contact resistance of the underfilled Bi-Sn solder joints did not change during a hot humidity test. We demonstrate that the COG technique using low temperature solder joints can be applied to advanced LCDs that lead to require excellent quality, high resolution, and low power consumption.     

A thermomechanical study of the electrical resistance of Cu lead interconnections

The choice of liquid crystal display (LCD) driver packaging technology significantly influences the display performance of flat panel displays. Tape automated bonding (TAB) is generally the method of choice for connecting the LCD and the LCD driver circuit in flat panel displays. To achieve a finer pitch, an easier assembly, and a greater connection reliability, the design of the inner Cu lead must not only consider thermomechanical failure aspects, but must also maintain an acceptable joint resistance. This paper proposes an analytical model to predict the unit change in resistance of the copper foils used for TAB inner lead interconnections under various thermal environments and stressstrain states. The analytical model is based on a constitutive equation of the copper foil and the working principle of strain gages. Copper foil specimens are tensile tested at temperatures of 25°C, 50°C, 75°C, and 100°C at strain rates of 0.2/min. and 0.5/min., respectively, to confirm the validity of the developed analytical model. The numerical results and the experimental data are found to be in good agreement. Hence, the analytical method provides the means of predicting the thermal effect on the electrical and mechanical properties of the copper foils. Finally, by implementing finite-element method (FEM) solutions in the developed analytical model, this study constructs electrical resistance design charts to predict the variation in the electrical resistance of the copper foils under different thermal-mechanical conditions.     

Issues in Assembly Process of Next-Generation Fine-Pitch Chip-On-Flex Packages for LCD Applications

Some of the current assembly issues of fine-pitch chip-on-flex (COF) packages for LCD applications are reviewed. Traditional underfill material, anisotropic conductive adhesive (ACA), and nonconductive adhesive (NCA) are considered in conjunction with two applicable bonding methods including thermal and laser bonding. Advantages and disadvantages of each material/process combination are identified. Their applicability is further investigated to identify a process most suitable to the next-generation fine-pitch packages (less than 35 mum). Numerical results and subsequent testing results indicate that the NCA/laser bonding process is advantageous for preventing both lead crack and excessive misalignment compared to the conventional bonding process     

Fatigue life evaluation of wire bonds in LED packages using numerical analysis

Reliability of LED packages is evaluated using several tests. When a thermal shock test, which is one of the reliability tests, is conducted, the most common failure mode is wire neck breakage. In order to evaluate the wire bonding reliability of LED packages, performing the thermal shock test is time-consuming. In this paper the wire bonding reliability for LED packages is evaluated by using numerical analysis. A wire bonding lifetime model for the thermal shock test was developed, which is based on Coffin-Manson fatigue law. The model was calibrated from fatigue data of thermal shock tests and volume averaging accumulated plastic strains. The accumulated plastic strains were calculated by using finite element analysis corresponding to the test conditions. The test conditions were changed by silicones, package sizes, wire bonding diameters, heights, and lengths. The calibrated model was used to estimate the number cycle to failure so that the wire bonding reliability for the thermal shock test was evaluated by performing the numerical analysis. Furthermore, we used a response surface methodology to study the relationship between the wire loop and the accumulated plastic strain to determine the optimal wire loop. The plastic strain was a function of diameter, height and length. At the optimal point, the number of cycle to failure for the thermal shock test was suggested using the wire bonding lifetime model.     

New encapsulation development for fine pitch IC devices

The continuous reduction of chip size driven by the market demand has a significant impact on circuit design and assembly process of IC packages. Shrinking chip size and increasing I/O counts require finer bond pad pitch and bond pad size for circuitry layout. As a result, serious wire deflection during transfer molding process could make adjacent wires short, and this issue becomes more critical as a smaller wire diameter has to be applied for the finer pitch wire bonded IC devices.This paper presents a new encapsulation process development for 50 μm fine pitch plastic ball grid array package. Since reduced wire diameter decreases the bending strength of bonded wires significantly, wire deflection during molding process becomes quite serious and critical. Experiments on conventional transfer molding were conducted to evaluate wire span threshold with 23.0 μm diameter gold wire. The results show that the wire span threshold is about 4.1 mm, which is much shorter than the wire span threshold of over 5.0 mm for wire with 25.4 μm diameter. Finite element analysis shows there is a significant difference in the wire deflection between 23.0 μm gold wire and 25.4 μm gold wire diameter under the same action of mold flow. A novel encapsulation method is introduced using non-sweep solution. The wire span could be extended to over 5.0 mm with wire sweep less than 1%. Reliability tests conducted showed that all the units passed 1000 temperature cycles (−55 to 125 °C) with JEDEC moisture sensitivity level 2a (60 °C/60% relative humidity for 120 h) and 3 times reflow (peak temperature at 220–225 °C). It is believed that this solution could efficiently overcome the risk of wire short issues and improve the yield of ultra fine pitch wire bonds in high-volume production.     

Lead-free plastic area array BGAs and polymer stud grid arrays package reliability

Many packaging and original equipment manufacturers (OEMs) have initiated a program of introducing lead-free electronics. Although lead usage in the packaging industry is relatively small, major efforts are ensuring to eliminate lead usage. In this context, we manufactured and qualified two “green” package solutions: lead-free low-profile fine pitch ball grid array (LFBGA) and polymer stud grid arrays (PSGA^TM) area array packages.The primary source of lead in BGA is in the solder balls. Lead-free solder alloys are readily available, although there is no universal drop-in replacement identified so far for plastic BGAs. One of the most promising alloys for this purpose appears to be the eutectic Sn95.5Ag4Cu0.5, although it involves higher processing temperature. Based on a design of experiment (DOE), the best reflow profile has been determined and used. A lead-free 8×8 mm² LFBGA has been manufactured without other process or equipment changes, and has been qualified for JEDEC moisture level 3, with 245°C reflow simulations, and standard 1st level package reliability tests.An alternative to lead-free plastic BGA is the PSGA^TM. The PSGA^TM package consists of a polymer injection-molded 3D body with a location for chip mounting and polymer studs. The metallized studs, which are by nature lead-free, replace the solder balls within the BGA package. Moisture conditioning and reliability analysis was performed on 8×8 mm² PSGA^TM. The package passed JEDEC moisture conditioning level 3 as well as standard reliability tests.     

Risk assessment of the crack propagation and delamination of the Cu-to-Cu direct bonded (CuDB) interface

Through Silicon Via (TSV) technology with micro joint has been identified as the 3D package technology to overcome the limitations of I/O density and enhances the system performance compared to that of the conventional flip chip packages. One of the challenges of the reliable 3D TSV packages is stacking and joining of thin wafers or dies. The conventional micro joining methods, such as use of solder bumps, cause many reliability problems, such as intermetallic compound (IMC) formation, electromigration, delamination, creep, and fatigue problems. As an alternative, copper-to-copper direct bonding (CuDB) has been proposed. CuDB enables reduction in fabrication process steps, can obtain higher interconnect density and enhanced thermal conductivity. However, the CuDB interface has potential reliability risk since the bonding is typically performed by compression at high temperature. Several prior studies have reported formation of small voids between the bonding interfaces of the CuDB that can lead to crack initiation, propagation and thereby delamination of the entire interface. The defect can result in failure of the entire package during its fabrication process or operation.This study is risk assessment of possibility of crack propagation at the CuDB interface using fracture mechanics approach. Finite element (FE) analysis and design of experiments (DOE) are used. A crack is assigned at the interface of the CuDB to mimic a small void. Initial crack location and dimensional variables (Initial crack length, Cu pad diameter and pitch, and TSV diameter and pitch) are varied to quantify the risk. The strain energy release rate (SERR) around the crack tip is calculated and compared with the critical SERR, obtained by experiments, to judge the possibility of crack propagation. Sensitivity analysis of design parameters is conducted. As a result, this study provides design recommendations that can minimize interfacial failure of the CuDB. In addition, this study explores various numerical modeling methodologies that can be implemented for efficient failure prediction of the interfaces.     

Experiment and numerical analysis for edge and corner bonded PoP bottom package assemblies under four-point bending

This paper presents the four-point bend test results for edge and corner bonded 0.5 mm pitch lead-free package stackable very thin fine pitch ball grid arrays (PSvfBGAs) as package-on-package (PoP) bottom packages on a standard IPC/JEDEC bend test board. The tests were carried out based on the above standard with a 30 mm loading span, 90 mm support span and 7.5 mm/s crosshead speed. The daisy chain resistance, strain, crosshead displacement and load of each PSvfBGA were measured and a 20% increase in the resistance was used as the failure criterion. Materials used in this study were a UV-cured acrylic edge bond adhesive, a thermal-cured epoxy edge bond adhesive and a thermal-cured epoxy corner bond adhesive. The test results show that all of them can improve the bend performance significantly; especially the edge bond high module epoxy increased the crosshead displacement, strain and bending force when mechanical damage occurred by 33.46%, 26.74% and 3.05% respectively. Failure analysis indicated that the predominant failure site was PCB pad lift/cratering regardless of with or without adhesives. The 3D quarter finite element model was also built to further study the improvement mechanism of bend performance by these adhesives.     

Studies on various chip-on-film (COF) packages using ultra fine pitch two-metal layer flexible printed circuits (two-metal layer FPCs)

Various fine pitch chip-on-film (COF) packages assembled by (1) anisotropic conductive film (ACF), (2) nonconductive film (NCF), and (3) AuSn metallurgical bonding methods using fine pitch flexible printed circuits (FPCs) with two-metal layers were investigated in terms of electrical characteristics, flip chip joint properties, peel adhesion strength, heat dissipation capability, and reliability. Two-metal layer FPCs and display driver IC (DDI) chips with 35 μm, 25 μm, and 20 μm pitch were prepared. All the COF packages using two-metal layer FPCs assembled by three bonding methods showed stable flip chip joint shapes, stable bump contact resistances below 5 mΩ, good adhesion strength of more than 600 gf/cm, and enhanced heat dissipation capability compared to a conventional COF package using one-metal layer FPCs. A high temperature/humidity test (85 °C/85% RH, 1000 h) and thermal cycling test (T/C test, ?40 °C to + 125 °C, 1000 cycles) were conducted to verify the reliability of the various COF packages using two-metal layer FPCs. All the COF packages showed excellent high temperature/humidity and T/C reliability, however, electrically shorted joints were observed during reliability tests only at the ACF joints with 20 μm pitch. Therefore, for less than 20 μm pitch COF packages, NCF adhesive bonding and AuSn metallurgical bonding methods are recommended, while all the ACF and NCF adhesives bonding and AuSn metallurgical bonding methods can be applied for over 25 μm pitch COF applications. Furthermore, we were also able to demonstrate double-side COF using two-metal layer FPCs.     

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.     

Reliability prediction for TFBGA assemblies

One of the key hot topics in dense large scale integration packaging technologies is to reduce the thermomechanical stress caused by a mismatch of coefficients of thermal expansion among material employed. Nearly all manufacturers of portable electronics products perform several kinds of physical tests in the development cycle to evaluate reliability of the products. In this paper, results obtained by accelerated thermal and power cycling tests by using thin fine pitch gall grid array (TFBGA) packages are reported. Power-cycling stands for a lifetime acceleration method which is close to the real environmental conditions of many electronic products. For this purpose, a set of TFBGA thermal test packages were designed and manufactured for reliability assessment of solder joint interconnections. The assemblies consisted of an array of polysilicon resistors surrounding a sensing diode for accurate temperature measurements. The package uses a qualified bill of materials including a 36-mm/sup 2/ dummy die. Each assembly was designed to perfectly reproduce the thermomechanical behavior of the mass production packages by several semiconductor manufacturers. This package is used in telecom wireless application where it offers high density input/output solution for advanced application-specific integrated circuit (IC) devices a system on chip ICs. Both experiments and simulations were carried out to locate the position of the most critical parts. Complexity of structural package characteristics was examined by using finite-element method modeling methodology. A strain energy based model was employed to locate the most vulnerable parts in the package and predict failure rates.     

CCGA packages for space applications

Commercial-off-the-shelf (COTS) area array packaging technologies in high reliability versions are now being considered for applications, including use in a number of NASA electronic systems being utilized for both the Space Shuttle and Mars Rover missions. Indeed, recently a ceramic package version specifically tailored for high reliability applications was used to provide the processing power required for the Spirit and Opportunity Mars Rovers built by NASA-JPL. Both Rovers successfully completed their 3-months mission requirements and continued exploring the Martian surface for many more moths, providing amazing new information on previous environmental conditions of Mars and strong evidence that water exists on Mars.Understanding process, reliability, and quality assurance (QA) indicators for reliability are important for low risk insertion of these newly available packages in high reliability applications. In a previous investigation, thermal cycle test results for a non-functional daisy-chained peripheral ceramic column grid array (CCGA) and its plastic ball grid array (PBGA) version, both having 560 I/Os, were gathered and are presented here. Test results included environmental data for three different thermal cycle regimes (−55/125 °C, −55/100 °C, and −50/75 °C). Detailed information on these—especially failure type for assemblies with high and low solder volumes—are presented. The thermal cycle test procedure followed those recommended by IPC-9701 for tin–lead solder joint assemblies. Its revision A covers guideline thermal cycle requirements for Pb-free solder joints. Key points on this specification are also discussed.In a recent investigation a fully populated CCGA with 717 I/Os was considered for assembly reliability evaluation. The functional package is a field-programmable gate array that has much higher processing power than its previous version. This new package is smaller in dimension, has no interposer, and has a thinner column wrapped with copper for reliability improvement. This paper will also present thermal cycle test results for assemblies of this and its plastic package version with 728 I/Os, both of which were exposed to four different cycle regimes. Two of these cycle profiles are specified by IPC-9701A for tin–lead, namely, −55 to 100 °C and −55 to 125 °C. One is a cycle profile specified by Mil-Std-883, namely, −65/150 °C, generally used for ceramic hybrid packages screening and qualification. The last cycle is in the range of −120 to 85 °C, a representative of electronic systems directly exposed to the Martian environment without use in a thermal control enclosure. Per IPC-9701A, test vehicles were built using daisy chain packages and were continuously monitored and/or manually checked for opens at intervals. The effects of many process and assembly variables—including corner staking commonly used for improving resistance to mechanical loading such as drop and vibration loads—were also considered as part of the test matrix. Optical photomicrographs were taken at various thermal cycle intervals to document damage progress and behavior. Representative samples of these are presented along with cross-sectional photomicrographs at higher magnification taken by scanning electron microscopy (SEM) to determine crack propagation and failure analyses for packages.     

Board-level reliability of Pb-free solder joints of TSOP and various CSPs

To evaluate various Pb-free solder systems for leaded package, thin small outline packages (TSOPs) and chip scale packages (CSPs) including leadframe CSP (LFCSP), fine pitch BGA (FBGA), and wafer level CSP (WLCSP) were characterized in terms of board level and mechanical solder joint reliability. For board level solder joint reliability test of TSOPs, daisy chain samples having pure-Sn were prepared and placed on daisy chain printed circuit board (PCB) with Pb-free solder pastes. For CSPs, the same composition of Pb-free solder balls and solder pastes were used for assembly of daisy chain PCB. The samples were subjected to temperature cycle (T/C) tests (-65/spl deg/C/spl sim/150/spl deg/C, -55/spl deg/C/spl sim/125/spl deg/C, 2 cycles/h). Solder joint lifetime was electrically monitored by resistance measurement and the metallurgical characteristics of solder joint were analyzed by microstructural observation on a cross-section sample. In addition, mechanical tests including shock test, variable frequency vibration test, and four point twisting test were carried out with daisy chain packages too. In order to compare the effect of Pb-free solders with those of Sn-Pb solder, Sn-Pb solder balls and solder paste were included. According to this paper, most Pb-free solder systems were compatible with the conventional Sn-Pb solder with respect to board level and mechanical solder joint reliability. For application of Pb-free solder to WLCSP, Cu diffusion barrier layer is required to block the excessive Cu diffusion, which induced Cu trace failure.     

Solder joint fatigue life of fine pitch BGAs – impact of design and material choices

The impact of design and material choices on solder joint fatigue life for fine pitch BGA packages is characterized. Package variables included die size, package size, ball count, pitch, mold compound, and substrate material. Test board variables included thickness, pad configuration, and pad size. Three thermal cycle conditions were used.Fatigue life increased by up to 6× as die size was reduced. For a given die size, fatigue life was up to 2× longer for larger packages with more solder balls. Mold compounds with higher filler content reduced fatigue life by up to 2× due to a higher stiffness and lower thermal expansion coefficient. Upilex S tape with punched holes gave 1.15× life improvement over Kapton E tape with etched holes. Once optimized, tape-based packages have equal board level reliability to laminate-based packages.Solder joint fatigue life was 1.2× longer for 0.9 mm thick test boards compared to 1.6 mm thick boards due to a lower assembly stiffness. The optimum PCB pad design depends on failure location. For CSP applications, NSMD test board pads give up to 3.1× life improvement over SMD pads. For a completely fan-out design, there was a 1.6× acceleration factor between −40125°C, 15 min ramps, 15 min dwells and 0100°C, 10 min ramps, 5 min dwells.     

微电子封装中FeCl_3蚀刻液沉淀失效及再恢复

在微电子封装中,多处要使用FeCl3溶液进行蚀刻,如PCB布线,细间距引线框架等。在实际湿法蚀刻的研究中,发现使用高玻美度的FeCl3溶液蚀刻效果好。而高玻美度溶液的低温结晶现象比低玻美度(40癇e)要明显得多,对科学研究和生产带来较大的不利。本文分析研究了FeCl3蚀刻液失效产物和产生机制,提出了失效的温度因素、杂质离子因素、时间因素的影响过程和再恢复的方法。