一种1.8伏带有foldback过流过热保护的低压线性稳压器设计

This paper introduces the design of a l.8 V low dropout voltage regulator （LDO） and a foldback current limit circuit which limits the output current to 3 mA when load over-current occurs. The LDO was implemented in a 0.18 μm CMOS technology. The measured result reveals that the LDO s power supply rejection （PSR） is about -58dB and -54dB at 20Hz and 1kHz respectively,the response time is 4μs and the quiescent currentis 20μA. The designed LDO regulator can work with a supply voltage down to 2.0 V with a drop-out voltage of 200 mV at a maximum load current of 240 mA.     

Load adaptive start-up scheme for synchronous boost DC-DC converter

This paper presents a load adaptive soft-start scheme through which the inductor current of the synchronous boost DC-DC converter can trace the load current at the start-up stage. This scheme effectively eliminates the inrush-current and over-shoot voltage and improves the load capability of the converter. According to the output voltage, the start-up process is divided into three phases and at each phase the inductor current is limited to match the load. In the pre-charge phase, a step-increasing constant current gives a smooth rise of the output voltage which avoids inrush current and ensures the converter successfully starts up at different load situations. An additional ring oscillator operation phase enables the converter to start up as low as 1.4 V. When the converter enters into the system loop soft-start phase, an output voltage and inductor current detection methods make the transition of the phases smooth and the inductor current and output voltage rise steadily. Effective protection circuits such as short-circuit protection, current limit circuit and over-temperature protection circuit are designed to guarantee the safety and reliability of the chip during the start-up process. The proposed start-up circuit is implemented in a synchronous boost DC-DC converter based on TSMC 0.35μm CMOS process with an input voltage range 1.4-4.2 V, and a steady output voltage 5 V, and the switching frequency is 1 MHz. Simulation results show that inrush current and overshoot voltage are suppressed with a load range from 0-2.1 A, and inductor current is as low as 259 mA when the output shorts to the ground.     

A high-efficiency,low-noise power solution for a dual-channel GNSS RF receiver

A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented.The power solution involves a DC-DC buck converter and a followed low-dropout regulator(LDO).The pulsewidth -modulation(PWM) control method is adopted for better noise performance.An improved low-power highfrequency PWM control circuit is proposed,which halves the average quiescent current of the buck converter to 80μA by periodically shutting down the OTA.The size of the output stage has also been optimized to achieve high efficiency under a light load condition.In addition,a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current.Fabricated with commercial 180-nm CMOS technology,the DC-DC converter achieves a peak efficiency of 93.1%under a 2 MHz working frequency.The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.     

A dual mode charge pump with adaptive output used in a class G audio power amplifier

A dual mode charge pump to produce an adaptive power supply for a class G audio power amplifier is presented.According to the amplitude of the input signals,the charge pump has two level output voltage rails available to save power.It operates both in current mode at high output load and in pulse frequency modulation (PFM) at light load to reduce the power dissipation.Also,dynamic adjustment of the power stage transistor size based on load current at the PFM mode is introduced to reduce the output voltage ripple and prevent the switching frequency from audio range.The prototype is implemented in 0.18μm 3.3 V CMOS technology.Experimental results show that the maximum power efficiency of the charge pump is 79.5%@ 0.5x mode and 83.6%@ lx mode.The output voltage ripple is less than 15 mV while providing 120 mA of the load current at PFM control and less than 18 mV while providing 300 mA of the load current at current mode control.An analytical model for ripple voltage and efficiency calculation of the proposed PFM control demonstrates reasonable agreement with measured results.     

大功率低阈值980nm单模AlGaInAs/AlGaAs量子阱激光器

To achieve low threshold current as well as high single mode output power,a graded index separate confinement heterostructure(GRIN-SCH)AlGaInAs/AlGaAs quantum well laser with an optimized ridge waveguide was fabricated.The threshold current was reduced to 8 mA.An output power of 76 mW was achieved at100 mA current at room temperature,with a slope efficiency of 0.83 W/A and a horizon divergent angle of 6.3.The maximum single mode output power of the device reached as high as 450 mW.     

适用于具有自适应续流电流的单电感双输出降压变换器的准滑模控制器设计

An analog implementation of a novel fixed-frequency quasi-sliding-mode controller for single-inductor dual-output(SIDO) buck converter in pseudo-continuous conduction mode(PCCM) with a self-adaptive freewheeling current level(SFCL) is presented.Both small and large signal variations around the operation point are considered to achieve better transient response so as to reduce the cross-regulation of this SIDO buck converter.Moreover,an internal integral loop is added to suppress the steady-state regulation error introduced by conventional PWM-based sliding mode controllers.Instead of keeping it as a constant value,the free-wheeling current level varies according to the load condition to maintain high power efficiency and less cross-regulation at the same time.To verify the feasibility of the proposed controller,an SIDO buck converter with two regulated output voltages,1.8 V and 3.3 V,is designed and fabricated in HEJIAN 0.35 m CMOS process.Simulation and experiment results show that the transient time of this SIDO buck converter drops to 10 s while the cross-regulation is reduced to 0.057 mV/mA,when its first load changes from 50 to 100 mA.     

High power single mode 980 nm AIGalnAs/AIGaAs quantum well lasers with a very low threshold current

To achieve low threshold current as well as high single mode output power, a graded index separate confinement heterostructure （GRIN-SCH） A1GaInAs/A1GaAs quantum well laser with an optimized ridge wave- guide was fabricated. The threshold current was reduced to 8 mA. An output power of 76 mW was achieved at 100 mA current at room temperature, with a slope efficiency of 0.83 W/A and a horizon divergent angle of 6.3°. The maximum single mode output power of the device reached as high as 450 mW.     

高效率低电磁干扰的升压型DC–DC转换器

A synchronous boost DC-DC converter with an adaptive dead time control （DTC） circuit and antiringing circuit is presented. The DTC circuit is used to provide adjustable dead time and zero inductor current detection for power transistors and therefore, a high efficiency is achieved by minimizing power losses, such as the shoot-through current loss, the body diode conduction loss, the charge-sharing loss and the reverse inductor current loss. Simultaneously, a novel anti-ringing circuit controlled by the switching sequence of power transistors is developed to suppress the ringing when the converter enters the discontinuous conduction mode （DCM） for low electromagnetic interference （EMI） and additional power savings. The proposed converter has been fabricated in a 0.6 #m CDMOS technology. Simulation and experimental results show that the power efficiency of the boost converter is above 81% under different load currents from 10 to 250 mA and a peak efficiency of 90% is achieved at about 100 mA. Moreover, the ringing is easily suppressed by the anti-ringing circuit and therefore the EMI noise is attenuated.     

电流模线性控制电荷泵的研究与设计

To meet the demands for a number of LEDs,a novel charge pump circuit with current mode control is proposed.Regulation is achieved by operating the current mirrors and the output current of the operational transconductance amplifier.In the steady state,the input current from power voltage retains constant,so reducing the noise induced on the input voltage source and improving the output voltage ripple.The charge pump small-signal model is used to describe the device’s dynamic behavior and stability.Analytical predictions were verified by Hspice simulation and testing.Load driving is up to 800 mA with a power voltage of 3.6 V,and the output voltage ripple is less than 45 mV.The output response time is less than 8μs,and the load current jumps from 400 to 800 mA.     

一个65nm GP CMOS工艺0.06mm2 1.0V 2.5mW 10bit 250MS/s 电流舵数模转换器

A10 bit 250 MS/s current-steering digital-to-analog converter is presented. Only standard Vv core de- vices are available for the sake of simplicity and low cost. In order to meet the INL performance, a Monte Carlo model is built to analyze the impact of mismatch on integral nonlinearity （INL） yield with both end-point line and best-fit line. A formula is derived for the relationship oflNL and output impedance. The relation of dynamic range and output impedance is also discussed. The double eentroid layout is adopted for the current source array in order to mitigate the effect of electrical, process, and temperature gradient. An adapted current mirror is used to over- come the gate leakage of the current source array, which cannot be ignored in the 65 nm GP CMOS process. The digital-to-analog converter occupies 0.06 mm2, and consumes 2.5 mW from a single 1.0 V supply at 250 MS/s.     

CMOS电流控制全平衡式电流传输器

This paper presents a current controlled fully balanced second-generation current conveyor circuit（CF-BCCII）.The proposed circuit has the traits of fully balanced architecture, and its X-Y terminals are current control-lable.Based on the CFBCCII, two biquadratic universal filters are also proposed as its applications.The CFBCCII circuits and the two filters were fabricated with chartered 0.35-μm CMOS technology;with ±1.65 V power supply voltage, the total power consumption of the CFBCCII circuit is 3.6 mW.Comparisons between measured and HSpice simulation results are also given.     

采用PMOS底部电流源的低功耗电流自调整压控振荡器

This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise. A current self-adjusted technique without additional external control signals is taken to ensure the VCO starts up in the whole band while keeping the power consumption relatively low. Meanwhile, the phase noise of the VCO at the low frequency （high Cvar） can be reduced by the technique. The circuit is implemented in 0.18 μm CMOS technology. The proposed VCO exhibits low power consumption of 〈1.6 mW at a 1.5 V supply voltage and a tuning range from 11.79 to 12.53 GHz. The measured phase noise at 1 MHz offset from the frequency 11.79 GHz is-104.7 dBc/Hz, and the corresponding FOM is -184.2 dBc/Hz.     

Current mode ADC design in a 0.5-μm CMOS process

This paper presents a pipelined current mode analog to digital converter（ADC） designed in a 0.5-μm CMOS process.Adopting the global and local bias scheme,the number of interconnect signal lines is reduced numerously,and the ADC exhibits the advantages of scalability and portability.Without using linear capacitance,this ADC can be implemented in a standard digital CMOS process;thus,it is suitable for applications in the system on one chip（SoC） design as an analogue IP.Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256 μA.Adopting the histogram testing method,the ADC was tested in a 3.3 V supply voltage/±64 μA quantization range and a 5 V supply voltage/±256 μA quantization range,respectively.The results reveal that this ADC achieves a spurious free dynamic range of 61.46 dB,DNL/INL are-0.005 to ＋0.027 LSB/-0.1 to ＋0.2 LSB,respectively,under a 5 V supply voltage with a digital error correction technique.     

A 0.18μm CMOS fluorescent detector system for bio-sensing application

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier （CTIA）, and a 12 bit pipelined analog-to- digital converter （ADC）, and is implemented in a 0.18μm standard CMOS process. Some special techniques, such as a ＂contact imaging＂ detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm^2 and consumes 37 mW.     

具有简单线性补偿和准谐振导通的原边控制的单级反激式LED驱动器

A single-stage flyback driving integrated circuit （IC） for light-emitting diodes （LEDs） is proposed. With an average primary-side current estimation and negative feedback networks, the driver operates in the boundary conduction mode （BCM）, while the output current can be derived and regulated precisely. By means of a simple external resistor divider, a compensation voltage is produced on the ISEN pin during the turn-on period of the primary MOSFET to improve the line regulation performance. On the other hand, since the delay time between the time that the secondary diode current reaches zero and the turn-on time of the MOSFET can be automatically adjusted, the MOSFET can always turn on at the valley voltage even if the inductance of the primary winding varies with the output power, resulting in quasi-resonant switching for different primary inductances. The driving IC is fabricated in a Dongbu HiTek＇s 0.35μm bipolar-CMOS-DMOS process. An 18 W LED driver is finally built and tested. Results show that the driver has an average efficiency larger than 86%, a power factor larger than 0.97, and works under the universal input voltage （85-265 V） with the LED current variation within ±0.5%.     

应用于65nm CMOS技术节点漏电流分析的精确快速的查表模型

Novel physical models for leakage current analysis in 65 nm technology are proposed. Taking into consideration the process variations and emerging effects in nano-scaled technology, the presented models are capable of accurately estimating the subthreshold leakage current and junction tunneling leakage current in 65 nm technology. Based on the physical models, new table look-up models are developed and first applied to leakage current analysis in pursuit of higher simulation speed. Simulation results show that the novel physical models are in excellent agreement with the data measured from the foundry in the 65 nm process, and the proposed table look-up models can provide great computational efficiency by using suitable interpolation techniques. Compared with the traditional physical-based models, the table look-up models can achieve 2.5X speedup on average on a variety of industry circuits.     

Annealing before gate metal deposition related noise performance in AIGaN/GaN HEMTs

For a further improvement of the noise performance in A1GaN/GaN HEMTs, reducing the relatively high gate leakage current is a key issue. In this paper, an experiment was carried out to demonstrate that one method during the device fabrication process can lower the noise. Two samples were treated differently after gate recess etching： one sample was annealed before metal deposition and the other sample was left as it is. From a comparison of their Ig-Vg characteristics, a conclusion could be drawn that the annealing can effectively reduce the gate leakage current. The etching plasma-induced damage removal or reduction after annealing is considered to be the main factor responsible for it. Evidence is given to prove that annealing can increase the Schottky barrier height. A noise model was used to verify that the annealing of the gate recess before the metal deposition is really effective to improve the noise performance of AIGaN/GaN HEMTs.     

Method of simulation of low dose rate for total dose effect in 0.18 μm CMOS technology

Three methods for simulating low dose rate irradiation are presented and experimentally verified by using 0.18 μm CMOS transistors.The results show that it is the best way to use a series of high dose rate irradiations, with 100 °C annealing steps in-between irradiation steps, to simulate a continuous low dose rate irradiation.This approach can reduce the low dose rate testing time by as much as a factor of 45 with respect to the actual 0.5 rad（Si）/s dose rate irradiation.The procedure also provides detailed information on the behavior of the test devices in a low dose rate environment.     

Software Radio——Software Radio： A Review of Design Considerations and Digital Hardware Choices

This paper reviews the requirements for Software Defined Radio （SDR） systems for high-speed wireless applications and compares how well the different technology choices available- from ASICs, FPGAs to digital signal processors （DSPs） and general purpose processors （GPPs） - meet them.