An IEEE 1149.1 Compliant Test Control Architecture

This paper deals with a design methodology and associated architecture to support the control of on-chip DFT and BIST hardware. The work is general in that it supports numerous test methods, such as partial and full scan, multiple and reconfigurable scan chains, and both test per clock BIST and scan BIST. The results presented here are compatible with the IEEE 1149.1 boundary scan architecture. The work is based on a hierarchical control methodology that includes systems, PCBs and MCMs. Various options for assigning control functions to be on-chip or off-chip are described. A new, partially distributed test control architecture is introduced that includes an internal test bus and distributed local controllers. There are three main modes of control of test resources, namely local static control, dynamic control and global static control. We show how the control mechanism can be implemented together with the IEEE 1149.1 test protocol. The synthesis of the on-chip test control hardware has been automated in a system called CONSYST.     

An introduction to the boundary scan standard: ANSI/IEEE Std 1149.1

ANSI/IEEE Std 1149.1 defines a standard implementation of boundary scan that, it is hoped, will be built into many catalog and application-specific integrated circuits. The standard was developed as a solution to two continuing trends that are having a significant, adverse, impact on the task of testing loaded printed wiring boards: increasing chip complexity and greater miniaturization. The former increases the difficulty of test generation, while the latter impedes access for the bed-of-nails and hand-held probes on which many established test techniques depend.This tutorial provides a guide to the principal features defined by the standard and to their operation. It is intended as a prelude to the standard itself, not as a substitute for it. In particular, it is recommended that readers who intend to implement integrated circuits, design tools, or test systems that support the standard read the standard document before doing so.     

一种遵循IEEE 1149.1标准的可测试性设计结构

IEEE ll49．1(也称JTAG)是支持芯片边界扫描的国际标准，提供了统一的测试访问端口。如今，它已成为芯片必不可少的一种“开销”。本文通过定制JTAG逻辑，以求用最少的开销，最简单灵活的方式来管理各种DFT逻辑。     

BIST for network on chip communication infrastructure based on combination of extended IEEE 1149.1 and IEEE 1500 standards

In this paper we propose a BIST based method to test network on chip (NOC) communication infrastructure. The proposed method utilizes an IEEE 1149.1 architecture based on BIST to at-speed test of crosstalk faults for inter-switch links as well as an IEEE 1500-compliant wrapper to test switches themselves in NOC communication infrastructure. The former architecture includes enhanced cells intended for MAF model test patterns generation and analysis test responses, and the later architecture includes: (a) a March decoder which decodes and executes March commands, which are scanned in serially from input system, on First-In-First-Out (FIFO) buffers in the switch; and (b) a scan chain which is defined to test routing logic block of the switch.To at-speed test inter-switch links one new instruction is used to control cells and TPG controller. Two new instructions, as well as, are applied to activate March decoder and to control scan activities in switch test session. These instructions are defined to fully comply with conventional IEEE 1149.1 and IEEE 1500 standards.     

An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip

With advance in technology and working frequency reaching gigahertz, designing and testing interconnects have become an important issue. In this paper, we proposed a BIST-based boundary scan architecture to at-speed test of crosstalk faults for inter-switch communication links in network on chip. This architecture includes enhanced cells intended for MVT model test patterns generation and analysis test responses. One new instruction is used to control cells and TPG controller in the at-speed test mode in order to fully comply with conventional IEEE 1149.1 standard.     

基于IEEE 1149.7的新一代测试接口实现与应用

随着芯片集成度的不断增加和对低功耗设计的重视,原初开发的JTAG（IEEE STD1149.1）面对新的挑战,不能满足当今设计的需要。CJTAG基于IEEE STD1149.7标准和传统的JTAG的边界扫描原理来提供一个更加强大的测试和调试的标准,来达到现在系统的要求。CJTAG用更少的管脚来提供更多的功能,而同时保证了对IEEE1149.1的软件和硬件的兼容性。     

基于IEEE1149.7的新一代测试接口实现与应用

随着芯片集成度的不断增加和对低功耗设计的重视,原初开发的JTAG（IEEE STD1149.1）面对新的挑战,不能满足当今设计的需要。CJTAG基于IEEE STD1149.7标准和传统的JTAG的边界扫描原理来提供一个更加强大的测试和调试的标准,来达到现在系统的要求。CJTAG用更少的管脚来提供更多的功能,而同时保证了对IEEE1149.1的软件和硬件的兼容性。     

Innovative Built-In Self-Test Schemes for On-Chip Diagnosis, Compliant with the IEEE 1149.4 Mixed-Signal Test Bus Standard

This paper presents a testing scheme for analog and mixed-signal circuitry compatible with the IEEE 1149.4 mixed-signal test bus standard. A high-speed dynamic current sensor is described, as well as an innovative self-diagnostic method called VDDQ. The former is used to measure signature supply currents and to compare them with the footprint of a defect-free circuit. The latter senses the quiescent nodal voltages on several nodes of the circuit under test and compares them to their nominal values. A flag is raised if significant deviations are found. Simulation results are provided for the high-speed dynamic current sensor. Through simulations the VDDQ method has performed at one node test every half millisecond and has potential for much higher speed. It is faster than currently used methods in industry, which average to 5000 nodes per minute. This will potentially allow a defect-free IC to enter the market in significantly less time than with conventional testing methods.     

IEEE 802.16e小区搜索算法的VLSI实现

小区搜索是IEEE 802.16e系统的关键技术之一.由此提出了一种低复杂度的快速联合小区搜索和整数倍频偏估计算法的VLSI结构.该结构采用差分估计方法,有效地解决了频率选择性衰落信道对检测性能的影响.详细描述了该结构的各组成单元和设计方法,并在Altera公司的EP2S130器件上进行了仿真综合验证.验证结果表明,该模块最高工作频率为103.7MHz,能够正常应用于IEEE 802.16e接收机或其他类似通信系统.     

An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment

To obtain satisfactory fault coverage for testing a logic circuit, linear feedback shift registers (LFSRs) have been used to generate not only the pseudorandom, but also the deterministic patterns in the scan-based built-in self-test environment. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time to feed deterministic patterns from the LFSR into a scan chain. In this paper we derive a general relationship between the bits in the scan chain and the states of the LFSR and show that any bit to be generated by an LFSR in any future clock cycle can be pre-generated by a linear function of the current LFSR state. With this relationship, we can divide a scan chain into multiple sub-chains and use one LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time for deterministic patterns. Moreover, due to the scan time reduction, test power wasted during the scan operation can also be significantly reduced.     

自动交换光网络的分层路由体系及其路由实现方法

本基于国际电信联盟电信标准化组织(ITU-T）相关标准及光互联论坛(OIF)有关草案,阐述了路由域分层的一般原则,给出了层次路由体系下实现路由功能的一般性原理,提出了分层路由体系下路由的实现方法。     

基于电力线通信芯片可测性设计的研究实现

集成电路的快速发展,迫切地需要快速、高效、低成本且具有可重复性的测试方案,这也成为可测性设计的发展方向。此次设计基于一款电力线通信芯片,数字部分采用传统常用的数字模块扫描链测试和存储器内建自测试;同时利用芯片正常的通信信道,引入模拟环路测试和芯片环路内建自测试,即覆盖了所有模拟模块又保证了芯片的基本通信功能,而且最大限度地减少了对芯片整体功能布局的影响。最终使芯片良率在98%以上,达到了大规模生产的要求。此设计可以为当前数模混合通信芯片的测试提供参考。     

适于运动估值VLSI实现的改进的树结构

文中给出了一种用于实现多分辨率运动估算算法后阶段任务的改进的树结构。在一个简单的RISC类型核控制下,它能够完成整个运动估值过程中除粗分辨率精度运动矢量搜索之外的所有后阶段子任务。包括运动矢量优化（搜索）在内的多任务是通过二叉树最底层叶节点上的多功能处理单元和可以拆分成子树的加法树来实现的。此外,运算单元寄存器堆的设计使能在二维方向上复用图像数据,完全避免了同一类数据从存储器中重复读取,从而实现了最小的存储器访问带宽,并有助于减小存储功耗。     

Generating a family of testable designs using the BILBO methodology

There are usually many different ways to make a digital circuit testable using the BILBO methodology. Each solution can have different values of test time and area overhead. A design system based on the BILBO methodology has been developed that can efficiently explore the testable design space to generate a family of designs ranging from the minimal test time design to the minimal area overhead design. A designer can select an appropriate design based on trade-offs between test time and area overhead. The branch and bound technique is employed during the exploring process to prune the design space. This significantly reduces the execution time of this process. To effectively bound the exploring process, a very efficient test scheduler has been developed. Unlike previous approaches, this new test scheduler can process a partially testable design as well as a complete testable design. A test schedule for a design is constructed incrementally. The test scheduling procedures are presented along with experimental results that show that this test scheduler usually outperforms existing schedulers. In many cases, it generates an optimal test schedule. Experiments have been performed on several circuits generated by MABAL, a CAD synthesis tool, to demonstrate the performance and practicality of this system.This work was supported by the Defense Advanced Research Projects Agency and monitored by the Federal Bureau of Investigation under Contract No. JFBI90092. The views and conclusions considered in this document are those of the authors and should not be interpreted as necessarily representing the official policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the U.S. Government.     

AVS高清视频环路滤波结构与电路实现

提出一种适用于AVS高清视频的环路滤波结构.该结构采用双端口存储器,在接收重建数据的同时,计算环路滤波结果,降低了输入输出延迟;通过改进滤波时序,达到较高的滤波效率;采用流水线计算滤波结果,提高了频率.对该模块进行了仿真和综合,在0.18μm工艺下,频率为200MHz,面积为18×103等效逻辑门,支持1920×1080,每秒60帧的视频解码.     

一种用于三层布线的分层算法

随着VLSI/LSI技术的发展,多层布线已能够实现。互连网络的分层问题就是要使得互连网络所需的通孔数最少。在通孔最小化问题中,如果布图拓扑逻辑已给出,这类问题被称为受限的通孔最小化(CVM)问题。本文针对三层布线中的CVM问题提出了一种分层算法,使得布图所需的通孔数最小化。应用此算法能获得比文献中所述更少的通孔数。     

一种基于分级路由的空地编队自组网方案

在现实通信中,越来越多的空间和地面单元投入使用。无线Adhoc技术的发展,使得组建一个空地一体化的编队通信自组织网络成为可能。提出了一种基于分级结构的网络组织方案,并对其分簇算法和路由协议进行了研究。     

一种MPEG2视频解码器的系统设计

对于设计像 MPEG2视频解码器的复杂系统 ,关键的难点是其系统结构的设计。文中设计了一种适合 VL SI实现的 MPEG2解码器的系统结构。它支持 MPEG2 (MP@ML)码流 ,并且兼容 MPEG1码流。为了设计和优化这个结构 ,采用硬件描述语言 VHDL 设计了系统级的 MPEG2视频解码器。此解码器在 Viewlogic系统中进行了模拟 ,并且对一些码流进行了测试验证。     

VLSI的动态功耗测试生成

本文指出，ＶＬＳＩ的最大动态功耗测试，可以通过在特定输入序列作用下使电路中的不变门数为最小值为实现，本文提出的极性推导，赋值法可以快速生成相应的输入序列，该算法与电路的输入变量数无关。