An innovative technique for packaging power electronic buildingblocks using metal posts interconnected parallel plate structures

Power electronics building blocks (PEBBs) are envisioned as integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors, and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. At the Center for Power Electronics Systems, we developed a topology for a basic building block-a two-switch two-diode half-bridge converter in totem-pole configuration with built-in gate-driver and protection circuitry, fiber-optic receiver/transmitter interface, and soft-switching capability. Based on the topology, a series of prototype modules, with 600 V, 3.3 kW rating, were fabricated using an innovative packaging technique developed for the program-metal posts interconnected parallel plate structure (MPIPPS). This new packaging technique uses direct attachment of bulk copper, not wire-bonding of fine aluminum wires, for interconnecting power devices. Electrical performance data of the packaged devices show that an air-cooled 15 kW inverter, operating from 400 V dc bus with 20 kHz switching frequency can be constructed by integrating three prototype modules, which is almost double what could be achieved with commercially packaged devices of the same rating     

Chip-scale packaging of power devices and its application inintegrated power electronics modules

A power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional (3-D) integrated power electronics modules (IPEMs) is presented in this paper. The chip-scale packaging structure, termed die dimensional ball grid array (D²BGA), eliminates wire bonds by using stacked solder joints to interconnect power chips. D²BGA package consists of a power chip, inner solder caps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniaturization possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultralow profile packaging. Electrical tests show that the V_CE(sat) and on-resistance of the D²BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D²BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported     

Three-dimensional flip-chip on flex packaging for power electronicsapplications

We have extended the concept of flip-chip technology, which is widely used in IC packaging, to the packaging of three-dimensional (3-D) integrated power electronics modules (IPEMs). We call this new approach flip-chip on flex IPEM (FCOF-IPEM), because the power devices are flip-chip bonded to a flexible substrate with control circuits. We have developed a novel triple-stacked solder bump metallurgy for improved and reliable device interconnections. In this multilayer structure, we have carefully selected packaging materials that distribute the thermo-mechanical stresses caused by mismatching coefficients of thermal expansion (CTEs) among silicon chips and substrates. We have demonstrated the feasibility of this packaging approach by constructing modules with two insulated gate bipolar transistors (IGBTs), two diodes, and a simple gate driver circuit. Fabricated FCOF-IPEMs have been successfully tested at power levels up to 10 kW. This paper presents the materials and reliability issues in the package design along with electrical, mechanical, and thermal test results for a packaged IPEM     

倒装芯片集成电力电子模块的热设计

将倒装芯片(Flip Chip, FC)技术引入三维集成电力电子模块(Integrated Power Electronic Module,IPEM)的封装,可构建FC-IPEM.在实验室完成了由两只球栅阵列芯片尺寸封装MOSFET和驱动、保护等电路构成的半桥FC-IPEM.针对半桥FC-IPEM,建立半桥FC-IPEM的一维热阻模型,分析模块主要的热阻来源.运用FLOTHERM软件进行三维仿真,得到模块温度分布结果,给出优化模块热性能的依据.     

集成电力电子模块封装的关键技术

封装技术直接影响到集成电力电子模块(Integrated Power Electronics Module,IPEM)的电气性能、EMI特性和热性能等,被公认为未来电力电子技术发展的核心推动力。介绍了IPEM封装的结构与互连和基板技术等关键技术及研究现状,分析了已存在的薄膜覆盖封装技术等三维IPEM封装技术,讨论了IPEM封装的发展趋势,最后指出我国IPEM封装技术研究的限制因素与对策。     

Design for reliability of power electronics modules

Power electronics uses semiconductor technology to convert and control electrical power. Demands for efficient energy management, conversion and conservation, and the increasing take-up of electronics in transport systems has resulted in tremendous growth in the use of power electronics devices such as Insulated Gate Bipolar Transistors (IGBT’s). The packaging of power electronics devices involves a number of challenges for the design engineer in terms of reliability. For example, IGBT modules will contain a number of semiconductor dies within a small footprint bonded to substrates with aluminum wires and wide area solder joints. To a great extent, the reliability of the package will depend on the thermo-mechanical behavior of these materials. This paper details a physics of failure approach to reliability predictions of IGBT modules. It also illustrates the need for a probabilistic approach to reliability predictions that include the effects of design variations. Also discussed are technologies for predicting the remaining life of the package when subjected to qualification stresses or in service stresses using prognostics methods.     

Three-Dimensional Packaging for Power Semiconductor Devices and Modules

Demands for increasing power density and levels of functional integration in switch-mode power converters require power electronics manufacturers to develop innovative packaging solutions for power semiconductor devices and modules. Three-dimensional (3-D) packaging techniques offer the potential of lower resistance, higher current handling capability, smaller volume, better thermal management capability, and high reliability. In this paper, we present the constructions and some electrical and thermomechanical analyses of four 3-D packaging approaches that have been developed within the Center for Power Electronics Systems—an NSF Engineering Research Center.     

Flip-chip on flex integrated power electronics modules for high-density power integration

Three-dimensional flip-chip on flex (FCOF) integrated power electronics modules (IPEMs) have been fabricated for high-density power applications. In this FCOF-IPEM structure, solder-bumped devices were flip-soldered to a flexible substrate with electrical circuits etched on both sides. One side of the flex provides interconnection to power devices while the other is used to construct a simple gate-drive circuit; via holes through the flex integrate the power stage and gate-drive together. Solder-bumped MOSFET devices were obtained by a metallization processing and were used in the FCOF power module construction to improve thermal performance, power density, and integration. With this packaging approach, the multiple solder bumps, instead of the thin, long bonding wires were utilized to connect the power devices to the flex substrate and to improve heat dissipation, lower parasitic oscillations, and reduce package size. Reliability of solder joints has been dealt with through selection of materials, such as use of flexible substrates and underfill encapsulation, and design of joint shape for lower thermomechanical stresses. A comparative study of continuous switching test results have shown that the FCOF-IPEMs have better electrical performance than commercial wire bonded power modules.     

Thermal management for multifunctional structures

Multifunctional structures (MFS) are an innovative concept that offer a new methodology for spacecraft design, eliminating chassis, cables and connectors, and integrating the electronics into the walls of the spacecraft. The MFS design consists of multilayer flexible circuit patches bonded onto a structural composite panel, and multichip modules (MCMs) performing specific functions are bonded onto the circuit patches which are interconnected via flexible circuit jumpers. Incorporation of the high power density two-dimensional (2-D) and three-dimensional (3-D) MCM's into smaller and more efficient packaging designs still has the fundamental requirement to maintain component temperatures within design limits. Higher component qualification temperatures, such as 393 K, can result in smaller spacecraft radiator areas that are consistent with efficient packaging schemes. During the MFS development effort, a structural radiator panel was fabricated using high thermal conductivity (Hi-K) composite facesheets, and several thermal management designs using combinations of Hi-K doublers (150-1500 W/m-K), Hi-K (150-700 W/m-K) corefill, and deployable radiators to maximize MCM's heat rejection. Results of the thermal vacuum tests and details of the thermal design methodology are presented in this paper     

功率模块封装结构及其技术

本文从封装角度评估功率电子系统集成的重要性。文中概述了多种功率模块的封装结构形式及其主要研发內容。另外还讨论了模块封装技术的一些新进展以及在功率电子电路系统集成中的地位和作用。     

GaN HEMT器件封装技术研究进展

GaN高电子迁移率晶体管(HEMT)器件由于其宽禁带材料的独特性能,相比硅功率器件具有击穿场强高、导通电阻低、转换速度快等优势,在智能家电、交直流转换器、光伏逆变器以及电动汽车等领域有着广泛的应用前景.但GaN HEMT器件的高功率密度和高频工作特性,给器件封装带来了极大挑战,要使其出色性能得以充分发挥,其封装结构、材...     

Thermal characterization of planar high temperature power module packages with sintered nanosilver interconnection

Many new innovations have emerged in the power electronics industry to aid in meeting the expanded market demand. In spite of that the interest in high temperature and high power applications has fueled new developments in wide bandgap semiconductor devices which are capable of operation above 200 °C, silicon devices are still prevalent in the marketplace and offer significant power ratings at affordable prices. Researches have kept pushing the limit of the application temperature of silicon devices. The key to offering functional and reliable silicon packages that can endure higher temperatures is through innovative thermal management and packaging. Effective thermal management of packaged devices can be accomplished through materials selection, design or a combination of the two. In this paper, we outline a newly designed packaging structure and the fabrication process of a functional double-sided power module switching units utilizing LTJT sintered silver for each interface. The thermal characteristics of the power module were measured in various cooling scenarios utilizing thermal transient measurements, structure function analysis and the transient dual interface method (TDIM), techniques developed by Mentor Graphics. Significant improvement of thermal performance of the fabricated module was demonstrated. The resulting improvements in thermal resistance of the power module, thermal simulation model agreement and construction, and comparison of double sided thermal results to single sided conventions are discussed.     

Recyclable,Flexible, Low‐Power Oxide Electronics

The ability to process and dimensionally scale field‐effect transistors with and on paper and to integrate them as a core component for low‐power‐consumption analog and digital circuits is demonstrated. Low‐temperature‐processed p‐ and n‐channel integrated oxide thin‐film transistors in the complementary metal oxide semiconductor (CMOS) inverter architecture are seamlessly layered on mechanically flexible, low‐cost, recyclable paper substrates. The possibility of building these circuits using low‐temperature processes opens the door to new applications ranging from smart labels and sensors on clothing and packaging to electronic displays printed on paper pages for use in newspapers, magazines, books, signs, and advertising billboards. Because the CMOS circuits reported constitute fundamental building blocks for analog and digital electronics, this development creates the potential to have flexible form factor computers seamlessly layered onto paper. The holistic approach of merging low‐power circuitry with a recyclable substrate is an important step towards greener electronics.     

共漏极双功率MOSFET封装研究

针对适用于锂电池保护电路特点要求的共漏极功率MOSFET的封装结构进行了研发和展望.从传统的TSSOP-8发展到替代改进型SOT-26,一直到芯片级尺寸的微型封装外形,其封装效率越来越高,接近100%.同时,在微互连和封装结构的改进方面,逐渐向短引线或焊球无引线、平坦式引脚、超薄型封装和漏极焊盘散热片暴露的方向发展,增...     

An Anisotropically High Thermal Conductive Boron Nitride/Epoxy Composite Based on Nacre‐Mimetic 3D Network

Polymer‐based thermal interface materials (TIMs) with excellent thermal conductivity and electrical resistivity are in high demand in the electronics industry. In the past decade, thermally conductive fillers, such as boron nitride nanosheets (BNNS), were usually incorporated into the polymer‐based TIMs to improve their thermal conductivity for efficient heat management. However, the thermal performance of those composites means that they are still far from practical applications, mainly because of poor control over the 3D conductive network. In the present work, a high thermally conductive BNNS/epoxy composite is fabricated by building a nacre‐mimetic 3D conductive network within an epoxy resin matrix, realized by a unique bidirectional freezing technique. The as‐prepared composite exhibits a high thermal conductivity (6.07 W m^?1 K^?1) at 15 vol% BNNS loading, outstanding electrical resistivity, and thermal stability, making it attractive to electronic packaging applications. In addition, this research provides a promising strategy to achieve high thermal conductive polymer‐based TIMs by building efficient 3D conductive networks.     

一种用于胎压传感器的新型系统级封装技术

TPMS IC是TPMS系统模块的关键核心器件,需要采用系统级封装(SiP)技术。对TPMS IC的一种新型SiP封装技术作了研究分析。在引线框架上引入电路板中介层,改善了芯片间电气互连与分布,增大了引入薄膜电阻电容元件的设计弹性。采用预成型模制部分芯片的封装技术,满足了IC与MEMS芯片不同的封装要求,还增强了SiP产品的可测试性和故障可分析性。采用敞口模封、灌装低应力弹性凝胶和传感器校准测试相结合的方法有效避免封装应力对MEMS压力传感器的影响。     

MCM-C金属气密封装技术

在介绍MCM-C常用金属气密封装方法的基础上,重点对MCM-C封装中工程实用性强、应用较多的平行缝焊密封工艺技术、链式炉钎焊密封工艺技术以及密封前的真空烘烤技术进行了较深入的研讨。实验结果表明,采用文中所述的MCM-C金属气密封装技术所封装的金属外壳封装MCM-C、一体化PGA封装MCM-C产品,在经受规定的环境试验、机械试验后,其结构完整性、电学有效性、机械牢固性、封装气密性均能很好地满足要求。     

Characterization of interfacial thermal resistance by acoustic micrography imaging

In high-power electronics modules, the heat generated by the power devices is transferred to the ambient environment by attaching a heat spreader to the semiconductor package to ensure efficient thermal management. Typical attachment materials introduce interfaces and/or interlayers of finite thickness. Using a scanning acoustic microscope (SAM), a non-destructive inspection tool, we can detect the cracks, voiding, porosity, coplanarity and delamination in the interface layer, which correlate to the measured thermal resistance of an interface. This investigation would result in optimizing the bonding process of the selected interface material, minimizing the void-content to ensure enhanced thermal management of power modules.     

Development of a novel stack package to fabricate high density memory modules for high-end application

A new thinking has been spreading rapidly throughout the microelectronics community in the development and application of 3D stack package. Based on the concept, the application of the 3D stack package to high density memory modules makes DRAM provides major opportunities in both miniaturization and integration for advanced and portable electronic products. In order to meet the increasing demands for smaller, higher functionality-integrated and low cost package, this paper presents a packaging method for multi-chip IC without the problem of warpage and pin leakages. Multiple chips are packaged into a single package by stacking up the chips vertically, in which the packaging method is based on the standard wire bond technology with the use of longer bonding wire, appropriate epoxy for delamination and special care in wafer thinning. The presented method promotes the yield of the packaged IC and also successfully reduces the package size. However, special circuit techniques are required to maintain the normal operation of the packaged IC, as well as to maintain the compatible operating speed and power consumption. The reliability of the IC packaged with the presented method has been examined and it verifies the high performance of the presented method.     

Multidisciplinary Electronic Package Design and Optimization Methodology Based on Genetic Algorithm

A new multidisciplinary design and optimization methodology in electronics packaging is presented. A genetic algorithm combined with multidisciplinary design and multiphysics analysis tools are used to optimize key design parameters. This methodology is developed to improve the electronic package design process by performing multidisciplinary design and optimization at an early design stage. To demonstrate its capability, the methodology is applied to a ball grid array (BGA) package design. Multidisciplinary criteria including thermal, thermal strain, electrical, electromagnetic leakage, and cost are optimized simultaneously. A simplified routability analysis criterion is used as a constraint. The genetic algorithm is used for systematic design optimization. The present methodology can be applied to electronics product design at various packaging levels.