Properties of low temperature Sn–Ag–Bi–In solder systems

The metallurgical and mechanical properties of Sn–3.5 wt%Ag–0.5 wt%Bi–xwt%In (x = 0–16) alloys and of their joints during 85 °C/85% relative humidity (RH) exposure and heat cycle test (−40–125 °C) were evaluated by microstructure observation, high temperature X-ray diffraction analysis, shear and peeling tests. The exposure of Sn–Ag–Bi–In joints to 85 °C/85%RH for up to 1000 h promotes In–O formation along the free surfaces of the solder fillets. The 85°C/85%RH exposure, however, does not influence the joint strength for 1000 h. Comparing with Sn–Zn–Bi solders, Sn–Ag–Bi–In solders are much stable against moisture, i.e. even at 85 °C/85%RH. Sn–Ag–Bi–In alloys with middle In content show severe deformation under a heat cycles between −40 °C and 125 °C after 2500 cycles, due to the phase transformation from β-Sn to β-Sn + γ-InSn₄ or γ-InSn₄ at 125 °C. Even though such deformation, high joint strength can be maintained for 1000 heat cycles.     

Electromigration of Sn–37Pb and Sn–3Ag–1.5Cu/Sn–3Ag–0.5Cu composite flip–chip solder bumps with Ti/Ni(V)/Cu under bump metallurgy

We examine electromigration fatigue reliability and morphological patterns of Sn–37Pb and Sn–3Ag–1.5Cu/Sn–3Ag–0.5Cu composite solder bumps in a flip–chip package assembly with Ti/Ni(V)/Cu UBM. The flip–chip test vehicle was subjected to test conditions of five combinations of applied electric currents and ambient temperatures, namely, 0.4 A/150 °C, 0.5 A/150 °C, 0.6 A/125 °C, 0.6 A/135 °C, and 0.6 A/150 °C. The electrothermal coupling analysis was employed to investigate the current crowding effect and maximum temperature in the solder bump in order to correlate with the experimental electromigration reliability using the Black’s equation as a reliability model. From available electromigration reliability models, we also present a comparison between fatigue lives of Sn–37Pb solder bumps with Ti/Ni(V)/Cu and those with Al/Ni(V)/Cu UBM under different current stressing conditions.     

Rapid power cycling of flip-chip and CSP components on ceramic substrates

Power cycling has been done for flip-chip and CSP components solder joined onto ceramic substrates. Cycle periods as short as 1 min were applied in the experiments where the chip temperature varied between about 30°C in the power off-state and 100–150°C in the power on-state. Disconnections of the joints were found after 4000–17 000 power cycles. The flip-chip components joined onto low temperature cofired ceramic substrate showed slightly better reliability than the components joined onto alumina substrate. Most of the samples showed clear effects of deterioration of the joints seen as increasing chip temperature for power on-state. The experimental results are compared with calculations based on modified Coffin–Manson equation as well as with one-dimensional simulations.     

Effect of primary creep and plasticity in the modeling of thermal fatigue of SnPb and SnAgCu solder joints

It has been conventional to simplify the thermo-mechanical modeling of solder joints by omitting the primary (transient) contributions to total creep deformation, assuming that secondary (steady-state) creep strain is dominant and primary creep is negligible. The error associated with this assumption has been difficult to assess because it depends on the properties of the solder joint and the temperature–time profile. This paper examines the relative contributions of plasticity, primary and secondary creep in Sn40Pb and Sn3.8Ag0.7Cu solders using the analysis of a trilayer solder joint structure with finite elements and a newly developed finite difference technique. The influences of temperature amplitude and ramp rate have been quantified. It was found that for the thermal profiles considered, the role of plasticity was negligible for trilayer assemblies with SnPb and SnAgCu solder interlayers. Furthermore, when primary creep was included for SnAgCu, the temperature-dependent yield strength was not exceeded and no plastic strains resulted. Neglect of primary creep can result in errors in the predicted stress and strain of the solder joint. Damage metrics based on the stabilized stress vs. strain hysteresis loop, for symmetric 5 min upper/lower dwell periods, differ widely when primary creep is considered compared to the secondary-only creep model. Creep strain energy density differences between the secondary-only and primary plus secondary creep models for SnPb were 32% (95 °C/min–Δ165 °C thermal profile), 32% (95 °C/min–Δ100 °C) and 35% (14 °C/min–Δ100 °C); similarly for SnAgCu, the differences were 29% (95 °C/min–Δ165 °C), 46% (95 °C/min–Δ100 °C) and 58% (14 °C/min–Δ100 °C). Accumulated creep strain differences between the secondary-only and primary plus secondary creep models for SnPb were 21% (95 °C/min–Δ165 °C), 25% (95 °C/min–Δ100 °C) and 25% (14 °C/min–Δ100 °C); similarly for SnAgCu the differences were 82% (14 °C/min–Δ100 °C), 89% (95 °C/min–Δ100 °C) and 100% (95 °C/min–Δ165 °C). In turn, these discrepancies can lead to errors in the estimation of the solder thermal fatigue life due to the changing proportion of primary creep strain to total inelastic strain under different thermal profiles, particularly for SnAgCu.     

A study in flip-chip UBM/bump reliability with effects of SnPb solder composition

This paper aims to investigate the electromigration phenomenon of under-bump-metallization (UBM) and solder bumps of a flip-chip package under high temperature operation life test (HTOL). UBM is a thin film Al/Ni(V)/Cu metal stack of 1.5 μm; while bump material consists of Sn/37Pb, Sn/90Pb, and Sn/95Pb solder. Current densities of 2500 and 5000 A/cm² and ambient temperatures of 150–160 °C are applied to study their impact on electromigration. It is observed that bump temperature has more significant influence than current density does to bump failures. Owing to its higher melting point characteristics and less content of Sn phase, Sn/95Pb solder bumps are observed to have 13-fold improvement in Mean-Time-To-Failure (MTTF) than that of eutectic Sn/37Pb. Individual bump resistance history is calculated to evaluate UBM/bump degradation. The measured resistance increase is from bumps with electrical current flowing upward into UBM/bump interface (cathode), while bumps having opposite current polarity cause only minor resistance change. The identified failure sites and modes from aforementioned high resistance bumps reveal structural damages at the region of UBM and UBM/bump interface in forms of solder cracking or delamination. Effects of current polarity and crowding are key factors to observed electromigration behavior of flip-chip packages.     

Experimental characterization and mechanical behavior analysis of intermetallic compounds of Sn–3.5Ag lead-free solder bump with Ti/Cu/Ni UBM on copper chip

Due to today’s trend towards ‘green’ products, the environmentally conscious manufacturers are moving toward lead-free schemes for electronic devices and components. Nowadays the bumping process has become a branch of the infrastructure of flip chip bonding technology. However, the formation of excessively brittle intermetallic compound (IMC) between under bump metallurgy (UBM)/solder bump interface influences the strength of solder bumps within flip chips, and may create a package reliability issue. Based on the above reason, this study investigated the mechanical behavior of lead-free solder bumps affected by the solder/UBM IMC formation in the duration of isothermal aging. To attain the objective, the test vehicles of Sn–Ag (lead-free) and Sn–Pb solder bump systems designed in different solder volumes as well as UBM diameters were used to experimentally characterize their mechanical behavior. It is worth to mention that, to study the IMC growth mechanism and the mechanical behavior of a electroplated solder bump on a Ti/Cu/Ni UBM layer fabricated on a copper chip, the test vehicles are composed of, from bottom to top, a copper metal pad on silicon substrate, a Ti/Cu/Ni UBM layer and electroplated solder bumps. By way of metallurgical microscope and scanning-electron-microscope (SEM) observation, the interfacial microstructure of test vehicles was measured and analyzed. In addition, a bump shear test was utilized to determine the strength of solder bumps. Different shear displacement rates were selected to study the time-dependent failure mechanism of the solder bumps. The results indicated that after isothermal aging treatment at 150 °C for over 1000 h, the Sn–Ag solder revealed a better maintenance of bump strength than that of the Sn–Pb solder, and the Sn–Pb solder showed a higher IMC growth rate than that of Sn–Ag solder. In addition, it was concluded that the test vehicles of copper chip with the selected Ti/Cu/Ni UBMs showed good bump strength in both the Sn–Ag and Sn–Pb systems as the IMC grows. Furthermore, the study of shear displacement rate effect on the solder bump strength indicates that the analysis of bump strength versus thermal aging time should be identified as a qualitative analysis for solder bump strength determination rather than a quantitative one. In terms of the solder bump volume and the UBM size effects, neither the Sn–Ag nor the Sn–Pb solders showed any significant effect on the IMC growth rate.     

High temperature reliability and interfacial reaction of eutectic Sn–0.7Cu/Ni solder joints during isothermal aging

The interfacial reactions and growth kinetics of intermetallic compound (IMC) layers formed between Sn–0.7Cu (wt.%) solder and Au/Ni/Cu substrate were investigated at aging temperatures of 185 and 200 °C for aging times of up to 60 days. After reflow, the IMC formed at the interface was (Cu, Ni)₆Sn₅. After aging at 185 °C for 3 days and at 200 °C for 1 day, two IMCs of (Cu, Ni)₆Sn₅ and (Ni, Cu)₃Sn₄ were observed. The growth of the (Ni, Cu)₃Sn₄ IMC consumed the (Cu, Ni)₆Sn₅ IMC at an aging temperature of 200 °C due to the restriction of supply of Cu atoms from the solder to interface. After aging at 200 °C for 60 days, the Ni layer of the substrate was completely consumed in many parts of the sample, at which point a Cu₃Sn IMC was formed. In the ball shear test, the shear strength decreased with increasing aging temperature and time. Until the aging at 185 °C for 15 days and at 200 °C for 3 days, fractures occurred in the bulk solder. After prolonged aging treatment, fractures partially occurred at the (Cu, Ni)₆Sn₅ + Au/solder interface for aging at 185 °C and at the (Ni, Cu)₃Sn₄/Ni interface for aging at 200 °C, respectively. Consequently, thick IMC layer and thermal loading history significantly affected the integrity of the Sn–0.7Cu/Ni BGA joints.     

Computational modelling for reliable flip-chip packaging at sub-100 μm pitch using isotropic conductive adhesives

This paper presents the assembly process using next generation electroformed stencils and Isotropic Conductive Adhesives (ICAs) as interconnection material. The utilisation of ICAs in flip-chip assembly process is investigated as an alternative to the lead and lead-free solder alloys and aims to ensure a low temperature (T < 100 °C) assembly process. The paper emphasizes and discusses in details the assembly of a flip-chip package based on copper columns bumped die and substrate with stencil printed ICA deposits at sub-100 μm pitch. A computational modelling approach is undertaken to provide comprehensive results on reliability trends of ICA joints subject to thermal cycling of the flip-chip assembly based on easy to use damage criteria and damage evaluation. Important design parameters in the package are selected and investigated using numerical modelling techniques to provide knowledge and understanding of their impact on the thermo-mechanical behaviour of the flip-chip ICA joints. Sensitivity analysis of the damage in the adhesive material is also carried out. Optimal design rules for enhanced performance and improved thermo-mechanical reliability of ICA assembled flip-chip packages are finally formulated.     

Effects of underfill materials on the reliability of low-K flip-chip packaging

The reliability of low-K flip-chip packaging has become a critical issue owing to the low strength and poor adhesion qualities of the low-K dielectric material when compared with that of SiO₂ or fluorinated silicate glass (FSG). The underfill must protect the solder bumps and the low-K chip from cracking and delamination. However, the material properties of underfill are contrary to those required for preventing solder bumps and low-K chip from cracking and delamination. This study describes the systematic methodologies for how to specify the adequate underfill materials for low-K flip-chip packaging. The structure of the test vehicle is seven copper layers with a low-K dielectric constant value of 2.7-2.9, produced by the chemical vapor deposition (CVD) process. Initially, the adhesion and the flow test of the underfill were evaluated, and then the low-K chip and the bumps stress were determined using the finite element method. The preliminary screened underfill candidates were acquired by means of the underfill adhesion and flow test, and balancing the low-K chip and the bumps stress simulation results. Next, the low-K chips were assembled with these preliminary screened underfills. All the flip-chip packaging specimens underwent the reliability test in order to evaluate the material properties of the underfill affecting the flip-chip packaging stress. In addition, the failed samples are subjected to failure analysis to verify the failure mechanism. The results of this study indicate that, of the underfill materials investigated, those with a glass transition temperature (T_g) and a Young’s modulus of approximately 70–80 °C and 8–10 GPa, respectively, are optimum for low-K flip-chip packaging with eutectic solder bumps.     

Reliability study of the electroless Ni–P layer against solder alloy

Copper (Cu) has been widely used in the under bump metallurgy of chip and substrate metallization for chip packaging. However, due to the rapid formation of Cu–Sn intermetallic compound (IMC) at the tin-based solder/Cu interface during solder reaction, the reliability of this type of solder joint is a serious concern. In this work, electroless nickel–phosphorous (Ni–P) layer was deposited on the Cu pad of the flexible substrate as a diffusion barrier between Cu and the solder materials. The deposition was carried out in a commercial acidic sodium hypophosphite bath at 85 °C for different pH values. It was found that for the same deposition time period, higher pH bath composition (mild acidic) yields thicker Ni–P layer with lower phosphorous content. Solder balls having composition 62%Sn–36%Pb–2%Ag were reflowed at 240 °C for 1 to 180 min on three types of electroless Ni–P layers deposited at the pH value of 4, 4.8 and 6, respectively. Thermal stability of the electroless Ni–P barrier layer against the Sn–36%Pb–2%Ag solder reflowed for different time periods was examined by scanning electron microscopy equipped with energy dispersed X-ray. Solder ball shear test was performed in order to find out the relationship between the mechanical strength of solder joints and the characteristics of the electroless Ni–P layer deposited.The layer deposited in the pH 4 acidic bath showed the weak barrier against reflow soldering whereas layer deposited in pH 6 acidic bath showed better barrier against reflow soldering. Mechanical strength of the joints were deteriorated quickly in the layer deposited at pH 4 acidic bath, which was found to be thin and has a high phosphorous content. From the cross-sectional studies and fracture surface analyses, it was found that the appearance of the dark crystalline phosphorous-rich Ni layer weakened the interface and hence lower solder ball shear strength. Ni–Sn IMC formed at the interfaces was found to be more stable at the low phosphorous content (14 at.%) layer. Electroless Ni–P deposited at mild acidic bath resulting phosphorous content of around 14 at.% is suggested as the best barrier layer for Sn–36%Pb–2%Ag solder.     

The effect of solder paste composition on the reliability of SnAgCu joints

As the electronics industry is moving towards lead-free manufacturing processes, more effort has been put into the reliability study of lead-free solder materials. Various tin–silver–copper-based solders have become widely accepted alternatives for tin–lead solders. In this study, we have tested three different SnAgCu solder compositions. The first consisted of a hypoeutectic 96.5Sn/3.0Ag/0.5Cu solder, the second of a eutectic 95.5Sn/3.8Ag/0.7Cu solder, and the third of a hypereutectic 95.5Sn/4.0Ag/0.5Cu solder. A eutectic SnPb solder was used as a reference. The test boards were temperature-cycled (−40 to +125 °C) until all samples failed. The results of the temperature cycling test were analyzed, and cross-section samples were made of the failed joints. Scanning electron and optical microscopy were employed to analyze the fracture behavior and microstructures of the solder joints. The reliability of lead-free solders and the effect of microstructures on joint reliability are discussed.     

Effects of process conditions on reliability, microstructure evolution and failure modes of SnAgCu solder joints

In this study, microstructure evolution at intermetallic interfaces in SnAgCu solder joints of an area array component was investigated at various stages of a thermal cycling test. Failure modes of solder joints were analyzed to determine the effects of process conditions on crack propagation. Lead-free printed-circuit-board (PCB) assemblies were carried out using different foot print designs on PCBs, solder paste deposition volume and reflow profiles. Lead-free SnAgCu plastic-ball-grid-array (PBGA) components were assembled onto PCBs using SnAgCu solder paste. The assembled boards were subjected to the thermal cycling test (−40 °C/+125 °C), and crack initiation and crack propagation during the test were studied. Microstructure analysis and measurements of interface intermetallic growth were conducted using samples after 0, 1000, 2000 and 3000 thermal cycles. Failures were not found before 5700 thermal cycles and the characteristic lives of all solder joints produced using different process and design parameters were more than 7200 thermal cycles, indicating robust solder joints produced with a wide process window. In addition, the intermetallic interfaces were found to have Sn–Ni–Cu. The solder joints consisted of two Ag–Sn compounds exhibiting unique structures of Sn-rich and Ag-rich compounds. A crystalline star-shaped structure of Sn–Ni–Cu–P was also observed in a solder joint. The intermetallic thicknesses were less than 3 μm. The intermetallics growth was about 10% after 3000 thermal cycles. However, these compounds did not affect the reliability of the solder joints. Furthermore, findings in this study were compared with those in previous studies, and the comparison proved the validity of this study.     

Electroless remetallization of aluminum bond pads on CMOS driverchip for flip-chip attachment to vertical cavity surface emitting lasers(VCSEL's)

A method for remetallizing the bond pads of electronic chips, which are initially metallized with aluminum or aluminum alloy is presented. Application of electroless plating process for the remetallization of aluminum to a solderable gold surface can reduce the cost and complication of the widely accepted flip-chip interconnection technology. We have developed a step by step nickel/gold wafer bumping technique (remetallized bump height is 5.0 μm) for the appropriate solder (15.0 μm of In:Pb). Variation of roughness of the remetallized surface has been studied carefully. We have completed prototype research studies on test devices and successfully packaged the flip-chip bonded hybrid pair of a CMOS driver chip and a dummy structure of vertical cavity surface emitting laser (VCSEL) array. Cross section of the flip-chip solder joint is studied. Also, adhesion strength of the metal deposit is investigated     

Thermal fatigue endurance of collapsible 95.5Sn4Ag0.5Cu spheres in LTCC/PWB assemblies

The behavior of thermomechanically loaded collapsible 95.5Sn4Ag0.5Cu spheres in LTCC/PWB assemblies with high (LTCC/FR-4; ΔCTE 10 ppm/°C) and low (LTCC/Arlon; ΔCTE < 10 ppm/°C) global thermal mismatches was studied by exposing the assemblies into two thermal cycling tests. The characteristic lifetimes of the LTCC/FR-4 assemblies, tested over the temperature ranges of 0–100 °C and −40 to 125 °C, were 1475 and 524 cycles, respectively, whereas the corresponding values of the LTCC/Arlon assemblies were 5424 and 1575 cycles. According to the typical requirements for the industrial lifetime duration of solder joints, the former values are inadequate, whereas the latter are at an acceptable level in a few cases. Furthermore, the global thermal mismatch affected the thermal fatigue behavior of the 95.5Sn4Ag0.5Cu spheres in the temperature range of −40 to 125 °C.     

Effects of different bonding parameters on the electrical performance and peeling strengths of ACF interconnection

The effects of different bonding parameters, such as temperature, pressure, curing time, bonding temperature ramp and post-processing, on the electrical performance and the adhesive strengths of anisotropic conductive film (ACF) interconnection are investigated. The test results show that the contact resistances change slightly, but the adhesive strengths increase with the bonding temperature increased. The curing time has great influence on the adhesive strength of ACF joints. The contact resistance and adhesive strength both are improved with the bonding pressure increased, but the adhesive strengths decrease if the bonding pressure is over 0.25 MPa. The optimum temperature, pressure, and curing time ranges for ACF bonding are concluded to be at 180–200 °C, 0.15–0.2 MPa, and 18–25 s, respectively. The effects of different Teflon thickness and post-processing on the contact resistance and adhesive strength of anisotropic conductive film (ACF) joints are studied. It is shown that the contact resistance and the adhesive strength both become deteriorated with the Teflon thickness increased. The tests of different post-processing conditions show that the specimens kept in 120 °C chamber for 30 min present the best performance of the ACF joints. The thermal cycling (−40 to 125 °C) and the high temperature/humidity (85 °C, 85% RH) aging test are conducted to evaluate the reliability of the specimens with different bonding parameters. It is shown that the high temperature/humidity is the worst condition to the ACF interconnection.     

Creep of thermally aged SnAgCu-solder joints

The creep behaviour of Sn96.5Ag3.5- and Sn95.5Ag3.8Cu0.7-solder was studied specifically for its dependence on technological and environmental factors. The technological factors considered were typical cooling rates and pad metallizations for solder joints in electronic packaging. The environmental factors included microstructural changes as a result of thermal aging of solder joints. Creep experiments were conducted on three types of specimens—flip–chip joints, PCB solder joints and bulk specimens. flip–chip specimens were altered through the selection of various under bump metallizations (Cu vs. NiAu), cooling rates (40 K/min vs. 120 K/min), and thermal storage (24 h, 168 h, and 1176 h at 125 °C). PCB solder joints were studied by using a copper pin soldered into a thru-hole connection on a printed circuit board having a NiAu metallization. Bulk specimens contained the pure alloys. The creep behaviour of the SnAg and SnAgCu solders varied in dependence of specimen type, pad metallization and aging condition. Constitutive models for SnAg and SnAgCu solders as they depend on the reviewed factors are provided.     

Pb-free high temperature solders for power device packaging

Reliabilities of joints for power semiconductor devices using a Bi-based high temperature solder has been studied. The Bi-based solder whose melting point is 270 °C were prepared by mixing of the CuAlMn particles and molten Bi to overcome the brittleness of Bi. Then, joined samples using the solder were fabricated and thermal cycling tests were examined. After almost 2000 test cycles of −40/200 °C test, neither intermetallic compounds nor cracks were observed for CTE (Coefficient of Thermal Expansion) matched sample with Cu interface. On the other hand, certain amount of intermetallic compound such as Bi₃Ni was found for a sample with Ni interface. In addition, higher reliability of this solder than Sn-Cu solder was obtained after −40/250 °C test. Furthermore, an example power module structure using double high temperature solder layers was proposed.     

Evaluation of Cu-bumps with lead-free solders for flip-chip package applications

Low cost electroplated Cu-bump with environmental friendly Sn solder was developed for flip-chip applications. The seed layer used was Ti/WN_x/Ti/Cu where WN_x was used as the Cu diffusion barrier and Ti was used to enhance the adhesion between bump and the chip pad. Thick negative photoresist (THB JSR-151N) with a high aspect ratio of 2.4 was used for electroplating of copper bump and Sn solder. The Sn solder cap was reflowed at 225° for 6 min at N₂ atmosphere. No wetting phenomenon was observed for the Sn solder as evaluated by energy-dispersed spectroscopy (EDS). The Cu-bump with Ti/WN_x/Ti/Cu seed layer not only have higher shear force than the Cu-bump with Ti/Cu seed layer but also has higher resistance to fatigue failure than the Au, SnCu, SnAg bumps.     

Thermally induced deformation of solder joints in real packages: Measurement and analysis

The paper presents a hybrid experimental and analytical approach to track the deformation of solder joints in an electronic package subject to a thermal process. The solder joint strain is directly measured using a computer vision technique. The strain measurement is analyzed following an approach that is devised based on an established solder constitutive relation. The analysis leads to the determination of the solder joint stress and in turn, to the separation of the elastic, plastic and creep strain from the measured total strain. The creep strain rate and stress–strain hysteresis loop are also obtained. Two case studies are presented to illustrate the applications and to show the viability of the approach. Each case involves a resistor package with SAC (Sn95.5Ag3.8Cu0.7) solder joints, which is subjected to a temperature variation between ambient and 120 °C. The results confirm that shear is a dominant strain component in such solder joints. The shear strain varies nearly in phase with the temperature whereas the shear stress exhibits a different trend of variation due to stress relaxation. The peak shear stress of around 10 MPa to 15 MPa are found, which occur at near 70 °C in both cases, when the temperature ramps up at approximately 3 °C/min. The creep shear strain goes up to 0.02 and accounts for over 80% of the total shear strain. The creep strain rate is in the order of magnitude of 10⁻⁵ s⁻¹. Responding to the temperature cycling with such moderate rate, the creep strain shows modest ratcheting while the stress–strain hysteresis stabilizes in two cycles.     

Fatigue analysis of miniaturized lead-free solder contacts based on a novel test concept

The paper presents the method of generating lifetime-prediction-laws on special prepared very stiff specimen. The combination of thin- and thick-film technology allows building up test samples on ceramic very similar to electronic packages including the measurement issues. Influences of pad surface metallurgy, microstructure of solder, ineutectic solder alloys and assembly process parameter are regarded now. The investigation objects provide monitoring of electrical and mechanical damage process of SnAgCu solder bump. Different thermo-mechanical loads will be applied in temperature ranges of 0 to +80 °C, −40 to +125 °C and −50 to +150 °C, where the temperature gradient and cycle frequency also vary. A Variation of four different chip sizes allows the determination of fatigue laws for each temperature profile, to be able to compare in between them. The results of these tests will give universal lifetime-prediction laws for SnAgCu base solder joints. Main goals are to find coefficients for lifetime prediction models such as Coffin–Manson- or Norris–Landzberg-relation, which are transferable in between different electronic packages.