由版图引起的CMOS ESD保护电路失效的分析

ESD保护电路已经成为CMOS集成电路不可或缺的组成部分,在当前CMOS IC特征尺寸进入深亚微米时代后,如何避免由ESD应力导致的保护电路的击穿已经成为CMOS IC设计过程中一个棘手的问题.光发射显微镜利用了IC芯片失效点所产生的显微红外发光现象可以对失效部位进行定位,结合版图分析以及微分析技术,如扫描电子显微镜SEM、聚焦离子束FIB等的应用可以揭示ESD保护电路的失效原因及其机理.通过对两个击穿失效的CMOS功率ICESD保护电路实际案例的分析和研究,提出了改进ESD保护电路版图设计的途径.     

Electrostatic discharge in semiconductor devices: protectiontechniques

Electrostatic discharges (ESDs) are everywhere-in our homes and businesses. Even the manufacturers of the electronics experience ESD failures in their factories. Electronic devices are sensitive to ESD. ESD results in failure of our computers, calculators, and car phones. There are ways to protect these sensitive components. This paper looks at ESD protection from a two-pronged approach: reducing the likelihood of having an ESD event and improving the robustness of the devices themselves. The first approach focuses on reducing the amount of charge that is developed and controlling the redistribution of any charges that are developed The second approach reviews ways to improve the circuit robustness by improving individual circuit elements and by adding additional elements for charge flow control and voltage clamping     

E~2PROM工艺的ESD保护电路失效分析

ESD保护电路已经成为集成电路不可或缺的组成部分,如何避免由ESD应力导致的保护电路的击穿已经成为CMOSIC设计过程中一个棘手的问题。光发射显微镜利用了IC芯片失效点所产生的显微红外发光现象可以对失效部位进行定位,结合版图分析以及微分析技术,如扫描电子显微镜SEM、微红外发光显示设备EMMI等的应用可以揭示ESD保护电路的失效原因及机理。文章通过对一组击穿失效的E2PROM工艺的ESD保护电路实际案例的分析和研究,介绍了几种分析工具,并且在ESD失效机制的基础上,提出了改进ESD保护电路的设计途径。     

IC设计中的ESD保护技术探讨

ESD是集成电路设计中最重要的可靠性问题之一。IC失效中约有40%与ESD/EOS(电学应力)失效有关。为了设计出高可靠性的IC,解决ESD问题是非常必要的。文中讲述一款芯片ESD版图设计,并且在0.35μm 1P3M 5V CMOS工艺中验证,成功通过HBM-3000V和MM-300V测试。这款芯片的端口可以被分成输入端口、输出端口、电源和地。为了达到人体放电模型(HBM)-3000V和机器放电模型(MM)-300V,首先要设计一个好的ESD保护网络。解决办法是先让ESD的电荷从端口流向电源或地,然后从电源或地流向其他端口。其次,给每种端口设计好的ESD保护电路,最后完成一张ESD保护电路版图。     

纳米集成电路的静电放电防护

综述了纳米集成电路片上(On-Chip)静电放电防护(ESD)的研究现状;结合自身流片数据,阐述其ESD防护机理和设计要点。从器件ESD防护机理入手,逐步深入分析阐述了纳米集成电路的新特征、纳米器件的失效机制以及基于体硅CMOS工艺和SOI工艺的基本ESD防护器件。在此基础上,对纳米集成电路ESD主要热击穿失效的热量产生机制、热耗散问题,以及边界热电阻对ESD防护带来的影响进行了分析,提出了利用纵向散热路径和工艺整合方案来提高纳米集成电路中ESD防护器件鲁棒性的有效措施。     

Analysis of reliability and optimization of ESD protection devices supported by modeling and simulation

An analysis of electrostatic discharge (ESD) protection structures supported by advanced 2-D mixed mode electro-thermal device and circuit simulation with calibrated electro-physical models to increase the reliability of protected IC’s is presented. The critical temperature as a criterion of device destruction is defined and experimentally verified. Numerical simulation and visualization of the internal electro-physical properties of the analyzed structures during a very short ESD pulse considerably improved the understanding of their physical behavior and contributes to a proper design and optimization of doping and geometry of the analyzed ESD protection devices. The analyzed devices are designed as protection against Human Body Model (HBM) and International Electromechanical Commission model (IEC) 61000-4-2 with very high robustness. The obtained results are shown on two examples. Modification of the device layout by splitting the cathode contact of the ESD diode into two parts allowing area reduction with improved electrical characteristics is the subject of the first example. The influence of doping fluctuations on the device robustness is presented in the second example. Different triggering and failure mechanisms of the diode and transistor structure during HBM and IEC pulse are presented.     

CMOS片上电源总线ESD保护结构设计

随着集成电路制造技术的高速发展,特征尺寸越来越小,静电放电对器件可靠性的危害也日益增大,ESD保护电路设计已经成为IC设计中的一个重要部分.讨论了三种常见的CMOS集成电路电源总线ESD保护结构,分析了其电路结构、工作原理和存在的问题,进而提出了一种改进的ESD保护电源总线拓扑结构.运用HSPICE仿真验证了该结构的正确性,并在一款自主芯片中实际使用,ESD测试通过±3 000 V.     

浅谈电子制造过程中的静电及静电防护

静电释放(ESD)就是一定数量的电荷从一个物体(例如人体)传送到另外一个物体(例如芯片)的过程。这个过程能导致在极短的时间内有一个非常高的电流通过芯片,35%以上的芯片损坏都可以归咎于此。因此,在电子制造行业里保护芯片免受静电释放的损害是非常重要的。实际上,很多公司在各种不同电子应用中都遇到了如何应对急速增长的静电防护需求的问题。通过针对ESD机制和防护做了一个较全面的介绍,包括ESD原理,电流产生,危害,防静电工艺要求等。     

浅谈电子制造过程中的静电及静电防护

静电释放（ESD）就是一定数量的电荷从一个物体（例如人体）传送到另一个物体（例如芯片）的过程。这个过程能导致在极短的时间内有一个非常高的电流通过芯片,35％以上的芯片损坏都可以归咎于此。因此,在电子制造行业里保护芯片免受静电释放的损害是非常重要的。实际上,很多企业在各种不同电子应用中都遇到了如何应对急速增长的静电防护需求的问题。文章针对ESD机制和防护做了一个较全面的介绍,包括ESD原理、电流产生、危害、防静电工艺要求等。     

浅谈电子制造过程中的静电及静电防护

静电释放(ESD)就是一定数量的电荷从一个物体(例如人体)传送到另外一个物体(例如芯片)的过程。这个过程能导致在极短的时间内有一个非常高的电流通过芯片,35%以上的芯片损坏都可以归咎于此。因此,在电子制造行业里保护芯片免受静电释放的损害是非常重要的。实际上,很多公司在各种不同电子应用中都遇到了如何应对急速增长的静电防护需求的问题。针对ESD机制和防护做了一个较全面的介绍,包括ESD原理,电流产生,危害,防静电工艺要求等。     

浅谈电子制造过程中的静电及静电防护

静电放电（ESD）就是一定数量的电荷从一个物体（例如人体）传送到另外一个物体（例如芯片）的过程。这个过程能导致在极短的时间内有一个非常高的电流通过芯片,35％以上的芯片损坏都可以归咎于此。因此,在电子制造行业里保护芯片免受静电放电的损害是非常重要的。实际上,很多公司在各种不同电子应用中都遇到了如何应对急速增长的静电防护需求的问题。针对ESD机制和防护作了一个较全面的介绍,包括ESD原理、电流产生、危害、防静电工艺要求等。     

Design optimization of ESD protection and latchup prevention for a serial I/O IC

ESD/latchup are often two contradicting variables during IC reliability development. Trade-off between the two must be properly adjusted to realize ESD/latchup robustness of IC products. A case study on SERIAL Input/Output (I/O) IC’s is reported here to reveal this ESD/latchup optimization issue. SERIAL I/O IC features a special clamping property to wake up PC’s during system standby situation. Along with high voltage operation, Input/Output (I/O) protection design of this IC becomes one of the most challenging tasks in the product reliability development. In the initial development phase, ignorance of latchup susceptibility resulted in severe Electrical Overstress (EOS) damage during latchup tests, and also gave a false over estimate of ESD protection threshold through parasitic latchup paths. The latchup origin is an output PMOS and floating-well ESD triggering NMOS beside the PMOS, and the main fatal link is this high-voltage (HV) NMOS connecting to a bi-directional SCR cell. This fatal link led to totally five latchup sites and three latchup paths clarified through careful and intensive FIB failure analysis, while this powerful SCR ESD device without appropriate triggering mechanism still could not provide sufficient product-level ESD hardness. Owing to there being no design window between ESD and latchup, the original several protection schemes were all abandoned. Using this bi-directional SCR ESD cell and proper triggering PNP bipolar transistors, a new I/O protection circuit could sustain at least ESD/HBM 4 kV and latchup triggering current 150 mA tests, thus accomplish the best optimization of ESD/latchup robustness.     

Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology

NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection capability. All of them are usually based on a similar circuit scheme with multiple-stage inverters to drive the main ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage inverter and 1-stage inverter controlling circuits have been studied to verify the optimal circuit schemes in the NMOS-based power-rail ESD clamp circuits. Besides, the circuit performances among the main ESD clamp NMOS transistors drawn in different layout styles cooperated with the controlling circuit of 3-stage inverters or 1-stage inverter are compared. Among the NMOS-based power-rail ESD clamp circuits, an abnormal latch-on event has been observed under the EFT test and fast power-on condition. The root cause of this latch-on failure mechanism has been clearly explained by the emission microscope with InGaAs FPA detector.     

一种新型低漏电ESD电源箝位电路

在到达纳米级工艺后,传统的静电放电防护(ESD)电源箝位电路的漏电对集成电路芯片的影响越来越严重。为降低漏电,设计了一种新型低漏电ESD电源箝位电路,该箝位电路通过2个最小尺寸的MOS管形成反馈来降低MOS电容两端的电压差。采用中芯国际40 nm CMOS工艺模型进行仿真,结果表明,在相同的条件下,该箝位电路的泄漏电流仅为32.59 nA,比传统箝位电路降低了2个数量级。在ESD脉冲下,该新型ESD箝位电路等效于传统电路,ESD器件有效开启。     

Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs

The RC-based power-rail electrostatic-discharge (ESD) clamp circuit with big field-effect transistor (BigFET) layout style in the main ESD clamp n-channel metal–oxide–semiconductor (NMOS) transistor was widely used to enhance the ESD robustness of a CMOS IC fabricated in advanced CMOS processes. To further reduce the occupied layout area of the RC in the power-rail ESD clamp circuit, a new ESD-transient detection circuit realized with smaller capacitance has been proposed and verified in a 0.13- $muhbox{m}$ CMOS process. From the experimental results, the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit can achieve a long-enough turn-on duration and higher ESD robustness under ESD stress condition, as well as better immunity against mistrigger and latch-on event under the fast-power-on condition.      

ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins

This paper reports a real case of electrostatic discharge (ESD) improvement on a complementary metal oxide semiconductor integrated circuit (IC) product with multiple separated power pins. After ESD stresses, the internal damage have been found to locate at the interface circuit connecting between different circuit blocks with different power supplies. Some ESD designs have been implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp N-channel metal oxide semiconductor with a channel width of 10 /spl mu/m between the interface node and the ground line, the human-body-model (HBM) ESD level of this IC product can be improved from the original 0.5 to 3 kV. By connecting the separated vertical sync signal (VSS) power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the enhanced version IC product with 12 separated power supplies pairs can be significantly improved from original 1 kV up to > 5 kV, without the noise coupling issue.     

CMOS集成电路中ESD保护技术研究

分析ESD失效的原因和失效模式,针对亚微米CMOS工艺对器件ESD保护能力的降低,从工艺、器件、电路三个层次对提高ESD保护能力的设计思路进行论述。工艺层次上通过增加ESD注入层和硅化物阻挡层实现ESD能力的提高;器件方面可针对电路的特点,选择合适的器件(如MOS,SCR,二极管及电阻)达到电路需要的ESD保护能力;电路方面采用栅耦和实现功能较强的ESD保护。     

Oscillatory Transmission Line Pulsing for Characterization of Device Transient Response

An oscillatory transmission line pulse generation system is introduced. This measurement system allows one to observe the response of an electrostatic discharge (ESD) protection device to a large-amplitude radio-frequency damped sinusoid; such waveforms mimic ESD tests. The trigger voltage of silicon-controlled rectifiers used for ESD protection is observed to be dependent on the past state of the device, due to charge storage in the bipolar bases.      

Study of CDM specific effects for a smart power input protection structure

A Charged Device Model (CDM) specific ESD failure mechanism is discussed for an input protection structure in a smart power technology. The input structure shows unexpected dependency of the CDM robustness on design variations of the input resistor. This paper demonstrates that circuit simulation reproduced the complex failure mechanism accurately after elements like package parameters, substrate resistance, parasitic pn-junctions and the resistance of parasitic physical layers were considered. The importance of accurately modeling these factors for achieving meaningful conclusions for CDM failure mechanisms and CDM robustness from circuit simulation is presented. For validation of the proposed simulation setup, results from circuit simulation are compared to measurements and device simulation.     

ESD protection strategies in advanced CMOS SOI ICs

This paper represents a part of the ESREF 2007 tutorial on the design of IC protection circuits built with advanced deep sub-micron CMOS silicon-on-insulator (SOI) technologies. The tutorial covers fundamental aspects of active rail clamp Electrostatic Discharge (ESD) protection approach to meet the human body model (HBM), machine model (MM), and charged device model (CDM) requirements in SOI ICs. The paper focuses on 65 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. It compares pulsed measurement results of SOI MOSFETs and diodes to bulk devices. It also introduces a response surface method (RSM) to optimize device sizes in the ESD networks.