Impact of downscaling on high-frequency noise performance of bulk and SOI MOSFETs

Parameters limiting the improvement of high-frequency noise characteristics for deep-submicrometer MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that the intrinsic Pucel's noise P, R, and C parameters are not strongly modified by the device scaling. The limitation of the noise performance versus the downscaling process is mainly related to the frequency performance (f/sub max/) of the device. It is demonstrated that for MOSFETs with optimized source, drain, and gate accesses, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high-frequency noise performance of ultra deep-submicrometer MOSFETs.     

Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors

It has been known that using selective epitaxial growth (SEG) of silicon, to elevate source/drain regions, is beneficial to digital CMOS by reducing the junction leakage. In addition, this architecture also reduces the gate resistance by enabling a T-shape gate and allowing thicker silicides, which is beneficial for RF-CMOS regarding increased maximum oscillation frequency (f/sub max/) and lowering of the noise figure (NF). In this paper, we report the impact of the SEG-deep source/drain implant (DSDI) process sequence and Co silicide thickness on DC and RF performance of NMOS transistors. Up to a 28%-45% improvement in f/sub max/ is achievable due to a T-shaped gate and thicker Co, made possible by an elevated source/drain (/sup E/S/D) architecture. The maximum transconductance (g/sub m/) of the /sup E/S/D device reaches a value of 1100 mS/mm, which in turn gives a very high f/sub T/ of 150 GHz. The low gate sheet resistance obtained with this architecture is also very beneficial for suppressing noise figure in the low-noise amplifier (LNA) circuit demonstrated in this paper. Furthermore, it is shown by simulation that the noise performance of an RF LNA improves due to the SEG and the Co thickness in the T-shaped gate of the NMOS transistor.     

High microwave and noise performance of 0.17-/spl mu/m AlGaN-GaN HEMTs on high-resistivity silicon substrates

AlGaN-GaN high-electron mobility transistors (HEMTs) based on high-resistivity silicon substrate with a 0.17-/spl mu/m T-shape gate length are fabricated. The device exhibits a high drain current density of 550 mA/mm at V/sub GS/=1 V and V/sub DS/=10 V with an intrinsic transconductance (g/sub m/) of 215 mS/mm. A unity current gain cutoff frequency (f/sub t/) of 46 GHz and a maximum oscillation frequency (f/sub max/) of 92 GHz are measured at V/sub DS/=10 V and I/sub DS/=171 mA/mm. The radio-frequency microwave noise performance of the device is obtained at 10 GHz for different drain currents. At V/sub DS/=10 V and I/sub DS/=92 mA/mm, the device exhibits a minimum-noise figure (NF/sub min/) of 1.1 dB and an associated gain (G/sub ass/) of 12 dB. To our knowledge, these results are the best f/sub t/, f/sub max/ and microwave noise performance ever reported on GaN HEMT grown on Silicon substrate.     

Structural optimization of SUTBDG devices for low-power applications

In this paper, we investigate the impact of physical structure on the performance of symmetric ultrathin body double-gate devices for low-operating-power (LOP) applications. Devices with regular raised source/drain (S/D) structures have optimal spacer thicknesses governed by a tradeoff between fringing capacitance and series resistance. Expanded S/D structures improve on regular raised S/D structures by slowing down the increases in both fringing capacitance with gate height and series resistance with spacer thickness. The cost is more chip area and process complexity. Pure high-/spl kappa/ gate dielectrics raise the off-state current (I/sub OFF/) due to the fringing field-induced barrier lowering effect. Suppressing the I/sub OFF/ increase requires either a significant reduction in equivalent oxide thickness or a significant shift in gate work function. If the gate work function is tuned to maintain a fixed I/sub OFF/, devices with less abrupt S/D-channel junctions suffer a drive current (I/sub ON/) degradation, and devices with weakly coupling S/D and relatively thick bodies gain improvements in I/sub ON/. The I/sub ON/ of a device with metal S/D is significantly lower than required for LOP applications, if the S/D Schottky barrier height (SBH) is over 200 meV. We also briefly discuss the impact of mobility degradation on this structural optimization.     

AlGaN/GaN MIS-HFETs with f/sub T/ of 163 GHz using cat-CVD SiN gate-insulating and passivation Layers

Al/sub 0.4/Ga/sub 0.6/N/GaN heterostructure field-effect transistors (HFETs) with an AlGaN barrier thickness of 8 nm and a gate length (L/sub G/) of 0.06-0.2 /spl mu/m were fabricated on a sapphire substrate. We employed two novel techniques, which were thin, high-Al-composition AlGaN barrier layers and SiN gate-insulating, passivation layers formed by catalytic chemical vapor deposition, to enhance high-frequency device characteristics by suppressing the short channel effect. The HFETs with L/sub G/=0.06-0.2 /spl mu/m had a maximum drain current density of 1.17-1.24 A/mm at a gate bias of +1.0 V and a peak extrinsic transconductance of 305-417 mS/mm. The current-gain cutoff frequency (f/sub T/) was 163 GHz, which is the highest value to have been reported for GaN HFETs. The maximum oscillation frequency (f/sub max/) was also high, and its value derived from the maximum stable gain or unilateral gain was 192 or 163 GHz, respectively.     

Scaling of characteristic frequencies in RF CMOS

Device simulation of the 180-, 90-, and 65-nm CMOS generations shows that in NMOSTs, the cut-off frequency f/sub T/ and the maximum oscillation frequency f/sub max/ are roughly inversely proportional to the gate length. The voltage-gain bandwidth f/sub A/ depends only weakly on the gate length. At 40-nm gate length, f/sub T/ values of 300 GHz are predicted. For small values of the drain and source contact resistance (<10/sup -8/ /spl Omega//spl middot/cm/sup 2/), f/sub T/ can only be improved by a further reduction of the gate length. The f/sub max/ values (for zero gate resistance higher than f/sub T/) degrade strongly with increasing gate resistance. Simple approximate formulas for the dependence of f/sub T/ and f/sub A/ on the contact resistances are presented.     

High breakdown voltage (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs quasi-enhancement-mode pHEMT with field-plate technology

A high breakdown voltage and a high turn-on voltage (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs quasi-enhancement-mode (E-mode) pseudomorphic HEMT (pHEMTs) with field-plate (FP) process is reported for the first time. Between gate and drain terminal, the transistor has a FP metal of 1 /spl mu/m, which is connected to a source terminal. The fabricated 0.5/spl times/150 /spl mu/m/sup 2/ device can be operated with gate voltage up to 1.6 V owing to its high Schottky turn-on voltage (V/sub ON/=0.85 V), which corresponds to a high drain-to-source current (I/sub ds/) of 420 mA/mm when drain-to-source voltage (V/sub ds/) is 3.5 V. By adopting the FP technology and large barrier height (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P layer design, the device achieved a high breakdown voltage of -47 V. The measured maximum transconductance, current gain cutoff frequency and maximum oscillation frequency are 370 mS/mm, 22 GHz , and 85 GHz, respectively. Under 5.2-GHz operation, a 15.2 dBm (220 mW/mm) and a 17.8 dBm (405 mW/mm) saturated output power can be achieved when drain voltage are 3.5 and 20 V. These characteristics demonstrate that the field-plated (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P E-mode pHEMTs have great potential for microwave power device applications.     

547-GHz f/sub t/ In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As HEMTs with reduced source and drain resistance

We fabricated 30-nm gate pseudomorphic channel In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As high electron mobility transistors (HEMTs) with reduced source and drain parasitic resistances. A multilayer cap structure consisting of Si highly doped n/sup +/-InGaAs and n/sup +/-InP layers was used to reduce these resistances while enabling reproducible 30-nm gate process. The HEMTs also had a laterally scaled gate-recess that effectively enhanced electron velocity, and an adequately long gate-channel distance of 12nm to suppress gate leakage current. The transconductance (g/sub m/) reached 1.5 S/mm, and the off-state breakdown voltage (BV/sub gd/) defined at a gate current of -1 mA/mm was -3.0 V. An extremely high current gain cutoff frequency (f/sub t/) of 547 GHz and a simultaneous maximum oscillation frequency (f/sub max/) of 400 GHz were achieved: the best performance yet reported for any transistor.     

Influences of sulfur passivation on temperature-dependent characteristics of an AlGaAs/InGaAs/GaAs PHEMT

The influences of (NH/sub 4/)/sub 2/S/sub x/ treatment on an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) are studied and demonstrated. Upon the sulfur passivation, the studied device exhibits better temperature-dependent dc and microwave characteristics. Experimentally, for a 1/spl times/100 /spl mu/m/sup 2/ gate/dimension PHEMT with sulfur passivation, the higher gate/drain breakdown voltage of 36.4 (21.5) V, higher turn-on voltage of 0.994 (0.69) V, lower gate leakage current of 0.6 (571) /spl mu/A/mm at V/sub GD/=-22 V, improved threshold voltage of -1.62 (-1.71) V, higher maximum transconductance of 240 (211) mS/mm with 348 (242) mA/mm broad operating regime (>0.9g/sub m,max/), and lower output conductance of 0.51 (0.53) mS/mm are obtained, respectively, at 300 (510) K. The corresponding unity current gain cutoff frequency f/sub T/ (maximum oscillation frequency f/sub max/) are 22.2 (87.9) and 19.5 (59.3) GHz at 250 and 400 K, respectively, with considerably broad operating regimes (>0.8f/sub T/,f/sub max/) larger than 455 mA/mm. Moreover, the relatively lower variations of device performances over wide temperature range (300/spl sim/510 K) are observed.     

Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs

A planar double-gate SOI MOSFET (DG-SOI) with thin channel and thick source/drain (S/D) was successfully fabricated. Using both experimental data and simulation results, the S/D asymmetric effect induced by gate misalignment was studied. For a misaligned DG-SOI, there is gate nonoverlapped region on one side and extra gate overlapped region on the other side. The nonoverlapped region introduces extra series resistance and weakly controlled channel, while the extra overlapped region introduces additional overlap capacitance and gate leakage current. We compared two cases: bottom gate shift to source side (DG/spl I.bar/S) and bottom gate shift to drain side (DG/spl I.bar/D). At the same gate misalignment value, DG/spl I.bar/S resulted in a larger drain-induced barrier lowering effect and smaller overlap capacitance at drain side than DG/spl I.bar/D. Because of reduced drain-side capacitance, the speed of three-stage ring oscillator of DG/spl I.bar/S, with 20% gate misalignment length (L/sub mis/) over gate length (L/sub g/), or L/sub mis//L/sub g/=20%, was faster than that of two-gate aligned DG-SOI.     

Hot-carrier effects in P-channel modified Schottky-barrier FinFETs

High-performance p-channel modified Schottky-barrier SOI FinFETs (MSB pFinFETs) with low temperature source/drain annealing process was recently suggested for future nano-scale devices. In this letter, the hot-carrier (HC) immunity of the MSB pFinFETs with different gate lengths (L/sub g/) and fin widths (W/sub f/) are presented. The experimental data shows that the MSB pFinFET with narrower W/sub f/ has less hot carrier degradation than that with wider W/sub f/. The effects of electrical field in Si fins induced from lateral-gate electrode and the degree of uniformity of source/drain extension are illustrated cautiously by two-dimensional simulation and transmission electron microscopy (TEM) micrographs, respectively. It is found that the devices with narrower W/sub f/ have weaker electrical field from gate electrode and better uniformity of source/drain extension resulting in superior hot-carrier immunity. The projected operation voltage at ten years dc lifetime exceeds 1.6 V as the W/sub f/ is narrower than 60 nm. It is thus concluded that the MSB pFinFET would be a very promising nano device.     

High-frequency performance of submicrometer channel-length siliconMOSFETs

Polycide-gate silicon n-channel MOSFETs were fabricated on the basis of a standard 0.5-μm MOS technology and measured over the 1.5-26.5-GHz frequency range, in order to investigate the effects of channel-length reduction on device behavior at high frequency. Excellent microwave performances were obtained with a maximum operating frequency (f_max) and a unity-current-gain frequency f _t near 20 GHz for 0.5-μm-gate-length NMOS devices. An equivalent circuit for a MOSFET with its parasitic elements was extracted from measured S-parameter data. The influence of gate resistance, gate-to-drain overlap capacitance, substrate conductivity, and the transit-time effect between the source and drain on microwave characteristics was analyzed     

Trade-offs and challenges of short channel design on millimetre-wave power performance of GaN HFETs

For the application of undoped AlGaN/GaN HFETs to Ka-band millimetre(mm)-wave high frequency power performance, the maximum frequency of oscillation, f/sub max/, was found to be seriously limited by gate resistance and output conductance with the gate length down to 0.1 /spl mu/m. This makes it difficult for devices to achieve both high f/sub T/ and f/sub max/ at the same time. However, the technology of field-plate gate, to increase device breakdown voltage, will add extra gate capacitance. It makes the optimum gate structure design more important. The influence of gate metal thickness and gate length on f/sub max/ based on the lumped small signal circuit model analysis and the possibility to obtain high f/sub T/ and f/sub max/ simultaneously for the GaN material structure is discussed for application to the Ka-band mm-wave operating system.     

Dependence of current-gain cutoff frequency on gate length in submicron GaInAs/AlInAs MODFETs

Investigates the gate length (L/sub g/) dependence of the current-gain cutoff frequency f/sub T/ in lattice-matched GaInAs/AlInAs MODFETs. The transconductance is found to be relatively insensitive to gate length in this submicron regime, while the f/sub T/ increases with decreasing gate length due to reduced capacitance as dictated by the charge control model. An effective saturation velocity of 1.3*10/sup 7/ cm/s is deduced from the f/sub T/-L/sub g/ dependence. A maximum f/sub T/ of 112 GHz is measured on an L/sub g/=0.15 mu m device, limited mainly by parasitic charge in the AlInAs.<>     

AlGaN/GaN HEMTs on SiC with f/sub T/ of over 120 GHz

AlGaN/GaN high electron mobility transistors (HEMTs) grown on semi-insulating SiC substrates with a 0.12 /spl mu/m gate length have been fabricated. These 0.12-/spl mu/m gate-length devices exhibited maximum drain current density as high as 1.23 A/mm and peak extrinsic transconductance of 314 mS/mm. The threshold voltage was -5.2 V. A unity current gain cutoff frequency (f/sub T/) of 121 GHz and maximum frequency of oscillation (f/sub max/) of 162 GHz were measured on these devices. These f/sub T/ and f/sub max/ values are the highest ever reported values for GaN-based HEMTs.     

DC and RF characteristics of E-mode Ga/sub 0.51/In/sub 0.49/P-In/sub 0.15/Ga/sub 0.85/As pseudomorphic HEMTs

The DC and RF characteristics of Ga/sub 0.49/In/sub 0.51/P-In/sub 0.15/Ga/sub 0.85/As enhancement- mode pseudomorphic HEMTs (pHEMTs) are reported for the first time. The transistor has a gate length of 0.8 /spl mu/m and a gate width of 200 /spl mu/m. It is found that the device can be operated with gate voltage up to 1.6 V, which corresponds to a high drain-source current (I/sub DS/) of 340 mA/mm when the drain-source voltage (V/sub DS/) is 4.0 V. The measured maximum transconductance, current gain cut-off frequency, and maximum oscillation frequency are 255.2 mS/mm, 20.6 GHz, and 40 GHz, respectively. When this device is operated at 1.9 GHz under class-AB bias condition, a 14.7-dBm (148.6 mW/mm) saturated power with a power-added efficiency of 50% is achieved when the drain voltage is 3.5 V. The measured F/sub min/ is 0.74 dB under I/sub DS/=15 mA and V/sub DS/=2 V.     

Metal gate work function engineering on gate leakage of MOSFETs

We present a systematic study of tunneling leakage current in metal gate MOSFETs and how it is affected by the work function of the metal gate electrodes. Physical models used for simulations were corroborated by experimental results from SiO/sub 2/ and HfO/sub 2/ gate dielectrics with TaN electrodes. In bulk CMOS results show that, at the same capacitance equivalent oxide thickness (CET) at inversion, replacing a poly-Si gate by metal reduces the gate leakage appreciably by one to two orders of magnitude due to the elimination of polysilicon gate depletion. It is also found that the work function /spl Phi//sub B/ of a metal gate affects tunneling characteristics in MOSFETs. It is particularly significant when the transistor is biased at accumulation. Specifically, the increase of /spl Phi//sub B/ reduces the gate-to-channel tunneling in off-biased n-FET and the use of a metal gate with midgap /spl Phi//sub B/ results in a significant reduction of gate to source/drain extension (SDE) tunneling in both n- and p-FETs. Compared to bulk FET, double gate (DG) FET has much lower off-state leakage due to the smaller gate to SDE tunneling. This reduction in off-state leakage can be as much as three orders of magnitude when high-/spl kappa/ gate dielectric is used. Finally, the benefits of employing metal gate DG structure in future CMOS scaling are discussed.     

High-temperature thermal stability performance in /spl delta/-doped In/sub 0.425/Al/sub 0.575/As--In/sub 0.65/Ga/sub 0.35/As metamorphic HEMT

We report, to our knowledge, the best high-temperature characteristics and thermal stability of a novel /spl delta/-doped In/sub 0.425/Al/sub 0.575/As--In/sub 0.65/Ga/sub 0.35/As--GaAs metamorphic high-electron mobility transistor. High-temperature device characteristics, including extrinsic transconductance (g/sub m/), drain saturation current density (I/sub DSS/), on/off-state breakdown voltages (BV/sub on//BV/sub GD/), turn-on voltage (V/sub on/), and the gate-voltage swing have been extensively investigated for the gate dimensions of 0.65/spl times/200 /spl mu/m/sup 2/. The cutoff frequency (f/sub T/) and maximum oscillation frequency (f/sub max/), at 300 K, are 55.4 and 77.5 GHz at V/sub DS/=2 V, respectively. Moreover, the distinguished positive thermal threshold coefficient (/spl part/V/sub th///spl part/T) is superiorly as low as to 0.45 mV/K.     

The study of hot-carrier stress on poly-Si TFT employing C-V measurement

The degradation of n-type and p-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) due to hot-carrier stress was investigated by capacitance-voltage (C-V) measurement. In C-V measurements, the fixed charges in the gate oxide of TFTs are not affected by a small-applied signal, whereas the trap states in the bandgap respond to the applied frequency, so that the dominant degradation mechanism of poly-Si TFTs can be evaluated. The capacitance (C/sub GS/) between the source and the gate, as well as the capacitance (C/sub GD/) between the drain and the gate, were measured. The difference between the C/sub GD/ and the C/sub GS/ indicates the location of degradation in the TFT. Our experimental results showed that the degradation of n-type TFTs was caused by additional trap states in the grain boundary, whereas the degradation of p-type TFTs was caused by electron trapping into the gate oxide.     

Molybdenum gate technology for ultrathin-body MOSFETs and FinFETs

Damage-free sputter deposition and highly selective dry-etch processes have been developed for molybdenum (Mo) metal gate technology, for application to fully depleted silicon-on-insulator ( devices such as the ultrathin body (UTB) MOSFET and double-gate FinFET. A plasma charge trap effectively eliminates high-energy particle bombardment during Mo sputtering; hence the gate-dielectric integrity (TDDB, Q/sub BD/) is significantly improved and the field-effect mobility in Mo-gated MOSFETs follows the universal mobility curve. The effects of etch process parameters such as chlorine (Cl/sub 2/) and oxygen (O/sub 2/) gas flow rate, and source and bias radio frequence powers, were investigated in order to optimize the Mo etch rate and selectivity to SiO/sub 2/. A highly selective etch process was successfully applied to pattern Mo gate electrodes for UTB MOSFETs and FinFETs without leaving any residue or stringers. Measured electrical characteristics and physical analysis results are discussed.