一种无栅氧化物介电强度退化的二硅化钼/薄多晶硅栅新工艺

本文详细地分析了高温退火后在二硅化钼/薄n~+多晶硅(<1000A)栅结构中栅氧化层介电强度退化的情况。同时分析了栅氧化层绝缘特性和多晶硅中磷浓度、多晶硅原生氧化物,二硅化钼薄层电阻等各方面因素之间的关系,给出了二硅化钼、多晶硅、栅氧化物结构扫描电子显微镜、透射电子显微镜的观测结果。通过分析得出下列结论:高温退火时,在有阻挡层存在的情况下(阻挡层指二硅化钼淀积之前所形成的多硅上原生的厚氧化物),多晶硅与硅化钼局部作用会透过薄多晶硅层造成栅氧化物的损坏。根据分析结果,我们研究了一种没有介电强度退化的Mosi_2/薄Poly—si栅工艺。该工艺将二硅化钼直接淀积到未掺杂多晶硅上,从而控制多晶硅原生氧化物的生长,然后再将磷注入到二硅化钼中。这种工艺提供了很好的栅氧化层介电强度(薄到500A的多晶硅栅器件也是如此),易干法腐蚀,不产生多晶硅钻蚀,器件特性稳定,比通常的多晶硅栅工艺可靠性好。     

用镶嵌工艺制作金属/高k晶体管

东芝公司的研究人员认为,２ｍｍ以下的薄栅介质是开发高性能晶体管的最佳材料。这意味着栅材料从现在采用的重掺杂多晶硅栅和ＳｉＯ２栅氧化层向金属栅和高ｋ栅介质材料发展。 金属栅与多晶硅栅相比,其优点是不受栅耗尽效应的影响。高ｋ介质的优点是介质材料具有较高的介质常数（ｋ值）以及较低的隧道电流密度。同时,由于它们具有较大的电容,所以在相似的电特性下,能淀积的膜层厚度比二氧化硅膜厚。高ｋ材料包括Ｔａ氧化层、Ｔｉ氧化层、Ｚｒ氧化层以及Ｈｆ氧化层。 促使开发镶嵌栅工艺的一个因素是用反应离子刻蚀薄栅氧化层图形太难,…     

伽马射线辐照总剂量对CMOS／SIMOX器件的影响

我们把用SIMOX工艺所形成的纵向隔离结构和新开发的横向隔离结构结合起来,研制出抗辐照CMOS/SIMOX器件。 n沟MOSFET的纵向隔离由多层高浓度氧掺杂多晶硅和埋层二氧化硅组成,横向隔离由多层薄的侧壁二氧化硅、侧壁多晶硅和厚的场二氧化硅组成。p沟MOSFET的纵向隔离结构与n沟MOSFET相同,但其横向隔离中没有侧壁多晶硅层,而是使用厚的场二氧化硅层。高浓度氧掺杂多晶硅和侧壁多晶硅层用来屏蔽被俘获在埋层二氧化硅和场二氧化硅中的辐照感生正电荷。利用这些隔离结构和薄栅二氧化硅层开发的CMOS/SIMOX器件,即使在经受2Mrad(Si)的~(60)Co伽马射线辐照之后,仍具有良好的工作特性。     

在不同的推进气氛中硼与磷对二氧化硅层的穿通扩散

据研究发现,当采用掺杂多晶硅作为扩散源时,硼与磷会扩散到热生长二氧化硅层中去,这种扩散的快慢与推进气氛有关,在氢气中扩散最快。根据双边界扩散模型,我们计算出了扩散系数。硼在二氧化硅中的扩散系数比磷大约要大两个数量级。这点对于硅栅工艺来说非常重要。在 P 沟硅栅晶体管中.由于硼从掺杂多晶硅栅电极扩散到栅氧化层中去,从而会引起晶体管性能的不稳定。     

含氧硅化钛膜的等离子腐蚀

如果低电阻率的硅钛栅被用于按比例缩小的MOS器件,硅化钛的各向异性腐蚀是必要的。CCl_4、CF_4等离子体以及离子铣都可用来腐蚀硅化钛/多晶硅复合膜,每一种方法都表现于一些缺点。由于硅化物含氧量高及CCl_4等离子腐蚀的腐蚀选择比大(对二氧化硅的腐蚀速率低),因而CCl_4等离子腐蚀时会产生残留物并且腐蚀表面粗糙。CF_4反应离子腐蚀和离子铣刻蚀是光洁的腐蚀,但存在对下面的薄栅SiO_2膜的过腐蚀问题。然而,综合这些方法就能成功地加工出上述结构的各向导性图形。首先用腐蚀选择性差的CF_4反应离子腐蚀的光洁腐蚀刻透氧化物,随后用具有较高腐蚀选择比的Cl_2等离子腐蚀刻透硅化物下的多晶硅层至薄栅SiO_2层。     

超薄LPCVD二氧化硅膜栅介质

本文介绍低温生长的薄LPCVD二氧化硅膜经短时间热退火后，热氮化后的物理及电学性质。与热生长二氧化硅膜性质进行比较，结果表明，LPCVD二氧化硅膜许多性质优于热生长二氧化硅膜。适合做MOS晶体管的栅介质。文中重点指出，小于10nm的超薄的LPCVD二氧化硅膜经快速热退火或热氮化后做MOS晶体管的栅介质，其电学特性优于热生长二氧化硅膜做栅介质的MOS晶体管。在低温器件及超大规模集成电路中有广泛的应用前景。     

MNOS存贮管存贮栅的工艺控制技术

介绍一种军用专用集成电路的核心器件──ＭＮＯＳ管。存贮栅是该存贮管的制作关键，存贮栅由薄二氧化硅层和氮化硅复合膜组成。着重论述了复合膜中较难制作的薄二氧化硅即薄栅（２．１５±０．１５ｎｍ）的工艺控制。     

硼扩散引起薄SiO2栅介质的性能退化

采用表沟p+多晶硅栅/PMOSFET代替埋沟n+多晶硅栅/PMOSFET具有易于调节阈值电压、降低短沟效应和提高器件开关特性的优点,因而在深亚微米CMOS工艺中被采纳.但是多晶硅掺杂后的高温工艺过程会使硼杂质扩散到薄栅介质和沟道区内,引起阈值电压不稳定和栅介质击穿性能变差.迄今为止对硼扩散退化薄栅介质可靠性的认识并不是很明朗,为此本文考察了硼扩散对薄栅介质击穿电荷和Fowler-Nordheim (FN)电应力产生SiO2/Si界面态的影响.     

功率VDMOS器件ESD防护结构设计研究

随着半导体工艺的不断发展,器件的特征尺寸在不断缩小,栅氧化层也越来越薄,使得器件受到静电放电破坏的概率大大增加。为此,设计了一种用于保护功率器件栅氧化层的多晶硅背靠背齐纳二极管ESD防护结构。多晶硅背靠背齐纳二极管通过在栅氧化层上的多晶硅中不同区域进行不同掺杂实现。该结构与现有功率VDMOS制造工艺完全兼容,具有很强的鲁棒性。由于多晶硅与体硅分开,消除了衬底耦合噪声和寄生效应等,从而有效减小了漏电流。经流片测试验证,该ESD防护结构的HBM防护级别达8 kV以上。     

金属栅将取代多晶硅栅

为了克服器件尺寸缩小达到O．lum时,与多晶硅栅和薄栅氧化物有关的诸多问题,如栅耗尽、高阻栅、沟道区内的棚渗透、栅氧化隧道漏泄等等,也许很有必要采用金属栅和高k柳材料。1999年在旧金山召开的国际电子器件会议上,讨论了金属棚和可替换栅介质材料。如东芝公司微电子工程实验室具体介绍了开发生产金属栅的镶嵌工艺,以及工艺中所用到的高介质常数栅绝缘体（Ta刃。）。当浅沟槽隔离（ST）形成后,就进行源／漏注入,与用生长在虚拟棚氧化物上的SIP4／多晶硅薄膜制作的虚拟栅自对准。用LPCVD淀积预金属介质膜SIO。,并用CMP平面…     

Decrease of gate oxide dielectric constant in tungsten polycidegate processes

The gate oxide thickness for tungsten (W) polycide gate processes is studied, with tungsten silicide (WSi_x) deposited either by chemical vapor deposition (CVD) or sputtering. For WSi_x deposited by CVD, it is found that the effective thickness of gate oxide as determined by CV measurement increases in all cases if the annealing temperature is 900°C or higher. However, high-resolution transmission electron microscopy (TEM) measurement indicates that the physical thickness does not change after a 900°C anneal. In this case, the dielectric constant of the gate oxide decreases by 7%. As the annealing temperature increases to 1000°C, CV and TEM measurements give the same thickness and the decrease of the dielectric constant disappears. In contrast, for WSi_x film deposited by sputtering, annealing at 900°C has no effect on the gate oxide thickness as measured by CV and TEM     

Electrical and compositional properties of TaSi2 films

Tantalum silicide (TaSi₂) thin films were sputter deposited on p- and n-type silicon substrates using ultrapure TaSi₂ targets. The TaSi₂/Si samples were annealed in nitrogen or forming gas or oxygen containing steam at temperatures in the range of 400–900°C. The sheet resistances of TaSi₂/Si were measured by four-point probe before and after anneal. The structure of these films was investigated using x-ray diffraction (XRD) methods. It has been found that the sheet resistance decreases with the increase in annealing temperature and also with the increase in film thickness. X-ray diffraction patterns show changes in the morphological structure of the films. Oxidation characteristics of the film have been investigated in the temperature range of 400–900°C in oxygen containing steam ambient. The oxidation time ranged from 0.5 to 1.5 h. No oxide formation of the tantalum silicide films was observed in this investigation. This has been attributed to the high purity of TaSi₂ sputter targets used in the preparation of the films.     

Effects of alloying elements on cobalt silicide formation

Alloying elements can substantially affect the formation of cobalt silicide. A comprehensive study of phase formation was performed on 23 Co alloys with alloying element concentrations ranging from 1 at.% up to 20 at.%. Using in-situ characterization techniques in which x-ray diffraction (XRD) and elastic-light scattering are monitored simultaneously, we follow the formation of the silicide phases and the associated variation in surface roughness in real time during rapid thermal annealing. For pure Co silicide, we detect the formation of all stable silicide phases (Co₂Si, CoSi, and CoSi₂) as well as abnormal grain growth in the Co film and thermal degradation of the silicide layer at high temperatures. The effect of the various additives on phase formation was determined. The roughness of the interface was also measured using grazing incidence x-ray reflectivity (GIXR). We show that by selecting an alloy with a specific composition, we can change the phase-formation temperatures and modify the final CoSi₂ film texture and roughness.     

用弹道电子发射显微术研究超薄金属硅化物/硅肖特基接触

采用弹道电子发射显微术 ( BEEM)技术对超薄 Pt Si/Si、Co Si2 /Si肖特基接触特性进行了研究 ,并与电流 -电压 ( I- V)及电容 -电压 ( C- V)测试结果进行了对比 .研究了 Ar离子轰击对超薄Pt Si/n- Si肖特基接触特性的影响 .BEEM、I- V/C- V技术对多种样品的研究结果表明 ,I- V/C- V测试会由于超薄硅化物层串联电阻的影响而使测试结果产生严重误差 ;BEEM测试则不受影响 .随着离子轰击能量增大 ,肖特基势垒高度降低 ,且其不均匀性也越大 .用 BEEM和变温 I- V对超薄 Co Si2 /n- Si肖特基二极管的研究结果表明 ,变温 I- V测试可在一定程度上获得肖特基势垒     

Ion-beam mixed ultra-thin cobalt suicide (CoSi2) films by cobalt sputtering and rapid thermal annealing

The influence of ion-beam mixing on ultra-thin cobalt silicide (CoSi₂) formation was investigated by characterizing the ion-beam mixed and unmixed CoSi₂ films. A Ge⁺ ion-implantation through the Co film prior to silicidation causes an interface mixing of the cobalt film with the silicon substrate and results in improved silicide-to-silicon interface roughness. Rapid thermal annealing was used to form Ge⁺ ion mixed and unmixed thin CoSi₂ layer from 10 nm sputter deposited Co film. The silicide films were characterized by secondary neutral mass spectroscopy, x-ray diffraction, tunneling electron microscopy (TEM), Rutherford backscattering, and sheet resistance measurements. The experi-mental results indicate that the final rapid thermal annealing temperature should not exceed 800°C for thin (<50 nm) CoSi₂ preparation. A comparison of the plan-view and cross-section TEM micrographs of the ion-beam mixed and unmixed CoSi₂ films reveals that Ge⁺ ion mixing (45 keV, 1 × 10¹⁵ cm⁻²) produces homogeneous silicide with smooth silicide-to-silicon interface.     

硅化钨MIP电容侧墙淀积工艺优化

硅化钨MIP工艺在集成电路和半导体器件制造中有着广泛的应用,但硅化钨膜在后续的侧墙工艺中容易出现剥落问题现象。通过对硅化钨材料特性,以及与电路制造相关联工艺的深入分析,发现在一定温度下,硅化钨的表面会产生富钨硅化物,它与氧气反应时会形成氧化钨,从而造成硅化钨膜的剥落。为避免氧化钨的形成,从减少富钨硅化物的形成、降低钨化硅与氧气的反应温度,以及减少参与反应的氧气量三个方面着手,在大量工艺试验的基础上提出了一种能有效防止硅化钨膜剥落的优化工艺。     

Arsenic redistribution induced by low-temperature Ni silicidation at 450°C on shallow junctions

Redistribution of arsenic (As) during silicidation of a 13-nm Ni film on an n⁺/p junction at 450°C is investigated. NiSi formation is observed by x-ray diffraction, micro-Raman scattering spectroscopy, and Rutherford backscattering spectroscopy (RBS). Both secondary ion mass spectroscopy and RBS data indicate the redistribution and accumulation of As into two layers after the low-temperature annealing. The deeper accumulation peak, located just near the silicide/silicon interface, is attributed to As segregation from silicide into Si substrate. The shallower accumulation peak is located in a vacancy-cluster layer several nanometers below the silicide film surface. The vacancy-cluster layer, characterized by cross-sectional transmission electron microscopy, separates the silicide film into two layers, and is attributed to the well-known Kirkendall effect.     

固相反应和离子注入制备硅化镍薄膜

采用固相反应和镍离子注入硅方法分别制备了硅化镍薄膜，利用卢瑟福背散射谱（RBS) , X射线衍射（XRD）和喇曼光谱对它们的成分和结构进行了表征. 结果表明固相反应方法中，硅化镍薄膜的相结构取决于不同的热退火条件，纯相的NiSi2薄膜需要在高温（1123K）下两步热退火才能获得. 而利用离子注入方法，则可以在较低温度（523K）下直接得到单相的NiSi2薄膜. 在30～400K范围内测量了它们的电阻率和霍尔迁移率随温度的变化关系，结果表明固相反应制备的NiSi和NiSi2薄膜都表现出典型的金属性电导行为，而离子注入制备的NiSi2薄膜则表现出完全不同的电学性质.     

New Observations in LOD Effect of 45-nm P-MOSFETs With Strained SiGe Source/Drain and Dummy Gate

Length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are systematically investigated. In the non-SiGe devices, the LOD effect is dominated by the STI stress and shows a little dependence of dummy poly gates. However, in the SiGe device, the LOD effect is strongly dependent on the location of the dummy poly gate. For dummy poly gate located outside the active area, the compressive stress from the SiGe S/D dominates the LOD effect, but for dummy poly gate located within the active area, the LOD effect is controlled by both the SiGe S/D stress within the dummy gate and the STI stress. The mechanisms of our new observations are analyzed with TCAD simulations.      

Microstructure and properties of multilayer-derived tungsten silicide

In metallization, peeling and oxidation of tungsten silicide are the most serious problems of tungsten rich silicide. In this study, multilayer-derived silicon rich tungsten silicide with the silicon film on the outermost surface is investigated to avoid these problems. The dependence of sheet resistance on the annealing conditions is studied. X-ray diffraction results indicate that silicide formation is nearly completed after 30 min annealing at 750° C. Microstructures of silicide and polycides are investigated by electron microscopy. Silicide deposited on SiO₂ has smaller grains that deposited on poly-Si. A resistivity of 60 μΩ-cm is obtained for multilayer-derived WSi_2.3.