4H-SiC BJT的Early电压分析

通过考虑缓变基区4H-SiC BJT电流增益及器件内4种载流子复合过程,计算了4H-SiC BJT的厄利(Early)电压,分析了Early电压及电流增益的温度特性.结果表明,其他参数不变时,Early电压VA随发射区掺杂浓度NE增大而增大,随集电区掺杂浓度Nc增大而减小,随基区宽度W增大而增大.SiC中杂质非完全离化会影响4H-SiC BJT的Early电压及电流增益的温度特性.     

双外延基区4H-SiC BJTs的高温特性研究

基于4H-SiC的材料特性及双外延基区BJTs的工作原理,依据漂移扩散及复合理论,求解在考虑4种复合机制下的双极晶体管直流增益,并通过二维仿真模型对其在高温条件下的工作特性进行了计算分析。结果表明,随着温度的升高,基区离化率的增加会导致发射极注入效率下降,从而降低器件的直流增益。同时,SiC/SiO2 界面态及钝化层的质量会影响器件的表面复合速度,从而造成大电流下直流增益的显著下降。     

6H-SiC基混合肖特基/PiN二极管反向恢复及少子特性研究北大核心CSCD

反向恢复特性是衡量混合肖特基/PiN(MPS)二极管开关性能最重要的参数之一。本文对6H-SiC基MPS二极管结构参数与反向恢复峰值电流、反向恢复电压之间的关系进行了数值模拟仿真,分析了器件关断过程中过剩少数载流子分布,以此就6HSiC基MPS器件结构参数对反向恢复特性的影响进行了研究。结果表明:结构参数P+区结深、P+区掺杂浓度的增加,或肖特基区占比的减小,均会引起反向恢复峰值电流、反向恢复峰值电压的增大。究其根本,是器件结构参数改变引起了漂移区下少数载流子发生产生、复合、抽运等一系列变化。综合考虑反向恢复峰值电流、反向恢复峰值电压与软恢复特性,得出6H-SiC基MPS最佳优化参数:P+结深为3.8~4.0μm,肖特基区的占比为48%~56%,P+掺杂浓度为5.0×1018/cm3。     

适用于低温和多种Ge分布的SiGeHBT电流增益模型

在前人优秀工作的基础上,叙述了一个适用于低温和多种基区Ｇｅ组分分布的ＳｉＧｅ－ＨＢＴ电流增益的解析模型,详细推出了它的模型公式。该模型考虑了基区处于非平衡态下的载流子准弹道输运效应对集电极电流Ｊｃ和电流增益β的影响,并考虑了ＳｉＧｅ材料迁移率及本征载流子浓度随温度的变化。解析模型的计算结果与数值模拟结果符合较好,证明了解析模型是可信的和有一定精度的。模型计算结果表明：均匀Ｇｅ分布、较低的发射区掺杂浓度和较宽的基区有利于ＳｉＧｅＨＢＴ在低温下具有较大的电流增益。     

功率SiGe/Si HBT的温度特性

测量了Si/SiGe HBT在23~260℃温度范围内的Gummel图、理想因子n、不同基极电流下的发射结电压VBE、电流增益β、共发射极输出特性,以及Early电压VA的变化情况。结果表明,随电流和温度的增加,β减少,VBE随温度的变化率dVBE/dT小于同质结Si BJT。在高集电极-发射极电压和大电流下,在输出特性曲线上观察到了负微分电阻(NDR)特性。结果还显示,电流增益-Early电压积与温度的倒数(1/T)呈线性关系,这对模拟电路应用是很重要和有用的。     

Si和SiGe三极管Early效应模型及在电路仿真器中的应用综述

Early效应作为表征双极器件关键性能的因素之一,影响输出跨导、传输电流、基区渡越时间、电流增益、扩散电容等器件特性。本文从Early效应的基本定义出发,综述了Early电压的起源,模型的发展及其在Si和SiGe电路仿真器中的应用。具体为：（1）综述了Si三极管中的基本模型及在SPICE中处理过程,然后针对SPICE的缺陷,描述了VBIC模型中针对Early效应的改进。（2）由于SPICE和VBIC不能有效描述SiGe HBT中基区Ge组分引入。本文基于SiGe HBT标准化模型Mextram、HICUM对SiGe HBT的建模思想,综述了将其用于建立Early电压模型的方法。（3）总结了现有主流模型对Early效应的建模方法及优缺点。     

双极性晶体管电流增益的研究

在传统双极性晶体管（简称BJT）的Gummel曲线中电流增益β都只有一个波峰（简称单峰）,然而现在实验室实测数据得到BJT的增益特征曲线出现了两个波峰的现象（简称双峰）,针对双峰现象建立器件模型,并分别从器件的结构和基极发射极和集电极的掺杂浓度上进行分析,得到基极的掺杂浓度和掺杂位置影响器件产生双峰现象。     

一种具有阶梯变掺杂基区的SiC光控晶体管

提出并研究了一种具有阶梯变掺杂基区的SiC光控晶体管.通过Silvaco TACD计算机仿真平台,对具有阶梯变掺杂基区的SiC光控晶体管与常规均匀掺杂基区的SiC光控晶体管的性能进行了对比分析.结果表明,阶梯变掺杂基区结构可以产生加速载流子输运的感生电场,缩短基区渡越时间,改善器件开通性能.该结构提高了SiC光控晶体管的电流增益并缩短开通时间,但同时会损失部分关断性能.仿真结果显示,当变掺杂区浓度梯度为4.5×1020 cm-4时,电流增益与开通时间改善幅度分别达到18％和32％,关断时间增加了约22％.     

微波晶体管电流增益和基极电流非理想因子的温度特性

本文研究了微波晶体管电流增益H_FE和基极电流非理想因子n随温度变化的机理,给出了电流增曾H_FE的温度模型,指出:(1)中电流时电流增益H_PE具有正温度系数,而在小电流时随温度上升迅速增大,在大电流时增大减缓,并会出现负增值,(2)基极电流非理想因子n具有负温度系数.实验结果和理论分析一致.     

一种新型4H-SiC BJT结终端结构研究

设计了一种应用于4H-SiC BJT的新型结终端结构。该新型结终端结构通过对基区外围进行刻蚀形成单层刻蚀型外延终端,辅助耐压的p+环位于刻蚀型外延终端的表面,采用离子注入的方式,与基极接触的p+区同时形成。借助半导体数值分析软件SILVACO,对基区外围的刻蚀厚度和p+环的间距进行了优化。仿真分析结果表明,当刻蚀厚度为0.8μm,环间距分别为8,10和9μm时,能获得最高击穿电压。新结构与传统保护环(GR)和传统结终端外延(JTE)相比,BVCEO分别提高了34%和15%。利用该新型终端结构,得到共发射极电流增益β>47、共发射极击穿电压BVCEO为1 570V的4H-SiC BJT器件。     

An implanted-emitter 4H-SiC bipolar transistor with high currentgain

An epi-base, implanted-emitter, npn bipolar transistor which showed a maximum common emitter current gain (β) of ~40, the highest current gain reported for BJT in any polytype of SiC has been experimentally demonstrated in 4H-SiC. The forward drop was ~1 V at forward current density of 50 A/cm². The current gain decreases hence specific on-resistance increases with increasing temperature. The negative temperature coefficient of β makes the device attractive for paralleling and for preventing thermal runaways     

Implantation-Free 4H-SiC Bipolar Junction Transistors With Double Base Epilayers

This letter reports the first 4H-SiC power bipolar junction transistor (BJT) with double base epilayers which is completely free of ion implantation and hence of implantation-induced crystal damages and high-temperature activation annealing-induced surface roughness. Based on this novel design and implantation-free process, a 4H-SiC BJT was fabricated to reach an open base collector-to-emitter blocking voltage of over 1300 V, with a common-emitter current gain up to 31. Improvements on reliability have also been observed, including less forward voltage drift (< 2%) and no significant degradation on current gain in the active region.     

1000-V, 30-A 4H-SiC BJTs with high current gain

This paper presents the development of 1000 V, 30A bipolar junction transistor (BJT) with high dc current gain in 4H-SiC. BJT devices with an active area of 3/spl times/3 mm/sup 2/ showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm/sup 2/, at a forward voltage drop of 2 V. A common-emitter current gain of 40, along with a low specific on-resistance of 6.0m/spl Omega//spl middot/cm/sup 2/ was observed at room temperature. These results show significant improvement over state-of-the-art. High temperature current-voltage characteristics were also performed on the large-area bipolar junction transistor device. A collector current of 10A is observed at V/sub CE/=2 V and I/sub B/=600 mA at 225/spl deg/C. The on-resistance increases to 22.5 m/spl Omega//spl middot/cm/sup 2/ at higher temperatures, while the dc current gain decreases to 30 at 275/spl deg/C. A sharp avalanche behavior was observed at a collector voltage of 1000 V. Inductive switching measurements at room temperature with a power supply voltage of 500 V show fast switching with a turn-off time of about 60 ns and a turn-on time of 32 ns, which is a result of the low resistance in the base.     

Modeling the temperature-dependent Early voltage of a silicongermanium heterojunction bipolar transistor

This paper compares the temperature-dependent Early voltage of a silicon germanium heterojunction bipolar transistor (HBT) to that of a silicon bipolar junction transistor (BJT) fabricated with identical geometry. Derived is an isothermal expression for the forward Early voltage specifically suited to the base composition of a SiGe HBT. The expression includes two fit factors, one for the Si_1-xGe_x alloy and the other for the nonuniform doping density. The fit factors are functions of the device temperature and are determined through pulsed bias measurements     

4H-SiC npn BJT特性研究

基于二维器件仿真软件Medici对4H-SiC双极型晶体管(BJT)进行了建模,包括能带模型、能带窄变模型、迁移率模型、产生复合模型和不完全电离模型,为4H-SiC的工艺与器件提供了设计平台.在此基础上对4H-SiC BJT器件进行了模拟研究.结果显示,器件基极电流I_B=1μA/μm时发射极电流增益β为32.4,击穿电压BV_CEO大于800V,截止频率f_T接近1GHZ.     

Fabrication and Characterization of High-Current-Gain 4H-SiC Bipolar Junction Transistors

This paper reports on newly developed high-performance 4H-SiC bipolar junction transistors (BJT) with improved current gain and power handling capabilities based on an intentionally designed continuously grown 4H-SiC BJT wafer. The measured dc common-emitter current gain is as high as 70, the specific on -state resistance $(R_{{rm SP}hbox{-}{rm ON}})$ is as low as 3.0 $hbox{m}Omegacdothbox{cm}^{2}$, and the open-base breakdown voltage $(V_{rm CEO})$ reaches 1750 V. Large-area 4H-SiC BJTs with a footprint of 4.1 $times$ 4.1 mm have been successfully packaged into a high-gain $(beta = hbox{50.8})$ high-power (80 A $times$ 700 V) all-SiC copack and evaluated at high temperature up to 250 $^{circ}hbox{C}$. Small 4H-SiC BJTs have been stress tested under a continuous collector current density of 100 $hbox{A}/hbox{cm}^{2}$ for 24 h and, for the first time, have shown no obvious forward voltage drift and no current gain degradation. Numerical simulations and experimental results have confirmed that simultaneous high current gain and high open-base breakdown voltage could be achieved in 4H-SiC BJTs.      

高频4H-SiC双极晶体管的研制

研制出国内第一个高频4H-SiC双极晶体管.该器件采用了双台面结构和叉指结构,室温下的最大直流电流增益(β)为3.25,集电结击穿电压BVCBO达200 V.器件的β随温度的升高而降低,具有负的温度系数,这种特性使该器件容易并联,避免出现热失控现象.器件的高频特性由矢量网络分析仪测量得到,截止频率.fT为360 MHz、最高振荡频率fmax为160 MHz.     

平面结构4H-SiC BJT击穿特性及终端技术研究

4H-SiC双极晶体管（BJT）主要应用于大功率器件,器件的阻断特性是最重要的性质之一,因此提高器件的耐高压能力非常重要。国内外的高校和研究机构在SiC器件击穿特性的研究方面进行了大量研究。但是目前绝大多数研究都是基于垂直型4H-SiC BJT,而对于平面型4H-SiC BJT击穿特性的研究相对较少。本论文对采取结终端扩展(JTE)和浮空场限环(FFLRs)两种基本结终端结构的平面型器件的击穿特性和击穿机理进行了比较和分析,并在此基础上进行了器件结构优化设计。     

4H-SiC power bipolar junction transistor with a very low specific ON-resistance of 2.9 m/spl Omega//spl middot/cm/sup 2/

This letter reports a newly achieved best result on the specific ON-resistance (R/sub SP/spl I.bar/ON/) of power 4H-SiC bipolar junction transistors (BJTs). A 4H-SiC BJT based on a 12-/spl mu/m drift layer shows a record-low specific-ON resistance of only 2.9 m/spl Omega//spl middot/cm/sup 2/, with an open-base collector-to-emitter blocking voltage (V/sub ceo/) of 757 V, and a current gain of 18.8. The active area of this 4H-SiC BJT is 0.61 mm/sup 2/, and it has a fully interdigitated design. This high-performance 4H-SiC BJT conducts up to 5.24 A at a forward voltage drop of V/sub CE/=2.5 V, corresponding to a low R/sub SP-ON/ of 2.9 m/spl Omega//spl middot/cm/sup 2/ up to J/sub c/=859 A/cm/sup 2/. This is the lowest specific ON-resistance ever reported for high-power 4H-SiC BJTs.     

High-voltage implanted-emitter 4H-SiC BJTs

Implanted-emitter, epi-base, npn 4H-SiC bipolar junction transistors (BJTs) which show maximum blocking voltage of 500 V and common-emitter current gain (β) of 8 are demonstrated. Compared to the previous results (BV_CEO of 60 V and β of 40), the blocking voltage is greatly improved with reduced current gain due to a decrease of the base transport factor. The samples also show negative temperature coefficient of β, similar to the previous samples, easing device paralleling problems