一种改进型CORDIC算法的FPGA实现

为实现CORDIC算法在二、三象限内的点的反正切函数的计算,提出了在传统CORDIC算法基础上增加两级初次迭代的改进措施,给出了改进后算法的硬件流水线实现结构,并在FPGA芯片EP1S10F484C5上仿真实现.仿真结果表明:修正后的CORDIC算法的运算结果与反正切函数的理论计算值基本一致,误差很小,可以实现平面上任意一点反正切函数的求解.     

CORDIC算法在正交调制技术的应用

首先介绍了CORDIC算法和正交调制技术的基本原理,对CORDIC算法的内核及前处理单元做了详细分析,给出了一种基于流水线的CORDIC算法的正交信号发生器。在传统CORDIC算法的基础之上,通过采用流水线技术和增加迭代次数,对参数进行了优化设计,提高了计算速度和计算精度,用HDL对其编程以及进行时序仿真和FPGA硬件下载实现。     

基于CORDIC的精确快速幅相解算方法

针对传统CORDIC算法进行高精度幅度相位解算时迭代次数过多、时延较长、相位收敛较慢等局限,提出了一种基于最佳一致逼近方法的幅度与相位补偿算法,即利用传统CORDIC算法迭代一定次数后得到的向量信息,采用最佳一致逼近方法对幅度和相位分区间进行一阶多项式补偿,有效提高了计算精度.仿真及实测结果表明,对传统CORDIC算法4次迭代后的结果进行补偿,幅度相对误差可达到10^-5量级、相位绝对误差可达到10^-5度量级,最大输出时延不大于100ns.在使用部分专用乘法器的条件下,寄存器消耗降低了42.5%,查找表消耗降低了15.5%.采用该补偿算法,每多一次CORDIC迭代其相位精度可提高约一个数量级.因此,本文提出的补偿CORDIC算法在迭代次数、计算精度等方面优于传统CORDIC算法,适合于高精度计算的场合.     

一种快速迭代的坐标旋转机结构

最简单超越函数硬件实现方法是基于移位加的坐标旋转机算法CORDIC，这种方法的结构简单规则，能以固定结构实现多种超越函数的计算。文章介绍了这种算法的工作方式和具体应用，引入冗余数计算以减少单次迭代的延迟。同时讨论了冗余计算结构所需的尺度因子补偿，并提出了一种减小迭代次数的混合基结构。     

一种基于贪婪算法的CORDIC改进算法

针对传统串行坐标旋转数字计算方法(CORDIC)耗时且占用较多资源的缺点,提出了一种旋转模式下CORDIC算法的新型改进算法,该改进算法可用来代替直接数字频率合成器(DDS)查找表进行正余弦的计算。通过采用贪婪算法实现对CORDIC旋转方向与旋转角度的优化,从而可以达到串行转并行和减少迭代次数、节约资源的目的。该算法可以应用于三角函数的复杂函数的硬件实现中。仿真结果表明,在迭代次数相同的情况下,改进算法较传统算法可以获得更高的精度。最后,在Xilinx FPGA的Spartan-3E芯片上实现了改进的CORDIC结构。与传统CORDIC算法相比,在运算精度为10-5时,可以节省Slices、LUTs(Look Up Tables)资源分别为28%和25%。     

80位嵌入式超越函数运算器的设计

基于移位加的CORDIC算法是最简单超越函数硬件实现方法。本文介绍了这种算法的工作方式和计算超越函数的具体过程,设计了一个80位嵌入式超越函数运算器,并从该处理器的设计构思和系统结构到处理器内部各单元的设计进行了比较详尽的阐述,最后给出了对该设计进行软件仿真的结果。     

基于CORDIC算法的数字鉴频方法及其在FPGA中的实现

本文给出了一种适合FPGA实现的基于CORDIC(Coordinate Rotation Digital Computer)算法的数字鉴频方法.首先讨论了利用CORDIC算法进行数字鉴相和一阶差分数字鉴频的原理,然后分别给出在FPGA中实现CORDIC算法的流水结构和迭代结构,通过与XILINX自带CORDIC IPCore资源利用情况的比较及FPGA仿真结果表明,基于CORDIC算法的迭代结构和一阶差分实现数字鉴频的方法是高效可行的.     

基于双曲正切函数的变步长盲均衡算法

针对同定步长常模算法（CMA）的缺点,提出一种新的基于双曲正切函数的变步长方法。该变步长算法同时结合误差函数和迭代次数两个凶素,对步长进行调整。仿真结果表明,这种新的变步长算法可以在一定程度上改善收敛速度和收敛精度的矛盾,使CMA算法获得较好的收敛性能。     

基于CORDIC的指数函数的FPGA实现

指数函数的应用领域十分广泛。本文首先介绍CORDIC算法双曲系统的基本原理及其计算模式.对CORDIC内核及前处理单元做了详细分析。在迭代算法的基础之上.采用流水线技术.以面积换速度.给出了一种基于流水线的CORDIC:算法来实现指数函数.具有很高的精度和很快的速度.使设计出的软核能够在精度要求很高的场合中运行。用Verilog HDL对其编程设计.进行功能仿真和时序仿真.及下载测试.结果表明该函数具有很好的实用性。     

基于折叠变换的CORDIC算法实现

在现代数字信号处理领域中,CORDIC算法是一种重要的数学计算方法。该算法采用一种迭代的方式,运算简便,被广泛应用于乘除法、开方以及一些三角函数运算当中。但CORDIC算法需要较高的迭代级数以保证运算精度,在进行FPGA实现时仍然会消耗较多的硬件逻辑资源。为进一步减少CORDIC算法实现时的资源消耗,设计并实现了一种基于折叠变换的CORDIC算法。相比传统的流水结构CORDIC算法,该折叠结构的CORDIC算法消耗的硬件资源大大减少。文中给出了这一方法的实现结构,并给出了仿真结果。     

Evaluation of CORDIC Algorithms for FPGA Design

This paper presents a study of the suitability for FPGA design of full custom based CORDIC implementations. Since all these methods are based on redundant arithmetic, the FPGA implementation of the required operators to perform the different CORDIC methods has been evaluated. Efficient mappings on FPGA have been performed leading to the fastest implementations. It is concluded that the redundant arithmetic operators require a 4 to 5 times larger area than the conventional architecture and the speed advantages of the full custom design has been lost. That is due to the longer routing delays caused by the increase of the fan-out and the number of nets. Therefore, the redundant arithmetic based CORDIC methods are not suitable for FPGA implementation, and the conventional two's complement architecture leads to the best performance.     

基于CORDIC算法的数字下变频

采用CORDIC算法设计实现数字下变频（DDC）。该设计方法克服了传统的数控振荡器（NCO）查找表（LUT）大的缺点,且该算法模块同时实现数控振荡器和混频器的功能,省去了2个硬件乘法器。这种方法能够有效地提高信号处理效率,减小硬件实现的代价,通过仿真证明了该方法的有效性和高效性。最终实现的下变频模块可以工作在200MHz的系统时钟之下,占用FPGA资源约9％。     

基于CORDIC算法的Hough变换及其FPGA实现

为了既能提高Hough变换的计算速度,同时能保持精度以及不大的存储量,讨论了Hough变换和CORDIC算法各自的特点,论证了用CORDIC算法实现Hough变换的可行性。研究了采用流水线构架的CORDIC算法,提出了一种基于CORDIC混合基算法的特殊处理器来计算Hough变换,使迭代次数减少1/4,并可显著改善迭代的速度。这种方法占用资源面积比较小,并且结构规则简单,适合于FPGA设计实现,具有较高应用价值。     

新型全数字三相SPWM发生器的设计与实现

传统SPWM（正弦脉宽调制）波形产生是通过查找表来产生正弦信号的,其查找表占用大量存储资源,增加芯片的面积和成本。文中自行研制了一种新型三相SPWM信号产生芯片,采用流水线结构CORDIC（坐标旋转数字计算机）算法实时计算正弦值,并且采用地址合成与数据分离、分时复用等技术,进一步减小了资源占用与成本。实验结果表明该芯片在节省硬件资源的同时能够达到设计的指标,具有一定的工程实际意义和应用前景。     

Application of Reconfigurable CORDIC Architectures

Reconfiguration enables the adaption of Coordinate Rotation DIgital Computer (CORDIC) units to the specific needs of sets of applications, hence creating application specific CORDIC-style implementations. Reconfiguration can be implemented at a high level, taking the entire CORDIC unit as a basic cell (CORDIC-cells) implemented in VLSI, or at a low level such as Field-Programmable Gate Arrays (FPGAs). We suggest a design methodology and analyze area/time results for coarse (VLSI) and fine-grain (FPGA) reconfigurable CORDIC units. For FPGAs we implement CORDIC units in Verilog HDL and our object-oriented design environment, PAM-Blox. For CORDIC-cells, multiple reconfigurable CORDIC modules are synthesized with state-of-the-art CAD tools. At the algorithm level we present a case study combining multiple CORDICs based on a geometrical interpretation of a normalized ladder algorithm for adaptive filtering to reduce latency and area of a fully pipelined CORDIC implementation. Ultimately, the goal is to create automatic tools to map applications directly to reconfigurable high-level arithmetic units such as CORDICs.     

CORDIC-lifting factorization of paraunitary filter banks based on the quaternionic multipliers for lossless image coding

Quaternions have offered a new paradigm to the signal processing community: to operate directly in a multidimensional domain. We have recently introduced the quaternionic approach to the design and implementation of paraunitary filter banks: four- and eight-channel linear-phase paraunitary filter banks, including those with pairwise-mirror-image symmetric frequency responses. The hypercomplex number theory is utilized to derive novel lattice structures in which quaternion multipliers replace Givens (planar) rotations. Unlike the conventional algorithms, the proposed computational schemes maintain losslessness regardless of their coefficient quantization. Moreover, the one regularity conditions can be expressed directly in terms of the quaternion lattice coefficients and thus easily satisfied even in finite-precision arithmetic. In this paper, a novel approach to realizing CORDIC-lifting factorization of paraunitary filter banks is presented, which is based on the embedding of the CORDIC algorithm inside the lifting scheme. Lifting allows for making multiplications invertible. The 2D CORDIC engine using sparse iterations and asynchronous pipeline processor architecture based on the embedded CORDIC engine as stage of processor is reported. Also it is necessary to notice, that the quaternion multiplier lifting scheme based on the 2D CORDIC algorithm is the structural decision for the lossless digital signal processing. This approach applies to very practical filter banks, which are essential for image processing, and addresses interesting theoretical questions.     

基于CORDIC算法的数字下变频器

提出一种基CORDIC算法的数字下变频实现方法。首先介绍了CORDIC算法的基本原理，然后讨论了数字下变频中本地数字压控振荡器的CORDIC算法实现。由于采用算法到结构的映射思想，使得该算法能成功地用FPGA来实现，并得到了实践验证。     

A floating-point advanced cordic processor

In this paper, a novel architecture of a floating-point digital signal processor is presented. It introduces a single hardware structure with a full set of elementary arithmetic functions which includessin, cos, tan, arctanh, circular rotation andvectoring, sinh, cosh, tanh, arctanh, hyperbolic rotation andvectoring, square root, logarithm, exponential as well asaddition, multiplication anddivision. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) and the Convergence Computing Method (CCM) algorithms for computing arithmetic functions and it is fully parallel and pipelined. Its advanced functionality is achieved without significant increase in hardware, in comparison to ordinary CORDIC processor, and makes it an ideal processing element in high speed multiprocessor applications, e.g. real time Digital Signal Processing (DSP) and computer graphics.     

M倍降速流水线技术实现正切余切

随着超大规模集成电路（VLSI, Very Large Scale Integrated circuites）技术的飞速发展,经常需要用硬件快速精确地进行三角函数的计算,而坐标旋转算法（CORDIC, Cordinate Rotational Digital Computer）能够将多种难以用硬件电路直接实现的复杂三角函数运算分解为统一的加减、移位操作,极大地降低了硬件设计的复杂性。这里在Circular CORDIC和Linear CORDIC的基础之上,搭建了正切余切模块的计算。介绍了M倍降速递归流水线技术,以及在保证车交II夹运算速度的前提下,如何尽可能减少系统的逻辑资源占用。     

Radix-4 Vectoring CORDIC Algorithm and Architectures

In this work we extend the radix-4 CORDIC algorithm to the vectoring mode (the radix-4 CORDIC algorithm was proposed recently by the authors for the rotation mode). The extension to the vectoring mode is not straightforward, since the digit selection function is more complex in the vectoring case than in the rotation case; as in the rotation mode, the scale factor is not constant. Although the radix-4 CORDIC algorithm in vectoring mode has a similar recurrence as the radix-4 division algorithm, there are specific issues concerning the vectoring algorithm that demand dedicated study. We present the digit selection for nonredundant and redundant arithmetic (following two different approaches: arithmetic comparisons and table look-up), the computation and compensation of the scale factor, and the implementation of the algorithm (with both types of digit selection) in a word-serial architecture. When compared with conventional radix-2 (redundant and non-redundant) architectures, the radix-4 algorithms present a significant speed up for angle calculation. For the computation of the magnitude the speed up is very slight, due to the nonconstant scale factor in the radix-4 algorithm.