用于设计连续时间滤波器的基于混合积分器的双二阶单元

摘要：提出了一种新型基于混合积分器的双二阶单元。与基于源极跟随器的双二阶单元采用正反馈综合复数极点相比,本文提出了另一种综合复数极点的机制。提出的双二阶单元采用负反馈结合不同类型积分器综合复数极点,用于设计连续时滤波器。该单元包括许多优点：电路结构简单、高增益、无寄生极点、不需要共模反馈电路和大的驱动能力。在0.18 μm CMOS 工艺上采用提出的双二阶单元实现了一个4阶巴特沃斯低通滤波器。滤波器包括测试缓冲器有源面积仅为200×170µm。提出的滤波器消耗201µW功耗,获得51dB动态范围。     

用于便携式GPS接收机中的5.4mW低噪声高增益CMOS射频前端电路设计

设计了应用于便携式GPS接收机射频前端中的CMOS低噪声放大器和正交混频器. 该电路中的低噪声放大器采用带源端电感负反馈的输入级,并引入功耗约束下的噪声和输入同时匹配技术. 正交混频器基于吉尔伯特单元. 电路采用TSMC 0.18μm RF CMOS工艺实现,总的电压转换增益为35dB,级联噪声系数为2.4dB,输入1dB压缩点为-22dBm,输入匹配良好,输入回损为-22.3dB, 在1.8V电压供电下,整个全差分电路功耗为5.4mW.     

带内噪声整形连续时间滤波器

提出了一种带内噪声整形连续时间滤波器,详细分析了滤波器的传输特性和噪声整形原理.采用0.18 μm CMOS工艺,设计了一个4阶巴特沃斯型全差分低通滤波器.仿真结果表明,滤波器的带内增益为10 dB, -3 dB频率为4.5 MHz;输出噪声的理论分析与仿真结果一致;在2.5 V电源电压下,消耗电流为0.8 mA, 带外IIP3为25.3 dBV,带外无杂散动态范围为65.3 dB.     

用于便携式GPS接收机中的5.4mW低噪声高增益CMOS射频前端电路设计

设计了应用于便携式GPS接收机射频前端中的CMOS低噪声放大器和正交混频器.该电路中的低噪声放大器采用带源端电感负反馈的输入级,并引入功耗约束下的噪声和输入同时匹配技术.正交混频器基于吉尔伯特单元.电路采用TSMC 0.18μm RFCMOS工艺实现,总的电压转换增益为35dB,级联噪声系数为2.4dB,输入ldB压缩点为-22dBm,输入匹配良好,输入回损为-22.3dB,在1.8V电压供电下,整个全差分电路功耗为5.4mW.     

基于CCII—的电压模式双二阶滤波器设计

本文讨论了利用系统方块图法设计双二阶滤波器的原理,并用２个ＣＣＩＩ－,一个电压跟随器,２个电阻和２个电容构成了极点角频率ωＰ独立可调,品质因素ＱＰ保持常数的电压模式通用双二阶滤波器,该通用滤波器具有低通、高通、带通、全通、陷波五种滤波功能和低的灵敏度。     

GPS接收机镜像信号抑制

分析了GPS接收机镜像信号抑制的要求,设计应用于低中频GPS接收机的镜像抑制复数滤波器.滤波器基于OTA-C双二次结构,通过线性变换实现频率搬移.采用了带源极负反馈的全差分跨导器以扩大输入线性范围.设计了基于环形振荡器的数字调谐锁相环以减小滤波器频率偏差.电路采用0.18μm CMOS工艺实现.测试结果表明,滤波器带宽为3.1MHz,偏移5MHz抑制为50dB,频率修调误差小于±1.5%.镜像抑制大于35dB.1.8V电源电压下滤波器和修正电路电流分别为0.82mA和0.23mA.     

基于双二阶的低功耗椭圆带通滤波器设计

为解决椭圆滤波器通带纹波较大的问题,设计了一种基于双二阶的椭圆窄带带通滤波器,滤波器由3个双二阶构造的带阻滤波器级联实现,滤波器中心频率11kHz,带宽2kHz,通带纹波不超过1dB,阻带衰减不小于30dB每倍频程。滤波器功耗不超过30mW,满足水下引信接收机长时间工作的要求。     

UHF RFID阅读器中可编程全差分低通滤波器的设计

基于TSMC 0.25 μm RF CMOS工艺,提出了一种应用于860～960 MHz UHF波段单片射频识别(RFID)阅读器的可编程全差分低通滤波器电路.该滤波器为6阶切比雪夫有源RC滤波器,其中的运放采用带共模反馈的全平衡差动放大器结构(FBDDA)实现了全差分的缓冲器.仿真结果表明:该电路可以通过3位信号控制位产生截止频率为400 kHz、600 kHz、800 kHz、1 MHz以及1.3 MHz的全差分低通滤波器,1 MHz处的点噪声为20 nV/Hz,1 dB输入压缩点为15 dBm,3.3 V电源电压下电路消耗总电流为4.86 mA.     

一种-100 dB电源抑制比的非带隙基准电压源

该文提出一种非带隙基准电路,通过一个带超级源极跟随器的预调制电路提供一个稳定的电压,为基准核心电路供电。超级源极跟随器通过降低基准核心电路电源端的对地阻抗,有效提高了基准电路的电源抑制能力。该基准电路采用0.35 m CMOS 工艺设计并流片,测试结果表明,该电路的工作电源电压为1.8~5 V,静态电流约为13 A。低频处电源抑制比(PSRR)约等于-100 dB,在小于1 kHz频率范围内PSRR均优于-93 dB。并且其片上面积仅为0.013 mm2。     

一种指数增益控制宽范围可变增益放大器

采用中芯国际(SMIC)0.18μm CMOS工艺设计了一种具有指数增益特性的的宽增益调节范围的可变增益放大器,该放大器由Gilbert单元、指数电压转换电路、直流消除电路及超级源级跟随器组成。经过Cadence仿真验证,该放大器可以实现-11.14dB~30.39dB的增益连续变化,其-3dB带宽为250MHz,控制电压与增益成dB线性关系。     

基于衬底驱动技术的0.8 V三阶椭圆 OTA-C滤波器

基于衬底驱动MOS技术,设计了一种0.8 V高性能全差分CMOS跨导运算放大器(OTA)。在互补输入差分对的衬底端施加信号,避开MOSFET阈值电压的限制,以达到超低压应用。在0.8 V的电源电压下,其直流开环增益为73.8 dB,单位增益带宽为16.4 MHz。基于该OTA,采用无源网络模拟法,设计实现了截止频率为5 MHz,通带波纹为0.5 dB的三阶椭圆OTA-C滤波器。仿真结果表明了所设计滤波器的正确性。     

SOI温度补偿效应的全集成高线性度Gm-C滤波器设计

提出了一种全差分运算放大器,该运算放大器采用电压负反馈方式稳定输出共模电平, 调节输入差分管相应的衬底偏置改变输入对的阈值电压差,从而调节放大器的跨导来调整滤波器的截止频率,这样可以补偿温度变化对滤波器频响造成的漂移。实现了基于Gm-c结构的三阶Chebyshev低通滤波器,该滤波器采用GSMC的0.13um SOI工艺,电源电压1.2v,6层金属设计,仿真结果表明,该滤波器通带增益0dB,-1dB截止频率8MHZ,38MHZ处增益衰减达到-35dB,带内波动0.5dB,输入为1MHZ,400mVpp时,THD为-57dB,,功耗7mW.     

Robust highly linear high-frequency CMOS OTA with IM3 below - 70 dB at 26 MHz

An enhanced configuration for a linearized MOS operational transconductance amplifier (OTA) is proposed. The proposed fully differential OTA circuit is based on resistive source degeneration and an improved adaptive biasing technique. It is robust to process variation, which has not been fully shown in previously reported linearization techniques. Detailed harmonic distortion analysis demonstrating the robustness of the proposed OTA is introduced. The transconductance gain is tunable from 160 to 340 /spl mu/S with a third-order intermodulation (IM3) below -70 dB at 26 MHz. As an application, a 26-MHz second-order low-pass filter fabricated in TSMC 0.35-/spl mu/m CMOS technology with a power supply of 3.3 V is presented. The measured IM3 with an input voltage of 1.4 Vpp is below - 65 dB for the entire filter pass-band, and the input referred noise density is 156nV//spl radic/Hz. The cutoff frequency of the filter is tunable in the range of 13-26 MHz. Theoretical and experimental results are in good agreement.     

AN ANTI-ALIASING FILTER FOR ∑△ ADC

An anti-aliasing filter for ADCs using a combination of active RC and analog FIR filters is presented in this letter. The first order active RC filter is set at 100kHz to minimize the die size and variations of linear phase and gain in 0-4kHz passband. The 2-tap FIR filter provides more than -53dB attenuation at 2MHz 4kHz frequency range. The proposed filter achieved more than -76dB attenuation at sampling frequency with 0.01 phase linearity and 0.02dB gain variation within 0-4kHz bandwidth. The active die area of the fully differential filter is 0.17mm2 in 0.5um CMOS technology. The experimental and simulation results have been obtained and the feasibility of the proposed method is shown.     

AN ANTI-ALIASING FILTER FOR ∑△ ADC

An anti-aliasing filter for ∑△ ADCs using a combination of active RC and analog FIR filters is presented in this letter. The first order active RC filter is set at 100kHz to minimize the die size and variations of linear phase and gain in 0-4kHz passband. The 2-tap FIR filter provides more than -53dB attenuation at 2MHz ±4kHz frequency range. The proposed filter achieved more than -76dB attenuation at sampling frequency with ±0.01° phase linearity and ±0.02dB gain variation within 0-4kHz bandwidth. The active die area of the fully differential filter is 0.17mm2 in 0.5μm CMOS technology. The experimental and simulation results have been obtained and the feasibility of the proposed method is shown.     

A 44-MHz wideband switched-capacitor bandpass filter using double-sampling pseudo-two-path techniques

A fully differential wideband sixth-order switched-capacitor bandpass filter is designed for channel selection in cable TV applications. A modified double-sampling pseudo-two-path technique is proposed to achieve a second-order wideband bandpass filter with a single opamp. Implemented in a standard double-poly four-metal 0.35-/spl mu/m CMOS process and operated at 176-MHz sampling frequency, the filter achieves a measured center frequency of 44 MHz with a bandwidth of 6.28 MHz and a dynamic range of 58.3 dB at 3% IM3. The filter consumes 92.5mW at a single 3.0-V supply and occupies a chip area of 0.52 mm /sup 2/.     

全差分群时延可精确调节的四阶Bessel滤波器实现

采用全差分运算放大器、无源电阻以及用作可变电阻的MOS管设计实现了全差分R-MOSFET-C四阶Bessel有源低通滤波器,在所提出的电路中通过调节工作在线性区的MOS管有源电阻的阻值以抵消集成电路制造工艺过程中电阻阻值的一致性偏差,达到Bessel滤波器的群时延值得到精确设计的目的.该滤波器中所采用的全差分运算放大器不仅具备有电压共模负反馈,而且还具有电流共模负反馈,极有利于电路静态工作点的稳定.通过无源双端RLC原型低通滤波器导出的0.75μs群时延四阶Bessel滤波器,采用台湾联电(UMC)2层多晶硅、2层金属(2P2M)、5.0V电源电压、0.5μm CMOS工艺制造,在输入信号为100kHz、2.5Vpp时,其谐波失真(THD)值低于-65dB.     

全差分可调频率四阶Chebyshev滤波器的实现

提出了一种新的全差分运算放大器,该运算放大器在具有电压共模负反馈的同时还具有电流共模负反馈,能较好地稳定其工作点。通过利用MOS管工作在线性区便能作可变电阻之用的特性,设计实现了基于R-MOSFET-C运放的全差分频率连续调节的四阶Chebyshev低通滤波器。该滤波器采用台湾联电(UMC)2层多晶硅、2层金属(2P2M)5V电源电压、0.5m CMOS工艺生产制造。其芯片面积大小为0.36mm~2,截止频率调节范围为20kHz到420kHz,输入信号频率在100kHz,2.5Vpp时的失真小于-65dB,功耗仅为16mW。     

用对数域电流模式积分器实现的高频集成滤波器

文本提出了全差动对数域电流模式积分器．该积分器的时间常数受参考偏流控制,其直流增益可达60dB,在高频它具有比较平坦的相频特性。用该积分器设计的二阶滤波器和1dB波纹五阶Chebyshev低通滤波器,计算机仿真显示,“实际”频响特性几乎是理想的．且频率可在很宽的范围内调控．这种滤波器具有很低的THD。     

A CMOS finite impulse response filter with a crossover traveling wave topology for equalization up to 30 Gb/s

This paper describes a fully differential 3-tap finite impulse response filter in 90-nm CMOS. A traditional traveling wave filter topology is modified to alleviate its inherent delay-bandwidth-gain tradeoffs. Each tap gain is comprised of two transconductors whose outputs superimpose with the same group delay, similar to a distributed amplifier. This doubles the bandwidth of the filter for a given tap spacing and gain. Digital control is provided for the tap gains, an integrated pre-amplifier, and tuning varactors. Coupled differential spirals are used in the delay lines to help the design fit into an area 600 /spl mu/m/spl times/500 /spl mu/m. A 1-V supply voltage and 25-mW power consumption are enabled by the use of parallel differential pairs for sign control of the transconductances instead of Gilbert cell amplifiers. The input return loss is better than 16 dB and the output return loss is better than 9 dB up to 30 GHz. Equalization of NRZ data over a coaxial cable channel was demonstrated up to 30 Gb/s, making it faster than any previously reported CMOS equalizer.